When loading the TRD response, keep the pointer to the old root directory to stay...
[u/mrichter/AliRoot.git] / TRD / AliTRDptrgParamConfigurationFile.txt
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f9720615 1#
2# Pre-trigger run time parameter example file
3# which should be generated by PVSS tag editor panels
4#
5
6# Configuration infos
7TAG 120
8REVISION 123
9TIMESTAMP/CREATION YYYY-MM-DD hh:mm:ss
10TIMESTAMP/LASTUPDATE YYYY-MM-DD hh:mm:ss
11COMMENT example configuration (2010-03-31) changes according to PT meeting
12
13# TLMU input masks
14TLMU/IMASK/SEC00 1111_1111_1111_1111_1111_1111_1111_1111
15TLMU/IMASK/SEC01 1111_1111_1111_1111_1111_1111_1111_1111
16TLMU/IMASK/SEC02 1111_1111_1111_1111_1111_1111_1111_1111
17TLMU/IMASK/SEC03 1111_1111_1111_1111_1111_1111_1111_1111
18TLMU/IMASK/SEC04 1111_1111_1111_1111_1111_1111_1111_1111
19TLMU/IMASK/SEC05 1111_1111_1111_1111_1111_1111_1111_1111
20TLMU/IMASK/SEC06 1111_1111_1111_1111_1111_1111_1111_1111
21TLMU/IMASK/SEC07 1111_1111_1111_1111_1111_1111_1111_1111
22TLMU/IMASK/SEC08 1111_1111_1111_1111_1111_1111_1111_1111
23TLMU/IMASK/SEC09 1111_1111_1111_1111_1111_1111_1111_1111
24TLMU/IMASK/SEC10 1111_1111_1111_1111_1111_1111_1111_1111
25TLMU/IMASK/SEC11 1111_1111_1111_1111_1111_1111_1111_1111
26TLMU/IMASK/SEC12 1111_1111_1111_1111_1111_1111_1111_1111
27TLMU/IMASK/SEC13 1111_1111_1111_1111_1111_1111_1111_1111
28TLMU/IMASK/SEC14 1111_1111_1111_1111_1111_1111_1111_1111
29TLMU/IMASK/SEC15 1111_1111_1111_1111_1111_1111_1111_1111
30TLMU/IMASK/SEC17 1111_1111_1111_1111_1111_1111_1111_1111
31
32# How long input if stretched. Value can be 0 to 3
33TLMU/STRETCH 1
34
35# Coincidence matrices set (there are three) (if not set, not activated)
36
37TLMU/CMATRIX0/SEC00 00_0000_0010_0000_0001
38TLMU/CMATRIX0/SEC01 00_0000_0100_0000_0010
39TLMU/CMATRIX0/SEC02 00_0000_1000_0000_0100
40TLMU/CMATRIX0/SEC03 00_0001_0000_0000_1000
41TLMU/CMATRIX0/SEC04 00_0010_0000_0001_0000
42TLMU/CMATRIX0/SEC05 00_0100_0000_0010_0000
43TLMU/CMATRIX0/SEC06 00_1000_0000_0100_0000
44TLMU/CMATRIX0/SEC07 01_0000_0000_1000_0000
45TLMU/CMATRIX0/SEC08 10_0000_0001_0000_0000
46
47TLMU/CMATRIX1/SEC00 00_0000_0111_0000_0001
48TLMU/CMATRIX1/SEC01 00_0000_1110_0000_0010
49TLMU/CMATRIX1/SEC02 00_0001_1100_0000_0100
50TLMU/CMATRIX1/SEC03 00_0011_1000_0000_1000
51TLMU/CMATRIX1/SEC04 00_0111_0000_0001_0000
52TLMU/CMATRIX1/SEC05 00_1110_0000_0010_0000
53TLMU/CMATRIX1/SEC06 01_1100_0000_0100_0000
54TLMU/CMATRIX1/SEC07 11_1000_0000_1000_0000
55TLMU/CMATRIX1/SEC08 11_0000_0001_0000_0001
56TLMU/CMATRIX1/SEC09 10_0000_0010_0000_0011
57TLMU/CMATRIX1/SEC10 00_0000_0100_0000_0111
58TLMU/CMATRIX1/SEC11 00_0000_1000_0000_1110
59TLMU/CMATRIX1/SEC12 00_0001_0000_0001_1100
60TLMU/CMATRIX1/SEC13 00_0010_0000_0011_1000
61TLMU/CMATRIX1/SEC14 00_0100_0000_0111_0000
62TLMU/CMATRIX1/SEC15 00_1000_0000_1110_0000
63TLMU/CMATRIX1/SEC16 01_0000_0001_1100_0000
64TLMU/CMATRIX1/SEC17 10_0000_0011_1000_0000
65
66
67TLMU/CMATRIX2/SEC00 00_0000_1111_1000_0001
68TLMU/CMATRIX2/SEC01 00_0001_1111_0000_0010
69TLMU/CMATRIX2/SEC02 00_0011_1110_0000_0100
70TLMU/CMATRIX2/SEC03 00_0111_1100_0000_1000
71TLMU/CMATRIX2/SEC04 00_1111_1000_0001_0000
72TLMU/CMATRIX2/SEC05 01_1111_0000_0010_0000
73TLMU/CMATRIX2/SEC06 11_1110_0000_0100_0000
74TLMU/CMATRIX2/SEC07 11_1100_0000_1000_0001
75TLMU/CMATRIX2/SEC08 11_1000_0001_0000_0011
76TLMU/CMATRIX2/SEC09 11_0000_0010_0000_0111
77TLMU/CMATRIX2/SEC10 10_0000_0100_0000_1111
78TLMU/CMATRIX2/SEC11 00_0000_1000_0001_1111
79TLMU/CMATRIX2/SEC12 00_0001_0000_0011_1110
80TLMU/CMATRIX2/SEC13 00_0010_0000_0111_1100
81TLMU/CMATRIX2/SEC14 00_0100_0000_1111_1000
82TLMU/CMATRIX2/SEC15 00_1000_0001_1111_0000
83TLMU/CMATRIX2/SEC16 01_0000_0011_1110_0000
84TLMU/CMATRIX2/SEC17 10_0000_0111_1100_0000
85
86
87# Multiplicity counter setup (where to slice) .
88# there are 9 slices with lower and upper thresholds
89TLMU/MCNTR0/THR 5 20
90TLMU/MCNTR1/THR 20 100
91TLMU/MCNTR2/THR 100 200
92TLMU/MCNTR3/THR 200 300
93TLMU/MCNTR4/THR 300 400
94TLMU/MCNTR5/THR 400 500
95TLMU/MCNTR6/THR 500 520
e51605d9 96TLMU/MCNTR7/THR 520 576
97TLMU/MCNTR8/THR 1 576
f9720615 98
99
100# Assign signal to output. CM means CMATRIX and MC means Multiplicity counter
101# SEQ [0..4] means trigger sequencer. NONE will not assign anything
102#
103# channel 0 1 2 3 4 5 6 7
104TLMU/OUTMUX CM1 MC2 MC3 MC4 MC5 MC6 MC7 MC8
105
106# FEBs
107
108# basically thresholds and delay (T0 has 12 channels, and V0 has 8 channels)
109# V0 has 4 sections named V0, V1, V2, V3
110# Delay is 0 to 31, with 1/4 BC precision (max delay is then 8 BCs)
111# The value can take here is from 0 to 255 for threshold and 0 to 31 for delay
112
113FEB/T0/A/THR 10 10 10 10 10 10 10 10 10 10 10 10
114FEB/T0/A/DELAY 1 1 1 1 1 1 1 1 1 1 1 1
115FEB/T0/C/THR 10 10 10 10 10 10 10 10 10 10 10 10
116FEB/T0/C/DELAY 1 1 1 1 1 1 1 1 1 1 1 1
117
118FEB/V0/A0/THR 10 10 10 10 10 10 10 10
119FEB/V0/A1/THR 10 10 10 10 10 10 10 10
120FEB/V0/A2/THR 10 10 10 10 10 10 10 10
121FEB/V0/A3/THR 10 10 10 10 10 10 10 10
122
123FEB/V0/A0/DELAY 1 1 1 1 1 1 1 1
124FEB/V0/A1/DELAY 1 1 1 1 1 1 1 1
125FEB/V0/A2/DELAY 1 1 1 1 1 1 1 1
126FEB/V0/A3/DELAY 1 1 1 1 1 1 1 1
127
128FEB/V0/C0/THR 10 10 10 10 10 10 10 10
129FEB/V0/C1/THR 10 10 10 10 10 10 10 10
130FEB/V0/C2/THR 10 10 10 10 10 10 10 10
131FEB/V0/C3/THR 10 10 10 10 10 10 10 10
132
133FEB/V0/C0/DELAY 1 1 1 1 1 1 1 1
134FEB/V0/C1/DELAY 1 1 1 1 1 1 1 1
135FEB/V0/C2/DELAY 1 1 1 1 1 1 1 1
136FEB/V0/C3/DELAY 1 1 1 1 1 1 1 1
137
138# Lookup table at FEB
139
140FEB/T0/A/LUT/0 M(1111_1111_1111)>0 # maybe also logical equations
141FEB/T0/A/LUT/1 M(1111_1111_1111)>4
142
143FEB/V0/A0/LUT/0 M(1111_1111)>0
144FEB/V0/A0/LUT/1 M(1111_1111)>2
145FEB/V0/A1/LUT/0 M(1111_1111)>0
146FEB/V0/A1/LUT/1 M(1111_1111)>2
147FEB/V0/A2/LUT/0 M(1111_1111)>0
148FEB/V0/A2/LUT/1 M(1111_1111)>2
149FEB/V0/A3/LUT/0 M(1111_1111)>0
150FEB/V0/A3/LUT/1 M(1111_1111)>2
151
152FEB/T0/C/LUT/0 M(1111_1111_1111)>0
153FEB/T0/C/LUT/1 M(1111_1111_1111)>4
154
155FEB/V0/C0/LUT/0 M(1111_1111)>0
156FEB/V0/C0/LUT/1 M(1111_1111)>2
157FEB/V0/C1/LUT/0 M(1111_1111)>0
158FEB/V0/C1/LUT/1 M(1111_1111)>2
159FEB/V0/C2/LUT/0 M(1111_1111)>0
160FEB/V0/C2/LUT/1 M(1111_1111)>2
161FEB/V0/C3/LUT/0 M(1111_1111)>0
162FEB/V0/C3/LUT/1 M(1111_1111)>2
163
164# Lookup table at CB-AC
165
166CBA/LUT/0 T0_0 || ( V0-0_0 || V0-1_0 || V0-2_0 || V0-3_0 )
167CBA/LUT/1 !T0_1 && !V0-0_1 && !V0-1_1 && !V0-2_1 && !V0-3_1
168
169CBC/LUT/0 T0_0 || ( V0-0_0 || V0-1_0 || V0-2_0 || V0-3_0 )
170CBC/LUT/1 !T0_1 && !V0-0_1 && !V0-1_1 && !V0-2_1 && !V0-3_1
171
172# Lookup table at CB-B
173
e51605d9 174CBB/LUT/0 ( CB-A_1 || CB-C_1 ) && TLMU_7
175CBB/LUT/1 ( CB-A_1 && CB-C_1 ) && TLMU_7
f9720615 176
177# Timing parameter for trigger processor
178
179CBB/TRG/L0A 43 # comment
180CBB/TRG/L0S 47
181CBB/TRG/L1A 308
182CBB/TRG/L1S 311
183CBB/TRG/DEAD/PT 200
184CBB/TRG/DEAD/L0 350
185CBB/TRG/DEAD/L1 500
186CBB/TRG/DELAY/L0 46
187
188CBB/TRG/CTRL/SM_TO_CTP YES
189CBB/TRG/CTRL/TRG_EMU YES
190CBB/TRG/CTRL/A/VALUE 0
191CBB/TRG/CTRL/A/OVR NO
192CBB/TRG/CTRL/B/VALUE 0
193CBB/TRG/CTRL/B/OVR NO
194
195CBB/TRG/A/DIS YES # do not change!
196
197CBB/TRG/TIN/0 0 # normal triggering (should be 0!)
198CBB/TRG/TIN/1 0 # normal triggering (should be 0!)
199
200CBB/PT/CBA/SAMPL 0
201CBB/PT/CBC/SAMPL 0
202
203
204CBB/PT/ALIGN/CB-A_0/STRETCH 0
205CBB/PT/ALIGN/CB-A_0/DELAY 0
206CBB/PT/ALIGN/CB-A_1/STRETCH 0
207CBB/PT/ALIGN/CB-A_1/DELAY 0
208CBB/PT/ALIGN/CB-C_0/STRETCH 0
209CBB/PT/ALIGN/CB-C_0/DELAY 0
210CBB/PT/ALIGN/CB-C_1/STRETCH 0
211CBB/PT/ALIGN/CB-C_1/DELAY 0
212CBB/PT/ALIGN/RND/STRETCH 0
213CBB/PT/ALIGN/RND/DELAY 0
214CBB/PT/ALIGN/BC/STRETCH 0
215CBB/PT/ALIGN/BC/DELAY 0
216CBB/PT/ALIGN/TLMU_0/STRETCH 0
217CBB/PT/ALIGN/TLMU_0/DELAY 0
218CBB/PT/ALIGN/TLMU_1/STRETCH 0
219CBB/PT/ALIGN/TLMU_1/DELAY 0
220CBB/PT/ALIGN/TLMU_2/STRETCH 0
221CBB/PT/ALIGN/TLMU_2/DELAY 0
222CBB/PT/ALIGN/TLMU_3/STRETCH 0
223CBB/PT/ALIGN/TLMU_3/DELAY 0
224CBB/PT/ALIGN/TLMU_4/STRETCH 0
225CBB/PT/ACBB/LIGN/TLMU_4/DELAY 0
226CBB/PT/ALIGN/TLMU_5/STRETCH 0
227CBB/PT/ALIGN/TLMU_5/DELAY 0
228CBB/PT/ALIGN/TLMU_6/STRETCH 0
229CBB/PT/ALIGN/TLMU_6/DELAY 0
230CBB/PT/ALIGN/TLMU_7/STRETCH 0
231CBB/PT/ALIGN/TLMU_7/DELAY 0
232CBB/PT/ALIGN/CB-B_0/STRETCH 0
233CBB/PT/ALIGN/CB-B_0/DELAY 0
234CBB/PT/ALIGN/CB-B_1/STRETCH 0
235CBB/PT/ALIGN/CB-B_1/DELAY 0
236
237CBB/BUSY/CTRL 0
238
239CBB/RND/THR 150000
240CBB/BC/RESET_VALUE 222
241
242CBB/PT/MASK/CB-A_0 YES
243CBB/PT/MASK/CB-A_1 YES
244CBB/PT/MASK/CB-C_0 YES
245CBB/PT/MASK/CB-C_1 YES
246CBB/PT/MASK/RND YES
247CBB/PT/MASK/BC YES
248CBB/PT/MASK/TLMU_0 YES
249CBB/PT/MASK/TLMU_1 YES
250CBB/PT/MASK/TLMU_2 YES
251CBB/PT/MASK/TLMU_3 YES
252CBB/PT/MASK/TLMU_4 YES
253CBB/PT/MASK/TLMU_5 YES
254CBB/PT/MASK/TLMU_6 YES
255CBB/PT/MASK/TLMU_7 YES
256CBB/PT/MASK/CB-B_0 YES
257CBB/PT/MASK/CB-B_1 YES
258
259# EOF