Version where the process for HLT and vdrift on DAQ are off(Raphaelle)
[u/mrichter/AliRoot.git] / TRD / AliTRDtrapConfig.cxx
CommitLineData
36dc3337 1/**************************************************************************
2 * Copyright(c) 1998-1999, ALICE Experiment at CERN, All rights reserved. *
3 * *
4 * Author: The ALICE Off-line Project. *
5 * Contributors are mentioned in the code where appropriate. *
6 * *
7 * Permission to use, copy, modify and distribute this software and its *
8 * documentation strictly for non-commercial purposes is hereby granted *
9 * without fee, provided that the above copyright notice appears in all *
10 * copies and that both the copyright notice and this permission notice *
11 * appear in the supporting documentation. The authors make no claims *
12 * about the suitability of this software for any purpose. It is *
13 * provided "as is" without express or implied warranty. *
14 **************************************************************************/
15
16////////////////////////////////////////////////////////////////////////////
17// //
18// TRAP config //
19// //
20// Author: J. Klein (Jochen.Klein@cern.ch) //
21// //
22////////////////////////////////////////////////////////////////////////////
23
ce4786b9 24#include "AliLog.h"
25
26#include "AliTRDgeometry.h"
27#include "AliTRDfeeParam.h"
28#include "AliTRDtrapConfig.h"
29
30#include <fstream>
31#include <iostream>
32#include <iomanip>
33
2b2b540f 34const Int_t AliTRDtrapConfig::AliTRDtrapValue::fgkSize[] = {
35 0,
36 1,
37 540,
38 1080,
39 8*18*540,
40 4,
41 6,
42 8*18*30
43};
44Bool_t AliTRDtrapConfig::fgRegAddressMapInitialized = kFALSE;
45AliTRDtrapConfig::TrapReg_t AliTRDtrapConfig::fgRegAddressMap[] = { };
46const Int_t AliTRDtrapConfig::fgkRegisterAddressBlockStart[] = { 0x0a00, 0x3000, 0xd000 };
47const Int_t AliTRDtrapConfig::fgkRegisterAddressBlockSize[] = { 0x0400, 0x0200, 0x0004 };
48
49AliTRDtrapConfig::AliTRDtrapConfig(const TString &name, const TString &title) :
50 TNamed(name, title)
ce4786b9 51{
2b2b540f 52 // default constructor
051af255 53
2b2b540f 54 // initialize and reset the TRAP registers
ce4786b9 55 InitRegs();
2b2b540f 56 ResetRegs();
ce4786b9 57
2b2b540f 58 for (Int_t iWord = 0; iWord < fgkDmemWords; ++iWord) {
59 fDmem[iWord].SetAddress(iWord + fgkDmemStartAddress);
ce4786b9 60 }
61
2b2b540f 62 // initialize the map from address to register
63 if (!fgRegAddressMapInitialized) {
64 for (Int_t iReg = 0; iReg < kLastReg; iReg++) {
65 Int_t addr = fRegisterValue[iReg].GetAddr();
66 if (addr < fgkRegisterAddressBlockStart[0]) {
67 AliError(Form("Register address 0x%04x not handled in register map", addr));
68 }
69 else if (addr < fgkRegisterAddressBlockStart[0] + fgkRegisterAddressBlockSize[0]) {
70 fgRegAddressMap[addr - fgkRegisterAddressBlockStart[0]] = (TrapReg_t) iReg;
71 }
72 else if (addr < fgkRegisterAddressBlockStart[1]) {
73 AliError(Form("Register address 0x%04x not handled in register map", addr));
74 }
75 else if (addr < fgkRegisterAddressBlockStart[1] + fgkRegisterAddressBlockSize[1]) {
76 fgRegAddressMap[addr - fgkRegisterAddressBlockStart[1] + fgkRegisterAddressBlockSize[0]] = (TrapReg_t) iReg;
77 }
78 else if (addr < fgkRegisterAddressBlockStart[2]) {
79 AliError(Form("Register address 0x%04x not handled in register map", addr));
80 }
81 else if (addr < fgkRegisterAddressBlockStart[2] + fgkRegisterAddressBlockSize[2]) {
6170d369 82 Int_t ind = addr - fgkRegisterAddressBlockStart[2] + fgkRegisterAddressBlockSize[1] + fgkRegisterAddressBlockSize[0];
83 fgRegAddressMap[ind] = (TrapReg_t) iReg;
2b2b540f 84 }
85 else {
86 AliError(Form("Register address 0x%04x not handled in register map", addr));
87 }
88 }
89 fgRegAddressMapInitialized = kTRUE;
90 }
ce4786b9 91}
92
93
051af255 94AliTRDtrapConfig::~AliTRDtrapConfig()
95{
6419bebb 96 // destructor
051af255 97}
98
99
8ea391e3 100void AliTRDtrapConfig::InitRegs()
ce4786b9 101{
2b2b540f 102 // initialize all TRAP registers
ce4786b9 103
2b2b540f 104 // Name Address Nbits Reset Value
105 fRegisterValue[kSML0] .Init("SML0", 0x0A00, 15, 0x4050 ); // Global state machine
106 fRegisterValue[kSML1] .Init("SML1", 0x0A01, 15, 0x4200 );
107 fRegisterValue[kSML2] .Init("SML2", 0x0A02, 15, 0x4384 );
108 fRegisterValue[kSMMODE] .Init("SMMODE", 0x0A03, 16, 0xF0E2 );
109 fRegisterValue[kSMCMD] .Init("SMCMD", 0x0A04, 16, 0x0000 );
110 fRegisterValue[kNITM0] .Init("NITM0", 0x0A08, 14, 0x3FFF );
111 fRegisterValue[kNITM1] .Init("NITM1", 0x0A09, 14, 0x3FFF );
112 fRegisterValue[kNITM2] .Init("NITM2", 0x0A0A, 14, 0x3FFF );
113 fRegisterValue[kNIP4D] .Init("NIP4D", 0x0A0B, 7, 0x7F );
114 fRegisterValue[kCPU0CLK] .Init("CPU0CLK", 0x0A20, 5, 0x07 );
115 fRegisterValue[kCPU1CLK] .Init("CPU1CLK", 0x0A22, 5, 0x07 );
116 fRegisterValue[kCPU2CLK] .Init("CPU2CLK", 0x0A24, 5, 0x07 );
117 fRegisterValue[kCPU3CLK] .Init("CPU3CLK", 0x0A26, 5, 0x07 );
118 fRegisterValue[kNICLK] .Init("NICLK", 0x0A28, 5, 0x07 );
119 fRegisterValue[kFILCLK] .Init("FILCLK", 0x0A2A, 5, 0x07 );
120 fRegisterValue[kPRECLK] .Init("PRECLK", 0x0A2C, 5, 0x07 );
121 fRegisterValue[kADCEN] .Init("ADCEN", 0x0A2E, 5, 0x07 );
122 fRegisterValue[kNIODE] .Init("NIODE", 0x0A30, 5, 0x07 );
123 fRegisterValue[kNIOCE] .Init("NIOCE", 0x0A32, 6, 0x21 ); // bit 5 is status bit (read-only)!
124 fRegisterValue[kNIIDE] .Init("NIIDE", 0x0A34, 5, 0x07 );
125 fRegisterValue[kNIICE] .Init("NIICE", 0x0A36, 5, 0x07 );
126 fRegisterValue[kARBTIM] .Init("ARBTIM", 0x0A3F, 4, 0x0 ); // Arbiter
127 fRegisterValue[kIA0IRQ0] .Init("IA0IRQ0", 0x0B00, 12, 0x000 ); // IVT of CPU0
128 fRegisterValue[kIA0IRQ1] .Init("IA0IRQ1", 0x0B01, 12, 0x000 );
129 fRegisterValue[kIA0IRQ2] .Init("IA0IRQ2", 0x0B02, 12, 0x000 );
130 fRegisterValue[kIA0IRQ3] .Init("IA0IRQ3", 0x0B03, 12, 0x000 );
131 fRegisterValue[kIA0IRQ4] .Init("IA0IRQ4", 0x0B04, 12, 0x000 );
132 fRegisterValue[kIA0IRQ5] .Init("IA0IRQ5", 0x0B05, 12, 0x000 );
133 fRegisterValue[kIA0IRQ6] .Init("IA0IRQ6", 0x0B06, 12, 0x000 );
134 fRegisterValue[kIA0IRQ7] .Init("IA0IRQ7", 0x0B07, 12, 0x000 );
135 fRegisterValue[kIA0IRQ8] .Init("IA0IRQ8", 0x0B08, 12, 0x000 );
136 fRegisterValue[kIA0IRQ9] .Init("IA0IRQ9", 0x0B09, 12, 0x000 );
137 fRegisterValue[kIA0IRQA] .Init("IA0IRQA", 0x0B0A, 12, 0x000 );
138 fRegisterValue[kIA0IRQB] .Init("IA0IRQB", 0x0B0B, 12, 0x000 );
139 fRegisterValue[kIA0IRQC] .Init("IA0IRQC", 0x0B0C, 12, 0x000 );
140 fRegisterValue[kIRQSW0] .Init("IRQSW0", 0x0B0D, 13, 0x1FFF );
141 fRegisterValue[kIRQHW0] .Init("IRQHW0", 0x0B0E, 13, 0x0000 );
142 fRegisterValue[kIRQHL0] .Init("IRQHL0", 0x0B0F, 13, 0x0000 );
143 fRegisterValue[kIA1IRQ0] .Init("IA1IRQ0", 0x0B20, 12, 0x000 ); // IVT of CPU1
144 fRegisterValue[kIA1IRQ1] .Init("IA1IRQ1", 0x0B21, 12, 0x000 );
145 fRegisterValue[kIA1IRQ2] .Init("IA1IRQ2", 0x0B22, 12, 0x000 );
146 fRegisterValue[kIA1IRQ3] .Init("IA1IRQ3", 0x0B23, 12, 0x000 );
147 fRegisterValue[kIA1IRQ4] .Init("IA1IRQ4", 0x0B24, 12, 0x000 );
148 fRegisterValue[kIA1IRQ5] .Init("IA1IRQ5", 0x0B25, 12, 0x000 );
149 fRegisterValue[kIA1IRQ6] .Init("IA1IRQ6", 0x0B26, 12, 0x000 );
150 fRegisterValue[kIA1IRQ7] .Init("IA1IRQ7", 0x0B27, 12, 0x000 );
151 fRegisterValue[kIA1IRQ8] .Init("IA1IRQ8", 0x0B28, 12, 0x000 );
152 fRegisterValue[kIA1IRQ9] .Init("IA1IRQ9", 0x0B29, 12, 0x000 );
153 fRegisterValue[kIA1IRQA] .Init("IA1IRQA", 0x0B2A, 12, 0x000 );
154 fRegisterValue[kIA1IRQB] .Init("IA1IRQB", 0x0B2B, 12, 0x000 );
155 fRegisterValue[kIA1IRQC] .Init("IA1IRQC", 0x0B2C, 12, 0x000 );
156 fRegisterValue[kIRQSW1] .Init("IRQSW1", 0x0B2D, 13, 0x1FFF );
157 fRegisterValue[kIRQHW1] .Init("IRQHW1", 0x0B2E, 13, 0x0000 );
158 fRegisterValue[kIRQHL1] .Init("IRQHL1", 0x0B2F, 13, 0x0000 );
159 fRegisterValue[kIA2IRQ0] .Init("IA2IRQ0", 0x0B40, 12, 0x000 ); // IVT of CPU2
160 fRegisterValue[kIA2IRQ1] .Init("IA2IRQ1", 0x0B41, 12, 0x000 );
161 fRegisterValue[kIA2IRQ2] .Init("IA2IRQ2", 0x0B42, 12, 0x000 );
162 fRegisterValue[kIA2IRQ3] .Init("IA2IRQ3", 0x0B43, 12, 0x000 );
163 fRegisterValue[kIA2IRQ4] .Init("IA2IRQ4", 0x0B44, 12, 0x000 );
164 fRegisterValue[kIA2IRQ5] .Init("IA2IRQ5", 0x0B45, 12, 0x000 );
165 fRegisterValue[kIA2IRQ6] .Init("IA2IRQ6", 0x0B46, 12, 0x000 );
166 fRegisterValue[kIA2IRQ7] .Init("IA2IRQ7", 0x0B47, 12, 0x000 );
167 fRegisterValue[kIA2IRQ8] .Init("IA2IRQ8", 0x0B48, 12, 0x000 );
168 fRegisterValue[kIA2IRQ9] .Init("IA2IRQ9", 0x0B49, 12, 0x000 );
169 fRegisterValue[kIA2IRQA] .Init("IA2IRQA", 0x0B4A, 12, 0x000 );
170 fRegisterValue[kIA2IRQB] .Init("IA2IRQB", 0x0B4B, 12, 0x000 );
171 fRegisterValue[kIA2IRQC] .Init("IA2IRQC", 0x0B4C, 12, 0x000 );
172 fRegisterValue[kIRQSW2] .Init("IRQSW2", 0x0B4D, 13, 0x1FFF );
173 fRegisterValue[kIRQHW2] .Init("IRQHW2", 0x0B4E, 13, 0x0000 );
174 fRegisterValue[kIRQHL2] .Init("IRQHL2", 0x0B4F, 13, 0x0000 );
175 fRegisterValue[kIA3IRQ0] .Init("IA3IRQ0", 0x0B60, 12, 0x000 ); // IVT of CPU3
176 fRegisterValue[kIA3IRQ1] .Init("IA3IRQ1", 0x0B61, 12, 0x000 );
177 fRegisterValue[kIA3IRQ2] .Init("IA3IRQ2", 0x0B62, 12, 0x000 );
178 fRegisterValue[kIA3IRQ3] .Init("IA3IRQ3", 0x0B63, 12, 0x000 );
179 fRegisterValue[kIA3IRQ4] .Init("IA3IRQ4", 0x0B64, 12, 0x000 );
180 fRegisterValue[kIA3IRQ5] .Init("IA3IRQ5", 0x0B65, 12, 0x000 );
181 fRegisterValue[kIA3IRQ6] .Init("IA3IRQ6", 0x0B66, 12, 0x000 );
182 fRegisterValue[kIA3IRQ7] .Init("IA3IRQ7", 0x0B67, 12, 0x000 );
183 fRegisterValue[kIA3IRQ8] .Init("IA3IRQ8", 0x0B68, 12, 0x000 );
184 fRegisterValue[kIA3IRQ9] .Init("IA3IRQ9", 0x0B69, 12, 0x000 );
185 fRegisterValue[kIA3IRQA] .Init("IA3IRQA", 0x0B6A, 12, 0x000 );
186 fRegisterValue[kIA3IRQB] .Init("IA3IRQB", 0x0B6B, 12, 0x000 );
187 fRegisterValue[kIA3IRQC] .Init("IA3IRQC", 0x0B6C, 12, 0x000 );
188 fRegisterValue[kIRQSW3] .Init("IRQSW3", 0x0B6D, 13, 0x1FFF );
189 fRegisterValue[kIRQHW3] .Init("IRQHW3", 0x0B6E, 13, 0x0000 );
190 fRegisterValue[kIRQHL3] .Init("IRQHL3", 0x0B6F, 13, 0x0000 );
191 fRegisterValue[kCTGDINI] .Init("CTGDINI", 0x0B80, 32, 0x00000000 ); // Global Counter/Timer
192 fRegisterValue[kCTGCTRL] .Init("CTGCTRL", 0x0B81, 12, 0xE3F );
193 fRegisterValue[kC08CPU0] .Init("C08CPU0", 0x0C00, 32, 0x00000000 ); // CPU constants
194 fRegisterValue[kC09CPU0] .Init("C09CPU0", 0x0C01, 32, 0x00000000 );
195 fRegisterValue[kC10CPU0] .Init("C10CPU0", 0x0C02, 32, 0x00000000 );
196 fRegisterValue[kC11CPU0] .Init("C11CPU0", 0x0C03, 32, 0x00000000 );
197 fRegisterValue[kC12CPUA] .Init("C12CPUA", 0x0C04, 32, 0x00000000 );
198 fRegisterValue[kC13CPUA] .Init("C13CPUA", 0x0C05, 32, 0x00000000 );
199 fRegisterValue[kC14CPUA] .Init("C14CPUA", 0x0C06, 32, 0x00000000 );
200 fRegisterValue[kC15CPUA] .Init("C15CPUA", 0x0C07, 32, 0x00000000 );
201 fRegisterValue[kC08CPU1] .Init("C08CPU1", 0x0C08, 32, 0x00000000 );
202 fRegisterValue[kC09CPU1] .Init("C09CPU1", 0x0C09, 32, 0x00000000 );
203 fRegisterValue[kC10CPU1] .Init("C10CPU1", 0x0C0A, 32, 0x00000000 );
204 fRegisterValue[kC11CPU1] .Init("C11CPU1", 0x0C0B, 32, 0x00000000 );
205 fRegisterValue[kC08CPU2] .Init("C08CPU2", 0x0C10, 32, 0x00000000 );
206 fRegisterValue[kC09CPU2] .Init("C09CPU2", 0x0C11, 32, 0x00000000 );
207 fRegisterValue[kC10CPU2] .Init("C10CPU2", 0x0C12, 32, 0x00000000 );
208 fRegisterValue[kC11CPU2] .Init("C11CPU2", 0x0C13, 32, 0x00000000 );
209 fRegisterValue[kC08CPU3] .Init("C08CPU3", 0x0C18, 32, 0x00000000 );
210 fRegisterValue[kC09CPU3] .Init("C09CPU3", 0x0C19, 32, 0x00000000 );
211 fRegisterValue[kC10CPU3] .Init("C10CPU3", 0x0C1A, 32, 0x00000000 );
212 fRegisterValue[kC11CPU3] .Init("C11CPU3", 0x0C1B, 32, 0x00000000 );
213 fRegisterValue[kNMOD] .Init("NMOD", 0x0D40, 6, 0x08 ); // NI interface
214 fRegisterValue[kNDLY] .Init("NDLY", 0x0D41, 30, 0x24924924 );
215 fRegisterValue[kNED] .Init("NED", 0x0D42, 16, 0xA240 );
216 fRegisterValue[kNTRO] .Init("NTRO", 0x0D43, 18, 0x3FFFC );
217 fRegisterValue[kNRRO] .Init("NRRO", 0x0D44, 18, 0x3FFFC );
218 fRegisterValue[kNES] .Init("NES", 0x0D45, 32, 0x00000000 );
219 fRegisterValue[kNTP] .Init("NTP", 0x0D46, 32, 0x0000FFFF );
220 fRegisterValue[kNBND] .Init("NBND", 0x0D47, 16, 0x6020 );
221 fRegisterValue[kNP0] .Init("NP0", 0x0D48, 11, 0x44C );
222 fRegisterValue[kNP1] .Init("NP1", 0x0D49, 11, 0x44C );
223 fRegisterValue[kNP2] .Init("NP2", 0x0D4A, 11, 0x44C );
224 fRegisterValue[kNP3] .Init("NP3", 0x0D4B, 11, 0x44C );
225 fRegisterValue[kNCUT] .Init("NCUT", 0x0D4C, 32, 0xFFFFFFFF );
226 fRegisterValue[kTPPT0] .Init("TPPT0", 0x3000, 7, 0x01 ); // Filter and Preprocessor
227 fRegisterValue[kTPFS] .Init("TPFS", 0x3001, 7, 0x05 );
228 fRegisterValue[kTPFE] .Init("TPFE", 0x3002, 7, 0x14 );
229 fRegisterValue[kTPPGR] .Init("TPPGR", 0x3003, 7, 0x15 );
230 fRegisterValue[kTPPAE] .Init("TPPAE", 0x3004, 7, 0x1E );
231 fRegisterValue[kTPQS0] .Init("TPQS0", 0x3005, 7, 0x00 );
232 fRegisterValue[kTPQE0] .Init("TPQE0", 0x3006, 7, 0x0A );
233 fRegisterValue[kTPQS1] .Init("TPQS1", 0x3007, 7, 0x0B );
234 fRegisterValue[kTPQE1] .Init("TPQE1", 0x3008, 7, 0x14 );
235 fRegisterValue[kEBD] .Init("EBD", 0x3009, 3, 0x0 );
236 fRegisterValue[kEBAQA] .Init("EBAQA", 0x300A, 7, 0x00 );
237 fRegisterValue[kEBSIA] .Init("EBSIA", 0x300B, 7, 0x20 );
238 fRegisterValue[kEBSF] .Init("EBSF", 0x300C, 1, 0x1 );
239 fRegisterValue[kEBSIM] .Init("EBSIM", 0x300D, 1, 0x1 );
240 fRegisterValue[kEBPP] .Init("EBPP", 0x300E, 1, 0x1 );
241 fRegisterValue[kEBPC] .Init("EBPC", 0x300F, 1, 0x1 );
242 fRegisterValue[kEBIS] .Init("EBIS", 0x3014, 10, 0x005 );
243 fRegisterValue[kEBIT] .Init("EBIT", 0x3015, 12, 0x028 );
244 fRegisterValue[kEBIL] .Init("EBIL", 0x3016, 8, 0xF0 );
245 fRegisterValue[kEBIN] .Init("EBIN", 0x3017, 1, 0x1 );
246 fRegisterValue[kFLBY] .Init("FLBY", 0x3018, 1, 0x0 );
247 fRegisterValue[kFPBY] .Init("FPBY", 0x3019, 1, 0x0 );
248 fRegisterValue[kFGBY] .Init("FGBY", 0x301A, 1, 0x0 );
249 fRegisterValue[kFTBY] .Init("FTBY", 0x301B, 1, 0x0 );
250 fRegisterValue[kFCBY] .Init("FCBY", 0x301C, 1, 0x0 );
251 fRegisterValue[kFPTC] .Init("FPTC", 0x3020, 2, 0x3 );
252 fRegisterValue[kFPNP] .Init("FPNP", 0x3021, 9, 0x078 );
253 fRegisterValue[kFPCL] .Init("FPCL", 0x3022, 1, 0x1 );
254 fRegisterValue[kFGTA] .Init("FGTA", 0x3028, 12, 0x014 );
255 fRegisterValue[kFGTB] .Init("FGTB", 0x3029, 12, 0x80C );
256 fRegisterValue[kFGCL] .Init("FGCL", 0x302A, 1, 0x1 );
257 fRegisterValue[kFTAL] .Init("FTAL", 0x3030, 10, 0x0F6 );
258 fRegisterValue[kFTLL] .Init("FTLL", 0x3031, 9, 0x11D );
259 fRegisterValue[kFTLS] .Init("FTLS", 0x3032, 9, 0x0D3 );
260 fRegisterValue[kFCW1] .Init("FCW1", 0x3038, 8, 0x1E );
261 fRegisterValue[kFCW2] .Init("FCW2", 0x3039, 8, 0xD4 );
262 fRegisterValue[kFCW3] .Init("FCW3", 0x303A, 8, 0xE6 );
263 fRegisterValue[kFCW4] .Init("FCW4", 0x303B, 8, 0x4A );
264 fRegisterValue[kFCW5] .Init("FCW5", 0x303C, 8, 0xEF );
265 fRegisterValue[kTPFP] .Init("TPFP", 0x3040, 9, 0x037 );
266 fRegisterValue[kTPHT] .Init("TPHT", 0x3041, 14, 0x00A0 );
267 fRegisterValue[kTPVT] .Init("TPVT", 0x3042, 6, 0x00 );
268 fRegisterValue[kTPVBY] .Init("TPVBY", 0x3043, 1, 0x0 );
269 fRegisterValue[kTPCT] .Init("TPCT", 0x3044, 5, 0x08 );
270 fRegisterValue[kTPCL] .Init("TPCL", 0x3045, 5, 0x01 );
271 fRegisterValue[kTPCBY] .Init("TPCBY", 0x3046, 1, 0x1 );
272 fRegisterValue[kTPD] .Init("TPD", 0x3047, 4, 0xF );
273 fRegisterValue[kTPCI0] .Init("TPCI0", 0x3048, 5, 0x00 );
274 fRegisterValue[kTPCI1] .Init("TPCI1", 0x3049, 5, 0x00 );
275 fRegisterValue[kTPCI2] .Init("TPCI2", 0x304A, 5, 0x00 );
276 fRegisterValue[kTPCI3] .Init("TPCI3", 0x304B, 5, 0x00 );
277 fRegisterValue[kADCMSK] .Init("ADCMSK", 0x3050, 21, 0x1FFFFF );
278 fRegisterValue[kADCINB] .Init("ADCINB", 0x3051, 2, 0x2 );
279 fRegisterValue[kADCDAC] .Init("ADCDAC", 0x3052, 5, 0x10 );
280 fRegisterValue[kADCPAR] .Init("ADCPAR", 0x3053, 18, 0x195EF );
281 fRegisterValue[kADCTST] .Init("ADCTST", 0x3054, 2, 0x0 );
282 fRegisterValue[kSADCAZ] .Init("SADCAZ", 0x3055, 1, 0x1 );
283 fRegisterValue[kFGF0] .Init("FGF0", 0x3080, 9, 0x000 );
284 fRegisterValue[kFGF1] .Init("FGF1", 0x3081, 9, 0x000 );
285 fRegisterValue[kFGF2] .Init("FGF2", 0x3082, 9, 0x000 );
286 fRegisterValue[kFGF3] .Init("FGF3", 0x3083, 9, 0x000 );
287 fRegisterValue[kFGF4] .Init("FGF4", 0x3084, 9, 0x000 );
288 fRegisterValue[kFGF5] .Init("FGF5", 0x3085, 9, 0x000 );
289 fRegisterValue[kFGF6] .Init("FGF6", 0x3086, 9, 0x000 );
290 fRegisterValue[kFGF7] .Init("FGF7", 0x3087, 9, 0x000 );
291 fRegisterValue[kFGF8] .Init("FGF8", 0x3088, 9, 0x000 );
292 fRegisterValue[kFGF9] .Init("FGF9", 0x3089, 9, 0x000 );
293 fRegisterValue[kFGF10] .Init("FGF10", 0x308A, 9, 0x000 );
294 fRegisterValue[kFGF11] .Init("FGF11", 0x308B, 9, 0x000 );
295 fRegisterValue[kFGF12] .Init("FGF12", 0x308C, 9, 0x000 );
296 fRegisterValue[kFGF13] .Init("FGF13", 0x308D, 9, 0x000 );
297 fRegisterValue[kFGF14] .Init("FGF14", 0x308E, 9, 0x000 );
298 fRegisterValue[kFGF15] .Init("FGF15", 0x308F, 9, 0x000 );
299 fRegisterValue[kFGF16] .Init("FGF16", 0x3090, 9, 0x000 );
300 fRegisterValue[kFGF17] .Init("FGF17", 0x3091, 9, 0x000 );
301 fRegisterValue[kFGF18] .Init("FGF18", 0x3092, 9, 0x000 );
302 fRegisterValue[kFGF19] .Init("FGF19", 0x3093, 9, 0x000 );
303 fRegisterValue[kFGF20] .Init("FGF20", 0x3094, 9, 0x000 );
304 fRegisterValue[kFGA0] .Init("FGA0", 0x30A0, 6, 0x00 );
305 fRegisterValue[kFGA1] .Init("FGA1", 0x30A1, 6, 0x00 );
306 fRegisterValue[kFGA2] .Init("FGA2", 0x30A2, 6, 0x00 );
307 fRegisterValue[kFGA3] .Init("FGA3", 0x30A3, 6, 0x00 );
308 fRegisterValue[kFGA4] .Init("FGA4", 0x30A4, 6, 0x00 );
309 fRegisterValue[kFGA5] .Init("FGA5", 0x30A5, 6, 0x00 );
310 fRegisterValue[kFGA6] .Init("FGA6", 0x30A6, 6, 0x00 );
311 fRegisterValue[kFGA7] .Init("FGA7", 0x30A7, 6, 0x00 );
312 fRegisterValue[kFGA8] .Init("FGA8", 0x30A8, 6, 0x00 );
313 fRegisterValue[kFGA9] .Init("FGA9", 0x30A9, 6, 0x00 );
314 fRegisterValue[kFGA10] .Init("FGA10", 0x30AA, 6, 0x00 );
315 fRegisterValue[kFGA11] .Init("FGA11", 0x30AB, 6, 0x00 );
316 fRegisterValue[kFGA12] .Init("FGA12", 0x30AC, 6, 0x00 );
317 fRegisterValue[kFGA13] .Init("FGA13", 0x30AD, 6, 0x00 );
318 fRegisterValue[kFGA14] .Init("FGA14", 0x30AE, 6, 0x00 );
319 fRegisterValue[kFGA15] .Init("FGA15", 0x30AF, 6, 0x00 );
320 fRegisterValue[kFGA16] .Init("FGA16", 0x30B0, 6, 0x00 );
321 fRegisterValue[kFGA17] .Init("FGA17", 0x30B1, 6, 0x00 );
322 fRegisterValue[kFGA18] .Init("FGA18", 0x30B2, 6, 0x00 );
323 fRegisterValue[kFGA19] .Init("FGA19", 0x30B3, 6, 0x00 );
324 fRegisterValue[kFGA20] .Init("FGA20", 0x30B4, 6, 0x00 );
325 fRegisterValue[kFLL00] .Init("FLL00", 0x3100, 6, 0x00 ); // non-linearity table, 64 x 6 bits
326 fRegisterValue[kFLL01] .Init("FLL01", 0x3101, 6, 0x00 );
327 fRegisterValue[kFLL02] .Init("FLL02", 0x3102, 6, 0x00 );
328 fRegisterValue[kFLL03] .Init("FLL03", 0x3103, 6, 0x00 );
329 fRegisterValue[kFLL04] .Init("FLL04", 0x3104, 6, 0x00 );
330 fRegisterValue[kFLL05] .Init("FLL05", 0x3105, 6, 0x00 );
331 fRegisterValue[kFLL06] .Init("FLL06", 0x3106, 6, 0x00 );
332 fRegisterValue[kFLL07] .Init("FLL07", 0x3107, 6, 0x00 );
333 fRegisterValue[kFLL08] .Init("FLL08", 0x3108, 6, 0x00 );
334 fRegisterValue[kFLL09] .Init("FLL09", 0x3109, 6, 0x00 );
335 fRegisterValue[kFLL0A] .Init("FLL0A", 0x310A, 6, 0x00 );
336 fRegisterValue[kFLL0B] .Init("FLL0B", 0x310B, 6, 0x00 );
337 fRegisterValue[kFLL0C] .Init("FLL0C", 0x310C, 6, 0x00 );
338 fRegisterValue[kFLL0D] .Init("FLL0D", 0x310D, 6, 0x00 );
339 fRegisterValue[kFLL0E] .Init("FLL0E", 0x310E, 6, 0x00 );
340 fRegisterValue[kFLL0F] .Init("FLL0F", 0x310F, 6, 0x00 );
341 fRegisterValue[kFLL10] .Init("FLL10", 0x3110, 6, 0x00 );
342 fRegisterValue[kFLL11] .Init("FLL11", 0x3111, 6, 0x00 );
343 fRegisterValue[kFLL12] .Init("FLL12", 0x3112, 6, 0x00 );
344 fRegisterValue[kFLL13] .Init("FLL13", 0x3113, 6, 0x00 );
345 fRegisterValue[kFLL14] .Init("FLL14", 0x3114, 6, 0x00 );
346 fRegisterValue[kFLL15] .Init("FLL15", 0x3115, 6, 0x00 );
347 fRegisterValue[kFLL16] .Init("FLL16", 0x3116, 6, 0x00 );
348 fRegisterValue[kFLL17] .Init("FLL17", 0x3117, 6, 0x00 );
349 fRegisterValue[kFLL18] .Init("FLL18", 0x3118, 6, 0x00 );
350 fRegisterValue[kFLL19] .Init("FLL19", 0x3119, 6, 0x00 );
351 fRegisterValue[kFLL1A] .Init("FLL1A", 0x311A, 6, 0x00 );
352 fRegisterValue[kFLL1B] .Init("FLL1B", 0x311B, 6, 0x00 );
353 fRegisterValue[kFLL1C] .Init("FLL1C", 0x311C, 6, 0x00 );
354 fRegisterValue[kFLL1D] .Init("FLL1D", 0x311D, 6, 0x00 );
355 fRegisterValue[kFLL1E] .Init("FLL1E", 0x311E, 6, 0x00 );
356 fRegisterValue[kFLL1F] .Init("FLL1F", 0x311F, 6, 0x00 );
357 fRegisterValue[kFLL20] .Init("FLL20", 0x3120, 6, 0x00 );
358 fRegisterValue[kFLL21] .Init("FLL21", 0x3121, 6, 0x00 );
359 fRegisterValue[kFLL22] .Init("FLL22", 0x3122, 6, 0x00 );
360 fRegisterValue[kFLL23] .Init("FLL23", 0x3123, 6, 0x00 );
361 fRegisterValue[kFLL24] .Init("FLL24", 0x3124, 6, 0x00 );
362 fRegisterValue[kFLL25] .Init("FLL25", 0x3125, 6, 0x00 );
363 fRegisterValue[kFLL26] .Init("FLL26", 0x3126, 6, 0x00 );
364 fRegisterValue[kFLL27] .Init("FLL27", 0x3127, 6, 0x00 );
365 fRegisterValue[kFLL28] .Init("FLL28", 0x3128, 6, 0x00 );
366 fRegisterValue[kFLL29] .Init("FLL29", 0x3129, 6, 0x00 );
367 fRegisterValue[kFLL2A] .Init("FLL2A", 0x312A, 6, 0x00 );
368 fRegisterValue[kFLL2B] .Init("FLL2B", 0x312B, 6, 0x00 );
369 fRegisterValue[kFLL2C] .Init("FLL2C", 0x312C, 6, 0x00 );
370 fRegisterValue[kFLL2D] .Init("FLL2D", 0x312D, 6, 0x00 );
371 fRegisterValue[kFLL2E] .Init("FLL2E", 0x312E, 6, 0x00 );
372 fRegisterValue[kFLL2F] .Init("FLL2F", 0x312F, 6, 0x00 );
373 fRegisterValue[kFLL30] .Init("FLL30", 0x3130, 6, 0x00 );
374 fRegisterValue[kFLL31] .Init("FLL31", 0x3131, 6, 0x00 );
375 fRegisterValue[kFLL32] .Init("FLL32", 0x3132, 6, 0x00 );
376 fRegisterValue[kFLL33] .Init("FLL33", 0x3133, 6, 0x00 );
377 fRegisterValue[kFLL34] .Init("FLL34", 0x3134, 6, 0x00 );
378 fRegisterValue[kFLL35] .Init("FLL35", 0x3135, 6, 0x00 );
379 fRegisterValue[kFLL36] .Init("FLL36", 0x3136, 6, 0x00 );
380 fRegisterValue[kFLL37] .Init("FLL37", 0x3137, 6, 0x00 );
381 fRegisterValue[kFLL38] .Init("FLL38", 0x3138, 6, 0x00 );
382 fRegisterValue[kFLL39] .Init("FLL39", 0x3139, 6, 0x00 );
383 fRegisterValue[kFLL3A] .Init("FLL3A", 0x313A, 6, 0x00 );
384 fRegisterValue[kFLL3B] .Init("FLL3B", 0x313B, 6, 0x00 );
385 fRegisterValue[kFLL3C] .Init("FLL3C", 0x313C, 6, 0x00 );
386 fRegisterValue[kFLL3D] .Init("FLL3D", 0x313D, 6, 0x00 );
387 fRegisterValue[kFLL3E] .Init("FLL3E", 0x313E, 6, 0x00 );
388 fRegisterValue[kFLL3F] .Init("FLL3F", 0x313F, 6, 0x00 );
389 fRegisterValue[kPASADEL] .Init("PASADEL", 0x3158, 8, 0xFF ); // end of non-lin table
390 fRegisterValue[kPASAPHA] .Init("PASAPHA", 0x3159, 6, 0x3F );
391 fRegisterValue[kPASAPRA] .Init("PASAPRA", 0x315A, 6, 0x0F );
392 fRegisterValue[kPASADAC] .Init("PASADAC", 0x315B, 8, 0x80 );
393 fRegisterValue[kPASACHM] .Init("PASACHM", 0x315C, 19, 0x7FFFF );
394 fRegisterValue[kPASASTL] .Init("PASASTL", 0x315D, 8, 0xFF );
395 fRegisterValue[kPASAPR1] .Init("PASAPR1", 0x315E, 1, 0x0 );
396 fRegisterValue[kPASAPR0] .Init("PASAPR0", 0x315F, 1, 0x0 );
397 fRegisterValue[kSADCTRG] .Init("SADCTRG", 0x3161, 1, 0x0 );
398 fRegisterValue[kSADCRUN] .Init("SADCRUN", 0x3162, 1, 0x0 );
399 fRegisterValue[kSADCPWR] .Init("SADCPWR", 0x3163, 3, 0x7 );
400 fRegisterValue[kL0TSIM] .Init("L0TSIM", 0x3165, 14, 0x0050 );
401 fRegisterValue[kSADCEC] .Init("SADCEC", 0x3166, 7, 0x00 );
402 fRegisterValue[kSADCMC] .Init("SADCMC", 0x3170, 8, 0xC0 );
403 fRegisterValue[kSADCOC] .Init("SADCOC", 0x3171, 8, 0x19 );
404 fRegisterValue[kSADCGTB] .Init("SADCGTB", 0x3172, 32, 0x37737700 );
405 fRegisterValue[kSEBDEN] .Init("SEBDEN", 0x3178, 3, 0x0 );
406 fRegisterValue[kSEBDOU] .Init("SEBDOU", 0x3179, 3, 0x0 );
407 fRegisterValue[kTPL00] .Init("TPL00", 0x3180, 5, 0x00 ); // pos table, 128 x 5 bits
408 fRegisterValue[kTPL01] .Init("TPL01", 0x3181, 5, 0x00 );
409 fRegisterValue[kTPL02] .Init("TPL02", 0x3182, 5, 0x00 );
410 fRegisterValue[kTPL03] .Init("TPL03", 0x3183, 5, 0x00 );
411 fRegisterValue[kTPL04] .Init("TPL04", 0x3184, 5, 0x00 );
412 fRegisterValue[kTPL05] .Init("TPL05", 0x3185, 5, 0x00 );
413 fRegisterValue[kTPL06] .Init("TPL06", 0x3186, 5, 0x00 );
414 fRegisterValue[kTPL07] .Init("TPL07", 0x3187, 5, 0x00 );
415 fRegisterValue[kTPL08] .Init("TPL08", 0x3188, 5, 0x00 );
416 fRegisterValue[kTPL09] .Init("TPL09", 0x3189, 5, 0x00 );
417 fRegisterValue[kTPL0A] .Init("TPL0A", 0x318A, 5, 0x00 );
418 fRegisterValue[kTPL0B] .Init("TPL0B", 0x318B, 5, 0x00 );
419 fRegisterValue[kTPL0C] .Init("TPL0C", 0x318C, 5, 0x00 );
420 fRegisterValue[kTPL0D] .Init("TPL0D", 0x318D, 5, 0x00 );
421 fRegisterValue[kTPL0E] .Init("TPL0E", 0x318E, 5, 0x00 );
422 fRegisterValue[kTPL0F] .Init("TPL0F", 0x318F, 5, 0x00 );
423 fRegisterValue[kTPL10] .Init("TPL10", 0x3190, 5, 0x00 );
424 fRegisterValue[kTPL11] .Init("TPL11", 0x3191, 5, 0x00 );
425 fRegisterValue[kTPL12] .Init("TPL12", 0x3192, 5, 0x00 );
426 fRegisterValue[kTPL13] .Init("TPL13", 0x3193, 5, 0x00 );
427 fRegisterValue[kTPL14] .Init("TPL14", 0x3194, 5, 0x00 );
428 fRegisterValue[kTPL15] .Init("TPL15", 0x3195, 5, 0x00 );
429 fRegisterValue[kTPL16] .Init("TPL16", 0x3196, 5, 0x00 );
430 fRegisterValue[kTPL17] .Init("TPL17", 0x3197, 5, 0x00 );
431 fRegisterValue[kTPL18] .Init("TPL18", 0x3198, 5, 0x00 );
432 fRegisterValue[kTPL19] .Init("TPL19", 0x3199, 5, 0x00 );
433 fRegisterValue[kTPL1A] .Init("TPL1A", 0x319A, 5, 0x00 );
434 fRegisterValue[kTPL1B] .Init("TPL1B", 0x319B, 5, 0x00 );
435 fRegisterValue[kTPL1C] .Init("TPL1C", 0x319C, 5, 0x00 );
436 fRegisterValue[kTPL1D] .Init("TPL1D", 0x319D, 5, 0x00 );
437 fRegisterValue[kTPL1E] .Init("TPL1E", 0x319E, 5, 0x00 );
438 fRegisterValue[kTPL1F] .Init("TPL1F", 0x319F, 5, 0x00 );
439 fRegisterValue[kTPL20] .Init("TPL20", 0x31A0, 5, 0x00 );
440 fRegisterValue[kTPL21] .Init("TPL21", 0x31A1, 5, 0x00 );
441 fRegisterValue[kTPL22] .Init("TPL22", 0x31A2, 5, 0x00 );
442 fRegisterValue[kTPL23] .Init("TPL23", 0x31A3, 5, 0x00 );
443 fRegisterValue[kTPL24] .Init("TPL24", 0x31A4, 5, 0x00 );
444 fRegisterValue[kTPL25] .Init("TPL25", 0x31A5, 5, 0x00 );
445 fRegisterValue[kTPL26] .Init("TPL26", 0x31A6, 5, 0x00 );
446 fRegisterValue[kTPL27] .Init("TPL27", 0x31A7, 5, 0x00 );
447 fRegisterValue[kTPL28] .Init("TPL28", 0x31A8, 5, 0x00 );
448 fRegisterValue[kTPL29] .Init("TPL29", 0x31A9, 5, 0x00 );
449 fRegisterValue[kTPL2A] .Init("TPL2A", 0x31AA, 5, 0x00 );
450 fRegisterValue[kTPL2B] .Init("TPL2B", 0x31AB, 5, 0x00 );
451 fRegisterValue[kTPL2C] .Init("TPL2C", 0x31AC, 5, 0x00 );
452 fRegisterValue[kTPL2D] .Init("TPL2D", 0x31AD, 5, 0x00 );
453 fRegisterValue[kTPL2E] .Init("TPL2E", 0x31AE, 5, 0x00 );
454 fRegisterValue[kTPL2F] .Init("TPL2F", 0x31AF, 5, 0x00 );
455 fRegisterValue[kTPL30] .Init("TPL30", 0x31B0, 5, 0x00 );
456 fRegisterValue[kTPL31] .Init("TPL31", 0x31B1, 5, 0x00 );
457 fRegisterValue[kTPL32] .Init("TPL32", 0x31B2, 5, 0x00 );
458 fRegisterValue[kTPL33] .Init("TPL33", 0x31B3, 5, 0x00 );
459 fRegisterValue[kTPL34] .Init("TPL34", 0x31B4, 5, 0x00 );
460 fRegisterValue[kTPL35] .Init("TPL35", 0x31B5, 5, 0x00 );
461 fRegisterValue[kTPL36] .Init("TPL36", 0x31B6, 5, 0x00 );
462 fRegisterValue[kTPL37] .Init("TPL37", 0x31B7, 5, 0x00 );
463 fRegisterValue[kTPL38] .Init("TPL38", 0x31B8, 5, 0x00 );
464 fRegisterValue[kTPL39] .Init("TPL39", 0x31B9, 5, 0x00 );
465 fRegisterValue[kTPL3A] .Init("TPL3A", 0x31BA, 5, 0x00 );
466 fRegisterValue[kTPL3B] .Init("TPL3B", 0x31BB, 5, 0x00 );
467 fRegisterValue[kTPL3C] .Init("TPL3C", 0x31BC, 5, 0x00 );
468 fRegisterValue[kTPL3D] .Init("TPL3D", 0x31BD, 5, 0x00 );
469 fRegisterValue[kTPL3E] .Init("TPL3E", 0x31BE, 5, 0x00 );
470 fRegisterValue[kTPL3F] .Init("TPL3F", 0x31BF, 5, 0x00 );
471 fRegisterValue[kTPL40] .Init("TPL40", 0x31C0, 5, 0x00 );
472 fRegisterValue[kTPL41] .Init("TPL41", 0x31C1, 5, 0x00 );
473 fRegisterValue[kTPL42] .Init("TPL42", 0x31C2, 5, 0x00 );
474 fRegisterValue[kTPL43] .Init("TPL43", 0x31C3, 5, 0x00 );
475 fRegisterValue[kTPL44] .Init("TPL44", 0x31C4, 5, 0x00 );
476 fRegisterValue[kTPL45] .Init("TPL45", 0x31C5, 5, 0x00 );
477 fRegisterValue[kTPL46] .Init("TPL46", 0x31C6, 5, 0x00 );
478 fRegisterValue[kTPL47] .Init("TPL47", 0x31C7, 5, 0x00 );
479 fRegisterValue[kTPL48] .Init("TPL48", 0x31C8, 5, 0x00 );
480 fRegisterValue[kTPL49] .Init("TPL49", 0x31C9, 5, 0x00 );
481 fRegisterValue[kTPL4A] .Init("TPL4A", 0x31CA, 5, 0x00 );
482 fRegisterValue[kTPL4B] .Init("TPL4B", 0x31CB, 5, 0x00 );
483 fRegisterValue[kTPL4C] .Init("TPL4C", 0x31CC, 5, 0x00 );
484 fRegisterValue[kTPL4D] .Init("TPL4D", 0x31CD, 5, 0x00 );
485 fRegisterValue[kTPL4E] .Init("TPL4E", 0x31CE, 5, 0x00 );
486 fRegisterValue[kTPL4F] .Init("TPL4F", 0x31CF, 5, 0x00 );
487 fRegisterValue[kTPL50] .Init("TPL50", 0x31D0, 5, 0x00 );
488 fRegisterValue[kTPL51] .Init("TPL51", 0x31D1, 5, 0x00 );
489 fRegisterValue[kTPL52] .Init("TPL52", 0x31D2, 5, 0x00 );
490 fRegisterValue[kTPL53] .Init("TPL53", 0x31D3, 5, 0x00 );
491 fRegisterValue[kTPL54] .Init("TPL54", 0x31D4, 5, 0x00 );
492 fRegisterValue[kTPL55] .Init("TPL55", 0x31D5, 5, 0x00 );
493 fRegisterValue[kTPL56] .Init("TPL56", 0x31D6, 5, 0x00 );
494 fRegisterValue[kTPL57] .Init("TPL57", 0x31D7, 5, 0x00 );
495 fRegisterValue[kTPL58] .Init("TPL58", 0x31D8, 5, 0x00 );
496 fRegisterValue[kTPL59] .Init("TPL59", 0x31D9, 5, 0x00 );
497 fRegisterValue[kTPL5A] .Init("TPL5A", 0x31DA, 5, 0x00 );
498 fRegisterValue[kTPL5B] .Init("TPL5B", 0x31DB, 5, 0x00 );
499 fRegisterValue[kTPL5C] .Init("TPL5C", 0x31DC, 5, 0x00 );
500 fRegisterValue[kTPL5D] .Init("TPL5D", 0x31DD, 5, 0x00 );
501 fRegisterValue[kTPL5E] .Init("TPL5E", 0x31DE, 5, 0x00 );
502 fRegisterValue[kTPL5F] .Init("TPL5F", 0x31DF, 5, 0x00 );
503 fRegisterValue[kTPL60] .Init("TPL60", 0x31E0, 5, 0x00 );
504 fRegisterValue[kTPL61] .Init("TPL61", 0x31E1, 5, 0x00 );
505 fRegisterValue[kTPL62] .Init("TPL62", 0x31E2, 5, 0x00 );
506 fRegisterValue[kTPL63] .Init("TPL63", 0x31E3, 5, 0x00 );
507 fRegisterValue[kTPL64] .Init("TPL64", 0x31E4, 5, 0x00 );
508 fRegisterValue[kTPL65] .Init("TPL65", 0x31E5, 5, 0x00 );
509 fRegisterValue[kTPL66] .Init("TPL66", 0x31E6, 5, 0x00 );
510 fRegisterValue[kTPL67] .Init("TPL67", 0x31E7, 5, 0x00 );
511 fRegisterValue[kTPL68] .Init("TPL68", 0x31E8, 5, 0x00 );
512 fRegisterValue[kTPL69] .Init("TPL69", 0x31E9, 5, 0x00 );
513 fRegisterValue[kTPL6A] .Init("TPL6A", 0x31EA, 5, 0x00 );
514 fRegisterValue[kTPL6B] .Init("TPL6B", 0x31EB, 5, 0x00 );
515 fRegisterValue[kTPL6C] .Init("TPL6C", 0x31EC, 5, 0x00 );
516 fRegisterValue[kTPL6D] .Init("TPL6D", 0x31ED, 5, 0x00 );
517 fRegisterValue[kTPL6E] .Init("TPL6E", 0x31EE, 5, 0x00 );
518 fRegisterValue[kTPL6F] .Init("TPL6F", 0x31EF, 5, 0x00 );
519 fRegisterValue[kTPL70] .Init("TPL70", 0x31F0, 5, 0x00 );
520 fRegisterValue[kTPL71] .Init("TPL71", 0x31F1, 5, 0x00 );
521 fRegisterValue[kTPL72] .Init("TPL72", 0x31F2, 5, 0x00 );
522 fRegisterValue[kTPL73] .Init("TPL73", 0x31F3, 5, 0x00 );
523 fRegisterValue[kTPL74] .Init("TPL74", 0x31F4, 5, 0x00 );
524 fRegisterValue[kTPL75] .Init("TPL75", 0x31F5, 5, 0x00 );
525 fRegisterValue[kTPL76] .Init("TPL76", 0x31F6, 5, 0x00 );
526 fRegisterValue[kTPL77] .Init("TPL77", 0x31F7, 5, 0x00 );
527 fRegisterValue[kTPL78] .Init("TPL78", 0x31F8, 5, 0x00 );
528 fRegisterValue[kTPL79] .Init("TPL79", 0x31F9, 5, 0x00 );
529 fRegisterValue[kTPL7A] .Init("TPL7A", 0x31FA, 5, 0x00 );
530 fRegisterValue[kTPL7B] .Init("TPL7B", 0x31FB, 5, 0x00 );
531 fRegisterValue[kTPL7C] .Init("TPL7C", 0x31FC, 5, 0x00 );
532 fRegisterValue[kTPL7D] .Init("TPL7D", 0x31FD, 5, 0x00 );
533 fRegisterValue[kTPL7E] .Init("TPL7E", 0x31FE, 5, 0x00 );
534 fRegisterValue[kTPL7F] .Init("TPL7F", 0x31FF, 5, 0x00 );
535 fRegisterValue[kMEMRW] .Init("MEMRW", 0xD000, 7, 0x79 ); // end of pos table
536 fRegisterValue[kMEMCOR] .Init("MEMCOR", 0xD001, 9, 0x000 );
537 fRegisterValue[kDMDELA] .Init("DMDELA", 0xD002, 4, 0x8 );
538 fRegisterValue[kDMDELS] .Init("DMDELS", 0xD003, 4, 0x8 );
ce4786b9 539}
540
541
8ea391e3 542void AliTRDtrapConfig::ResetRegs()
ce4786b9 543{
2b2b540f 544 // Reset the content of all TRAP registers to the reset values (see TRAP User Manual)
ce4786b9 545
2b2b540f 546 for (Int_t iReg = 0; iReg < kLastReg; iReg++) {
547 fRegisterValue[iReg].Reset();
548 }
ce4786b9 549}
550
551
8ea391e3 552void AliTRDtrapConfig::ResetDmem()
553{
6419bebb 554 // reset the data memory
555
2b2b540f 556 for(Int_t iAddr = 0; iAddr < fgkDmemWords; iAddr++)
557 fDmem[iAddr].Reset();
8ea391e3 558}
559
560
561Int_t AliTRDtrapConfig::GetTrapReg(TrapReg_t reg, Int_t det, Int_t rob, Int_t mcm) const
ce4786b9 562{
5f006bd7 563 // get the value of an individual TRAP register
ce4786b9 564 // if it is individual for TRAPs a valid TRAP has to be specified
565
566 if ((reg < 0) || (reg >= kLastReg)) {
567 AliError("Non-existing register requested");
54d34aac 568 return 0;
ce4786b9 569 }
570 else {
2b2b540f 571 return fRegisterValue[reg].GetValue(det, rob, mcm);
ce4786b9 572 }
ce4786b9 573}
574
575
ce4786b9 576Bool_t AliTRDtrapConfig::SetTrapReg(TrapReg_t reg, Int_t value, Int_t det)
577{
2b2b540f 578 // set a value for the given TRAP register on all chambers,
ce4786b9 579
2b2b540f 580 return fRegisterValue[reg].SetValue(value, det);
ce4786b9 581}
582
583
584Bool_t AliTRDtrapConfig::SetTrapReg(TrapReg_t reg, Int_t value, Int_t det, Int_t rob, Int_t mcm)
585{
5f006bd7 586 // set the value for the given TRAP register of an individual MCM
ce4786b9 587
2b2b540f 588 return fRegisterValue[reg].SetValue(value, det, rob, mcm);
ce4786b9 589}
590
591
8ea391e3 592UInt_t AliTRDtrapConfig::Peek(Int_t addr, Int_t det, Int_t rob, Int_t mcm) const
ce4786b9 593{
594 // reading from given address
ce4786b9 595
5f006bd7 596 if ( (addr >= fgkDmemStartAddress) &&
ce4786b9 597 (addr < (fgkDmemStartAddress + fgkDmemWords)) ) {
8ea391e3 598 return GetDmemUnsigned(addr, det, rob, mcm);
ce4786b9 599 }
600 else {
601 TrapReg_t mcmReg = GetRegByAddress(addr);
602 if ( mcmReg >= 0 && mcmReg < kLastReg) {
8ea391e3 603 return (UInt_t) GetTrapReg(mcmReg, det, rob, mcm);
ce4786b9 604 }
605 }
606
2b2b540f 607 AliError(Form("peek for invalid addr: 0x%04x", addr));
b17aded9 608 return 0;
ce4786b9 609}
610
611
8ea391e3 612Bool_t AliTRDtrapConfig::Poke(Int_t addr, UInt_t value, Int_t det, Int_t rob, Int_t mcm)
ce4786b9 613{
614 // writing to given address
ce4786b9 615
5f006bd7 616 if ( (addr >= fgkDmemStartAddress) &&
ce4786b9 617 (addr < (fgkDmemStartAddress + fgkDmemWords)) ) {
051af255 618 AliDebug(2, Form("DMEM 0x%08x : %i", addr, value));
2b2b540f 619 return SetDmem(addr, value, det, rob, mcm);
ce4786b9 620 }
621 else {
622 TrapReg_t mcmReg = GetRegByAddress(addr);
623 if ( mcmReg >= 0 && mcmReg < kLastReg) {
051af255 624 AliDebug(2, Form("Register: %s : %i\n", GetRegName(mcmReg), value));
2b2b540f 625 return SetTrapReg(mcmReg, (UInt_t) value, det, rob, mcm);
ce4786b9 626 }
627 }
5f006bd7 628
2b2b540f 629 AliError(Form("poke for invalid address: 0x%04x", addr));
ce4786b9 630 return kFALSE;
631}
632
633
2b2b540f 634Bool_t AliTRDtrapConfig::SetDmemAlloc(Int_t addr, Alloc_t mode)
ce4786b9 635{
2b2b540f 636 addr = addr - fgkDmemStartAddress;
59f78ad5 637
2b2b540f 638 if(addr < 0 || addr >= fgkDmemWords) {
639 AliError(Form("Invalid DMEM address: 0x%04x", addr+fgkDmemStartAddress));
640 return kFALSE;
641 }
642 else {
643 fDmem[addr].Allocate(mode);
644 return kTRUE;
645 }
646}
ce4786b9 647
8ea391e3 648
2b2b540f 649Bool_t AliTRDtrapConfig::SetDmem(Int_t addr, UInt_t value, Int_t det)
650{
651 // Set the content of the given DMEM address
8ea391e3 652
2b2b540f 653 addr = addr - fgkDmemStartAddress;
8ea391e3 654
2b2b540f 655 if(addr < 0 || addr >= fgkDmemWords) {
656 AliError(Form("No DMEM address: 0x%08x", addr+fgkDmemStartAddress));
657 return kFALSE;
658 }
051af255 659
2b2b540f 660 if (!fDmem[addr].SetValue(value, det)) {
661 AliError(Form("Problem writing to DMEM address 0x%04x", addr));
662 return kFALSE;
663 }
664 else
665 return kTRUE;
ce4786b9 666}
667
668
8ea391e3 669Bool_t AliTRDtrapConfig::SetDmem(Int_t addr, UInt_t value, Int_t det, Int_t rob, Int_t mcm)
ce4786b9 670{
5f006bd7 671 // Set the content of the given DMEM address
2b2b540f 672 addr = addr - fgkDmemStartAddress;
59f78ad5 673
2b2b540f 674 if(addr < 0 || addr >= fgkDmemWords) {
8ea391e3 675 AliError(Form("No DMEM address: 0x%08x", addr+fgkDmemStartAddress));
676 return kFALSE;
677 }
678
2b2b540f 679 if (!fDmem[addr].SetValue(value, det, rob, mcm)) {
680 AliError(Form("Problem writing to DMEM address 0x%04x", addr));
681 return kFALSE;
682 }
683 else
684 return kTRUE;
ce4786b9 685}
686
687
8ea391e3 688UInt_t AliTRDtrapConfig::GetDmemUnsigned(Int_t addr, Int_t det, Int_t rob, Int_t mcm) const
ce4786b9 689{
6419bebb 690 // get the content of the data memory at the given address
2b2b540f 691 // (only if the value is the same for all MCMs)
6419bebb 692
8ea391e3 693 addr = addr - fgkDmemStartAddress;
5f006bd7 694
2b2b540f 695 if(addr < 0 || addr >= fgkDmemWords) {
696 AliError(Form("No DMEM address: 0x%08x", addr+fgkDmemStartAddress));
697 return 0;
698 }
5f006bd7 699
2b2b540f 700 return fDmem[addr].GetValue(det, rob, mcm);
ce4786b9 701}
702
703
8ea391e3 704Bool_t AliTRDtrapConfig::PrintTrapReg(TrapReg_t reg, Int_t det, Int_t rob, Int_t mcm) const
ce4786b9 705{
706 // print the value stored in the given register
707 // if it is individual a valid MCM has to be specified
708
2b2b540f 709 if((det >= 0 && det < AliTRDgeometry::Ndet()) &&
710 (rob >= 0 && rob < AliTRDfeeParam::GetNrobC1()) &&
6170d369 711 (mcm >= 0 && mcm < AliTRDfeeParam::GetNmcmRob() + 2)) {
2b2b540f 712 printf("%10s (%2i bits) at 0x%04x is 0x%08x and resets to: 0x%08x (currently individual mode)\n",
713 GetRegName((TrapReg_t) reg),
714 GetRegNBits((TrapReg_t) reg),
715 GetRegAddress((TrapReg_t) reg),
716 fRegisterValue[reg].GetValue(det, rob, mcm),
717 GetRegResetValue((TrapReg_t) reg));
ce4786b9 718 }
2b2b540f 719 else {
720 AliError("Register value is MCM-specific: Invalid detector, ROB or MCM requested");
ce4786b9 721 return kFALSE;
722 }
2b2b540f 723
ce4786b9 724 return kTRUE;
725}
726
727
8ea391e3 728Bool_t AliTRDtrapConfig::PrintTrapAddr(Int_t addr, Int_t det, Int_t rob, Int_t mcm) const
ce4786b9 729{
730 // print the value stored at the given address in the MCM chip
731 TrapReg_t reg = GetRegByAddress(addr);
732 if (reg >= 0 && reg < kLastReg) {
733 return PrintTrapReg(reg, det, rob, mcm);
734 }
735 else {
736 AliError(Form("There is no register at address 0x%08x in the simulator", addr));
737 return kFALSE;
738 }
739}
740
741
8ea391e3 742AliTRDtrapConfig::TrapReg_t AliTRDtrapConfig::GetRegByAddress(Int_t address) const
ce4786b9 743{
8ea391e3 744 // get register by its address
745 // used for reading of configuration data as sent to real FEE
ce4786b9 746
2b2b540f 747 if (address < fgkRegisterAddressBlockStart[0])
748 return kLastReg;
749 else if (address < fgkRegisterAddressBlockStart[0] + fgkRegisterAddressBlockSize[0])
750 return fgRegAddressMap[address - fgkRegisterAddressBlockStart[0]];
751 else if (address < fgkRegisterAddressBlockStart[1])
752 return kLastReg;
753 else if (address < fgkRegisterAddressBlockStart[1] + fgkRegisterAddressBlockSize[1])
754 return fgRegAddressMap[address - fgkRegisterAddressBlockStart[1] + fgkRegisterAddressBlockSize[0]];
755 else if (address < fgkRegisterAddressBlockStart[2])
756 return kLastReg;
757 else if (address < fgkRegisterAddressBlockStart[2] + fgkRegisterAddressBlockSize[2])
758 return fgRegAddressMap[address - fgkRegisterAddressBlockStart[2] + fgkRegisterAddressBlockSize[1] + fgkRegisterAddressBlockSize[0]];
759 else
760 return kLastReg;
ce4786b9 761}
762
763
8ea391e3 764void AliTRDtrapConfig::PrintMemDatx(ostream &os, Int_t addr) const
ce4786b9 765{
6419bebb 766 // print the content of the data memory as datx
767
8ea391e3 768 PrintMemDatx(os, addr, 0, 0, 127);
ce4786b9 769}
770
8ea391e3 771void AliTRDtrapConfig::PrintMemDatx(ostream &os, Int_t addr, Int_t det, Int_t rob, Int_t mcm) const
ce4786b9 772{
6419bebb 773 // print the content of the data memory as datx
774
8ea391e3 775 if(addr < fgkDmemStartAddress || addr >= fgkDmemStartAddress+fgkDmemWords) {
776 AliError(Form("Invalid DMEM address 0x%08x!", addr));
777 return;
778 }
779 PrintDatx(os, addr, GetDmemUnsigned(addr, det, rob, mcm), rob, mcm);
780}
781
ce4786b9 782
8ea391e3 783void AliTRDtrapConfig::PrintMemDatx(ostream &os, TrapReg_t reg) const
784{
6419bebb 785 // print the content of the data memory as datx
786
8ea391e3 787 PrintMemDatx(os, reg, 0, 0, 127);
ce4786b9 788}
789
790
8ea391e3 791void AliTRDtrapConfig::PrintMemDatx(ostream &os, TrapReg_t reg, Int_t det, Int_t rob, Int_t mcm) const
ce4786b9 792{
6419bebb 793 // print the content of the data memory as datx
794
8ea391e3 795 if(reg>= kLastReg) {
796 AliError(Form("Invalid register %i!", reg));
797 return;
798 }
799 PrintDatx(os, GetRegAddress(reg), GetTrapReg(reg, det, rob, mcm), rob, mcm);
800}
36dc3337 801
ce4786b9 802
8ea391e3 803void AliTRDtrapConfig::PrintDatx(ostream &os, UInt_t addr, UInt_t data, Int_t rob, Int_t mcm) const
804{
6419bebb 805 // print the value at the given address as datx
806
5f006bd7 807 os << std::setw(5) << 10
8ea391e3 808 << std::setw(8) << addr
809 << std::setw(12) << data;
810 if(mcm==127)
811 os << std::setw(8) << 127;
812 else
813 os << std::setw(8) << AliTRDfeeParam::AliToExtAli(rob, mcm);
5f006bd7 814
8ea391e3 815 os << std::endl;
ce4786b9 816}
2b2b540f 817
818
6d976847 819void AliTRDtrapConfig::PrintVerify(ostream &os, Int_t det, Int_t rob, Int_t mcm) const
820{
821 // print verification file in datx format
822
823 for (Int_t iReg = 0; iReg < kLastReg; ++iReg) {
824 os << std::setw(5) << 9
825 << std::setw(8) << GetRegAddress((TrapReg_t) iReg)
826 << std::setw(12) << GetTrapReg((TrapReg_t) iReg, det, rob, mcm)
827 << std::setw(8) << AliTRDfeeParam::AliToExtAli(rob, mcm)
828 << std::endl;
829 }
830
831 for (Int_t iWord = 0; iWord < fgkDmemWords; ++iWord) {
832 if (GetDmemUnsigned(fgkDmemStartAddress + iWord, det, rob, mcm) == 0)
833 continue;
834 os << std::setw(5) << 9
835 << std::setw(8) << fgkDmemStartAddress + iWord
836 << std::setw(12) << GetDmemUnsigned(fgkDmemStartAddress + iWord, det, rob, mcm)
837 << std::setw(8) << AliTRDfeeParam::AliToExtAli(rob, mcm)
838 << std::endl;
839 }
840}
841
2b2b540f 842AliTRDtrapConfig::AliTRDtrapValue::AliTRDtrapValue() :
843 TObject(),
844 fAllocMode(kAllocGlobal),
845 fSize(1),
846 fData(new UInt_t[1]),
847 fValid(new Bool_t[1])
848{
849 fData[0] = 0;
850 fValid[0] = kTRUE;
851}
852
0aa63880
JK
853AliTRDtrapConfig::AliTRDtrapValue::~AliTRDtrapValue()
854{
855 delete [] fData;
856 delete [] fValid;
857}
2b2b540f 858
859Bool_t AliTRDtrapConfig::AliTRDtrapValue::Allocate(Alloc_t alloc)
860{
861 // allocate memory for the specified granularity
862
863 delete [] fData;
864 delete [] fValid;
865
866 fAllocMode = alloc;
867 fSize = fgkSize[fAllocMode];
868
869 if (fSize > 0) {
870 fData = new UInt_t[fSize];
871 fValid = new Bool_t[fSize];
872 for (Int_t i = 0; i < fSize; ++i) {
873 fData[i] = 0;
874 fValid[i] = kFALSE;
875 }
876 }
877 else {
878 fData = 0x0;
879 fValid = 0x0;
880 }
881
882 return kTRUE;
883}
884
885
886Int_t AliTRDtrapConfig::AliTRDtrapValue::GetIdx(Int_t det, Int_t rob, Int_t mcm) const
887{
888 // return Idx to access the data for the given position
889
890 Int_t idx = -1;
891
892 switch (fAllocMode) {
893 case kAllocNone:
894 idx = -1;
895 break;
896 case kAllocGlobal:
897 idx = 0;
898 break;
899 case kAllocByDetector:
900 idx = det;
901 break;
902 case kAllocByHC:
903 idx = det + (rob % 2);
904 break;
905 case kAllocByMCM:
906 idx = 18*8*det + 18*rob + mcm;
907 break;
908 case kAllocByLayer:
909 idx = det % 6;
910 break;
911 case kAllocByMCMinSM:
912 idx = 18*8*(det%30) + 18*rob + mcm;
913 break;
914 default:
915 idx = -1;
916 AliError("Invalid allocation mode");
917 }
918 if (idx < fSize) {
919 return idx;
920 }
921 else {
922 AliError(Form("Index too large %i (size %i) for %s", idx, fSize, this->GetName()));
923 return -1;
924 }
925}
926
927
3df58e28 928Bool_t AliTRDtrapConfig::AliTRDtrapValue::SetData(UInt_t value)
2b2b540f 929{
930 // set the given value everywhere
931
932 for (Int_t i = 0; i < fSize; ++i) {
933 fData[i] = value;
934 fValid[i] = kFALSE;
935 }
936
937 return kTRUE;
938}
939
940
3df58e28 941Bool_t AliTRDtrapConfig::AliTRDtrapValue::SetData(UInt_t value, Int_t det)
2b2b540f 942{
943 // set the data for a given detector
944
945 Int_t idx = GetIdx(det, 0, 0);
946
947 if (idx >= 0) {
948 // short cut for detector-wise allocation
949 if (fAllocMode == kAllocByDetector) {
950 if (fValid[idx] && (fData[idx] != value)) {
951 AliDebug(1, Form("Overwriting previous value %i of %s with %i for %i!",
952 fData[idx], this->GetName(), value, det));
953 }
954 fData[idx] = value;
955 fValid[idx] = kTRUE;
956 return kTRUE;
957 }
958 else {
959 for (Int_t rob = 0; rob < 8; ++rob) {
960 for (Int_t mcm = 0; mcm < 18; ++mcm) {
961 idx = GetIdx(det, rob, mcm);
962 if (fValid[idx] && (fData[idx] != value)) {
963 AliDebug(1, Form("Overwriting previous value %i of %s with %i for %i %i:%02i!",
964 fData[idx], this->GetName(), value, det, rob, mcm));
965 }
966 fData[idx] = value;
967 fValid[idx] = kTRUE;
968 }
969 }
970 return kTRUE;
971 }
972 }
973
974 if (fAllocMode == kAllocNone) {
975 // assume nobody cares
976 return kTRUE;
977 }
978 return kFALSE;
979}
980
3df58e28 981Bool_t AliTRDtrapConfig::AliTRDtrapValue::SetData(UInt_t value, Int_t det, Int_t rob, Int_t mcm)
2b2b540f 982{
983 // set data for an individual MCM
984
985 Int_t idx = GetIdx(det, rob, mcm);
986
987 if (idx >= 0) {
988 if (fValid[idx] && (fData[idx] != value)) {
989 AliDebug(1, Form("Overwriting previous value %i of %s with %i for %i %i:%02i (idx: %i)!",
990 fData[idx], this->GetName(), value, det, rob, mcm, idx));
991 }
992 fData[idx] = value;
993 fValid[idx] = kTRUE;
994 return kTRUE;
995 }
996 else if (fAllocMode == kAllocNone) {
997 return kTRUE;
998 }
999 else {
1000 AliError(Form("setting failed"));
1001 return kFALSE;
1002 }
1003}
1004
3df58e28 1005UInt_t AliTRDtrapConfig::AliTRDtrapValue::GetData(Int_t det, Int_t rob, Int_t mcm) const
2b2b540f 1006{
1007 // read data for the given MCM
1008
1009 Int_t idx = GetIdx(det, rob, mcm);
1010 if (idx >= 0) {
1011 if (!fValid[idx])
1012 AliDebug(1,Form("reading from unwritten address: %s at idx %i: %i", this->GetName(), idx, fValid[idx]));
1013 return fData[idx];
1014 }
1015 else {
1016 AliError("read from invalid address");
1017 return 0;
1018 }
1019}
1020
1021AliTRDtrapConfig::AliTRDtrapRegister::AliTRDtrapRegister() :
1022 AliTRDtrapValue(),
1023 fName("invalid"),
1024 fAddr(0),
1025 fNbits(0),
1026 fResetValue(0)
1027{
1028 // default constructor
1029
1030}
1031
1032AliTRDtrapConfig::AliTRDtrapRegister::~AliTRDtrapRegister()
1033{
1034 // destructor
1035
1036}
1037
1038void AliTRDtrapConfig::AliTRDtrapRegister::Init(const char* name, Int_t addr, Int_t nBits, Int_t resetValue)
1039{
1040 // init the TRAP register
1041
1042 if (fAddr == 0) {
1043 fName = name;
1044 fAddr = addr;
1045 fNbits = nBits;
1046 fResetValue = resetValue;
1047 }
1048 else
1049 AliFatal("Re-initialising an existing TRAP register");
1050}
1051