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36dc3337 | 1 | /************************************************************************** |
2 | * Copyright(c) 1998-1999, ALICE Experiment at CERN, All rights reserved. * | |
3 | * * | |
4 | * Author: The ALICE Off-line Project. * | |
5 | * Contributors are mentioned in the code where appropriate. * | |
6 | * * | |
7 | * Permission to use, copy, modify and distribute this software and its * | |
8 | * documentation strictly for non-commercial purposes is hereby granted * | |
9 | * without fee, provided that the above copyright notice appears in all * | |
10 | * copies and that both the copyright notice and this permission notice * | |
11 | * appear in the supporting documentation. The authors make no claims * | |
12 | * about the suitability of this software for any purpose. It is * | |
13 | * provided "as is" without express or implied warranty. * | |
14 | **************************************************************************/ | |
15 | ||
16 | //////////////////////////////////////////////////////////////////////////// | |
17 | // // | |
18 | // TRAP config // | |
19 | // // | |
20 | // Author: J. Klein (Jochen.Klein@cern.ch) // | |
21 | // // | |
22 | //////////////////////////////////////////////////////////////////////////// | |
23 | ||
7627bf12 | 24 | #include "AliLog.h"\r |
25 | \r | |
7d298182 | 26 | #include "AliTRDgeometry.h"\r |
27 | #include "AliTRDfeeParam.h"\r | |
7627bf12 | 28 | #include "AliTRDtrapConfig.h"\r |
29 | \r | |
7d298182 | 30 | #include <fstream>\r |
31 | #include <iostream>\r | |
32 | #include <iomanip>\r | |
33 | \r | |
7627bf12 | 34 | ClassImp(AliTRDtrapConfig)\r |
35 | \r | |
36 | AliTRDtrapConfig* AliTRDtrapConfig::fgInstance = 0x0;\r | |
7d298182 | 37 | const Int_t AliTRDtrapConfig::fgkMaxMcm = AliTRDfeeParam::GetNmcmRob() + 2;\r |
7627bf12 | 38 | \r |
39 | AliTRDtrapConfig::AliTRDtrapConfig() : \r | |
40 | TObject()\r | |
41 | {\r | |
42 | // default constructor, initializing array of TRAP registers\r | |
43 | \r | |
44 | // Name Address Nbits Reset Value\r | |
45 | fRegs[kSML0] = SimpleReg_t("SML0", 0x0A00, 15, 0x4050 ); // Global state machine\r | |
46 | fRegs[kSML1] = SimpleReg_t("SML1", 0x0A01, 15, 0x4200 );\r | |
47 | fRegs[kSML2] = SimpleReg_t("SML2", 0x0A02, 15, 0x4384 );\r | |
48 | fRegs[kSMMODE] = SimpleReg_t("SMMODE", 0x0A03, 16, 0xF0E2 );\r | |
49 | fRegs[kNITM0] = SimpleReg_t("NITM0", 0x0A08, 14, 0x3FFF );\r | |
50 | fRegs[kNITM1] = SimpleReg_t("NITM1", 0x0A09, 14, 0x3FFF );\r | |
51 | fRegs[kNITM2] = SimpleReg_t("NITM2", 0x0A0A, 14, 0x3FFF );\r | |
52 | fRegs[kNIP4D] = SimpleReg_t("NIP4D", 0x0A0B, 7, 0x7F );\r | |
53 | fRegs[kCPU0CLK] = SimpleReg_t("CPU0CLK", 0x0A20, 5, 0x07 );\r | |
54 | fRegs[kCPU1CLK] = SimpleReg_t("CPU1CLK", 0x0A22, 5, 0x07 );\r | |
55 | fRegs[kCPU2CLK] = SimpleReg_t("CPU2CLK", 0x0A24, 5, 0x07 );\r | |
56 | fRegs[kCPU3CLK] = SimpleReg_t("CPU3CLK", 0x0A26, 5, 0x07 );\r | |
57 | fRegs[kNICLK] = SimpleReg_t("NICLK", 0x0A28, 5, 0x07 );\r | |
58 | fRegs[kFILCLK] = SimpleReg_t("FILCLK", 0x0A2A, 5, 0x07 );\r | |
59 | fRegs[kPRECLK] = SimpleReg_t("PRECLK", 0x0A2C, 5, 0x07 );\r | |
60 | fRegs[kADCEN] = SimpleReg_t("ADCEN", 0x0A2E, 5, 0x07 );\r | |
61 | fRegs[kNIODE] = SimpleReg_t("NIODE", 0x0A30, 5, 0x07 );\r | |
62 | fRegs[kNIOCE] = SimpleReg_t("NIOCE", 0x0A32, 6, 0x21 ); // bit 5 is status bit (read-only)!\r | |
63 | fRegs[kNIIDE] = SimpleReg_t("NIIDE", 0x0A34, 5, 0x07 );\r | |
64 | fRegs[kNIICE] = SimpleReg_t("NIICE", 0x0A36, 5, 0x07 );\r | |
65 | fRegs[kARBTIM] = SimpleReg_t("ARBTIM", 0x0A3F, 4, 0x0 ); // Arbiter\r | |
66 | fRegs[kIA0IRQ0] = SimpleReg_t("IA0IRQ0", 0x0B00, 12, 0x000 ); // IVT of CPU0\r | |
67 | fRegs[kIA0IRQ1] = SimpleReg_t("IA0IRQ1", 0x0B01, 12, 0x000 );\r | |
68 | fRegs[kIA0IRQ2] = SimpleReg_t("IA0IRQ2", 0x0B02, 12, 0x000 );\r | |
69 | fRegs[kIA0IRQ3] = SimpleReg_t("IA0IRQ3", 0x0B03, 12, 0x000 );\r | |
70 | fRegs[kIA0IRQ4] = SimpleReg_t("IA0IRQ4", 0x0B04, 12, 0x000 );\r | |
71 | fRegs[kIA0IRQ5] = SimpleReg_t("IA0IRQ5", 0x0B05, 12, 0x000 );\r | |
72 | fRegs[kIA0IRQ6] = SimpleReg_t("IA0IRQ6", 0x0B06, 12, 0x000 );\r | |
73 | fRegs[kIA0IRQ7] = SimpleReg_t("IA0IRQ7", 0x0B07, 12, 0x000 );\r | |
74 | fRegs[kIA0IRQ8] = SimpleReg_t("IA0IRQ8", 0x0B08, 12, 0x000 );\r | |
75 | fRegs[kIA0IRQ9] = SimpleReg_t("IA0IRQ9", 0x0B09, 12, 0x000 );\r | |
76 | fRegs[kIA0IRQA] = SimpleReg_t("IA0IRQA", 0x0B0A, 12, 0x000 );\r | |
77 | fRegs[kIA0IRQB] = SimpleReg_t("IA0IRQB", 0x0B0B, 12, 0x000 );\r | |
78 | fRegs[kIA0IRQC] = SimpleReg_t("IA0IRQC", 0x0B0C, 12, 0x000 );\r | |
79 | fRegs[kIRQSW0] = SimpleReg_t("IRQSW0", 0x0B0D, 13, 0x1FFF );\r | |
80 | fRegs[kIRQHW0] = SimpleReg_t("IRQHW0", 0x0B0E, 13, 0x0000 );\r | |
81 | fRegs[kIRQHL0] = SimpleReg_t("IRQHL0", 0x0B0F, 13, 0x0000 );\r | |
82 | fRegs[kIA1IRQ0] = SimpleReg_t("IA1IRQ0", 0x0B20, 12, 0x000 ); // IVT of CPU1\r | |
83 | fRegs[kIA1IRQ1] = SimpleReg_t("IA1IRQ1", 0x0B21, 12, 0x000 );\r | |
84 | fRegs[kIA1IRQ2] = SimpleReg_t("IA1IRQ2", 0x0B22, 12, 0x000 );\r | |
85 | fRegs[kIA1IRQ3] = SimpleReg_t("IA1IRQ3", 0x0B23, 12, 0x000 );\r | |
86 | fRegs[kIA1IRQ4] = SimpleReg_t("IA1IRQ4", 0x0B24, 12, 0x000 );\r | |
87 | fRegs[kIA1IRQ5] = SimpleReg_t("IA1IRQ5", 0x0B25, 12, 0x000 );\r | |
88 | fRegs[kIA1IRQ6] = SimpleReg_t("IA1IRQ6", 0x0B26, 12, 0x000 );\r | |
89 | fRegs[kIA1IRQ7] = SimpleReg_t("IA1IRQ7", 0x0B27, 12, 0x000 );\r | |
90 | fRegs[kIA1IRQ8] = SimpleReg_t("IA1IRQ8", 0x0B28, 12, 0x000 );\r | |
91 | fRegs[kIA1IRQ9] = SimpleReg_t("IA1IRQ9", 0x0B29, 12, 0x000 );\r | |
92 | fRegs[kIA1IRQA] = SimpleReg_t("IA1IRQA", 0x0B2A, 12, 0x000 );\r | |
93 | fRegs[kIA1IRQB] = SimpleReg_t("IA1IRQB", 0x0B2B, 12, 0x000 );\r | |
94 | fRegs[kIA1IRQC] = SimpleReg_t("IA1IRQC", 0x0B2C, 12, 0x000 );\r | |
95 | fRegs[kIRQSW1] = SimpleReg_t("IRQSW1", 0x0B2D, 13, 0x1FFF );\r | |
96 | fRegs[kIRQHW1] = SimpleReg_t("IRQHW1", 0x0B2E, 13, 0x0000 );\r | |
97 | fRegs[kIRQHL1] = SimpleReg_t("IRQHL1", 0x0B2F, 13, 0x0000 );\r | |
98 | fRegs[kIA2IRQ0] = SimpleReg_t("IA2IRQ0", 0x0B40, 12, 0x000 ); // IVT of CPU2\r | |
99 | fRegs[kIA2IRQ1] = SimpleReg_t("IA2IRQ1", 0x0B41, 12, 0x000 );\r | |
100 | fRegs[kIA2IRQ2] = SimpleReg_t("IA2IRQ2", 0x0B42, 12, 0x000 );\r | |
101 | fRegs[kIA2IRQ3] = SimpleReg_t("IA2IRQ3", 0x0B43, 12, 0x000 );\r | |
102 | fRegs[kIA2IRQ4] = SimpleReg_t("IA2IRQ4", 0x0B44, 12, 0x000 );\r | |
103 | fRegs[kIA2IRQ5] = SimpleReg_t("IA2IRQ5", 0x0B45, 12, 0x000 );\r | |
104 | fRegs[kIA2IRQ6] = SimpleReg_t("IA2IRQ6", 0x0B46, 12, 0x000 );\r | |
105 | fRegs[kIA2IRQ7] = SimpleReg_t("IA2IRQ7", 0x0B47, 12, 0x000 );\r | |
106 | fRegs[kIA2IRQ8] = SimpleReg_t("IA2IRQ8", 0x0B48, 12, 0x000 );\r | |
107 | fRegs[kIA2IRQ9] = SimpleReg_t("IA2IRQ9", 0x0B49, 12, 0x000 );\r | |
108 | fRegs[kIA2IRQA] = SimpleReg_t("IA2IRQA", 0x0B4A, 12, 0x000 );\r | |
109 | fRegs[kIA2IRQB] = SimpleReg_t("IA2IRQB", 0x0B4B, 12, 0x000 );\r | |
110 | fRegs[kIA2IRQC] = SimpleReg_t("IA2IRQC", 0x0B4C, 12, 0x000 );\r | |
111 | fRegs[kIRQSW2] = SimpleReg_t("IRQSW2", 0x0B4D, 13, 0x1FFF );\r | |
112 | fRegs[kIRQHW2] = SimpleReg_t("IRQHW2", 0x0B4E, 13, 0x0000 );\r | |
113 | fRegs[kIRQHL2] = SimpleReg_t("IRQHL2", 0x0B4F, 13, 0x0000 );\r | |
114 | fRegs[kIA3IRQ0] = SimpleReg_t("IA3IRQ0", 0x0B60, 12, 0x000 ); // IVT of CPU3\r | |
115 | fRegs[kIA3IRQ1] = SimpleReg_t("IA3IRQ1", 0x0B61, 12, 0x000 );\r | |
116 | fRegs[kIA3IRQ2] = SimpleReg_t("IA3IRQ2", 0x0B62, 12, 0x000 );\r | |
117 | fRegs[kIA3IRQ3] = SimpleReg_t("IA3IRQ3", 0x0B63, 12, 0x000 );\r | |
118 | fRegs[kIA3IRQ4] = SimpleReg_t("IA3IRQ4", 0x0B64, 12, 0x000 );\r | |
119 | fRegs[kIA3IRQ5] = SimpleReg_t("IA3IRQ5", 0x0B65, 12, 0x000 );\r | |
120 | fRegs[kIA3IRQ6] = SimpleReg_t("IA3IRQ6", 0x0B66, 12, 0x000 );\r | |
121 | fRegs[kIA3IRQ7] = SimpleReg_t("IA3IRQ7", 0x0B67, 12, 0x000 );\r | |
122 | fRegs[kIA3IRQ8] = SimpleReg_t("IA3IRQ8", 0x0B68, 12, 0x000 );\r | |
123 | fRegs[kIA3IRQ9] = SimpleReg_t("IA3IRQ9", 0x0B69, 12, 0x000 );\r | |
124 | fRegs[kIA3IRQA] = SimpleReg_t("IA3IRQA", 0x0B6A, 12, 0x000 );\r | |
125 | fRegs[kIA3IRQB] = SimpleReg_t("IA3IRQB", 0x0B6B, 12, 0x000 );\r | |
126 | fRegs[kIA3IRQC] = SimpleReg_t("IA3IRQC", 0x0B6C, 12, 0x000 );\r | |
127 | fRegs[kIRQSW3] = SimpleReg_t("IRQSW3", 0x0B6D, 13, 0x1FFF );\r | |
128 | fRegs[kIRQHW3] = SimpleReg_t("IRQHW3", 0x0B6E, 13, 0x0000 );\r | |
129 | fRegs[kIRQHL3] = SimpleReg_t("IRQHL3", 0x0B6F, 13, 0x0000 );\r | |
130 | fRegs[kCTGDINI] = SimpleReg_t("CTGDINI", 0x0B80, 32, 0x00000000 ); // Global Counter/Timer\r | |
131 | fRegs[kCTGCTRL] = SimpleReg_t("CTGCTRL", 0x0B81, 12, 0xE3F );\r | |
132 | fRegs[kC08CPU0] = SimpleReg_t("C08CPU0", 0x0C00, 32, 0x00000000 ); // CPU constants\r | |
133 | fRegs[kC09CPU0] = SimpleReg_t("C09CPU0", 0x0C01, 32, 0x00000000 );\r | |
134 | fRegs[kC10CPU0] = SimpleReg_t("C10CPU0", 0x0C02, 32, 0x00000000 );\r | |
135 | fRegs[kC11CPU0] = SimpleReg_t("C11CPU0", 0x0C03, 32, 0x00000000 );\r | |
136 | fRegs[kC12CPUA] = SimpleReg_t("C12CPUA", 0x0C04, 32, 0x00000000 );\r | |
137 | fRegs[kC13CPUA] = SimpleReg_t("C13CPUA", 0x0C05, 32, 0x00000000 );\r | |
138 | fRegs[kC14CPUA] = SimpleReg_t("C14CPUA", 0x0C06, 32, 0x00000000 );\r | |
139 | fRegs[kC15CPUA] = SimpleReg_t("C15CPUA", 0x0C07, 32, 0x00000000 );\r | |
140 | fRegs[kC08CPU1] = SimpleReg_t("C08CPU1", 0x0C08, 32, 0x00000000 );\r | |
141 | fRegs[kC09CPU1] = SimpleReg_t("C09CPU1", 0x0C09, 32, 0x00000000 );\r | |
142 | fRegs[kC10CPU1] = SimpleReg_t("C10CPU1", 0x0C0A, 32, 0x00000000 );\r | |
143 | fRegs[kC11CPU1] = SimpleReg_t("C11CPU1", 0x0C0B, 32, 0x00000000 );\r | |
144 | fRegs[kC08CPU2] = SimpleReg_t("C08CPU2", 0x0C10, 32, 0x00000000 );\r | |
145 | fRegs[kC09CPU2] = SimpleReg_t("C09CPU2", 0x0C11, 32, 0x00000000 );\r | |
146 | fRegs[kC10CPU2] = SimpleReg_t("C10CPU2", 0x0C12, 32, 0x00000000 );\r | |
147 | fRegs[kC11CPU2] = SimpleReg_t("C11CPU2", 0x0C13, 32, 0x00000000 );\r | |
148 | fRegs[kC08CPU3] = SimpleReg_t("C08CPU3", 0x0C18, 32, 0x00000000 );\r | |
149 | fRegs[kC09CPU3] = SimpleReg_t("C09CPU3", 0x0C19, 32, 0x00000000 );\r | |
150 | fRegs[kC10CPU3] = SimpleReg_t("C10CPU3", 0x0C1A, 32, 0x00000000 );\r | |
151 | fRegs[kC11CPU3] = SimpleReg_t("C11CPU3", 0x0C1B, 32, 0x00000000 );\r | |
152 | fRegs[kNMOD] = SimpleReg_t("NMOD", 0x0D40, 6, 0x08 ); // NI interface\r | |
153 | fRegs[kNDLY] = SimpleReg_t("NDLY", 0x0D41, 30, 0x24924924 );\r | |
154 | fRegs[kNED] = SimpleReg_t("NED", 0x0D42, 16, 0xA240 );\r | |
155 | fRegs[kNTRO] = SimpleReg_t("NTRO", 0x0D43, 18, 0x3FFFC );\r | |
156 | fRegs[kNRRO] = SimpleReg_t("NRRO", 0x0D44, 18, 0x3FFFC );\r | |
157 | fRegs[kNES] = SimpleReg_t("NES", 0x0D45, 32, 0x00000000 );\r | |
158 | fRegs[kNTP] = SimpleReg_t("NTP", 0x0D46, 32, 0x0000FFFF );\r | |
159 | fRegs[kNBND] = SimpleReg_t("NBND", 0x0D47, 16, 0x6020 );\r | |
160 | fRegs[kNP0] = SimpleReg_t("NP0", 0x0D48, 11, 0x44C );\r | |
161 | fRegs[kNP1] = SimpleReg_t("NP1", 0x0D49, 11, 0x44C );\r | |
162 | fRegs[kNP2] = SimpleReg_t("NP2", 0x0D4A, 11, 0x44C );\r | |
163 | fRegs[kNP3] = SimpleReg_t("NP3", 0x0D4B, 11, 0x44C );\r | |
164 | fRegs[kNCUT] = SimpleReg_t("NCUT", 0x0D4C, 32, 0xFFFFFFFF );\r | |
165 | fRegs[kTPPT0] = SimpleReg_t("TPPT0", 0x3000, 7, 0x01 ); // Filter and Preprocessor\r | |
166 | fRegs[kTPFS] = SimpleReg_t("TPFS", 0x3001, 7, 0x05 );\r | |
167 | fRegs[kTPFE] = SimpleReg_t("TPFE", 0x3002, 7, 0x14 );\r | |
168 | fRegs[kTPPGR] = SimpleReg_t("TPPGR", 0x3003, 7, 0x15 );\r | |
169 | fRegs[kTPPAE] = SimpleReg_t("TPPAE", 0x3004, 7, 0x1E );\r | |
170 | fRegs[kTPQS0] = SimpleReg_t("TPQS0", 0x3005, 7, 0x00 );\r | |
171 | fRegs[kTPQE0] = SimpleReg_t("TPQE0", 0x3006, 7, 0x0A );\r | |
172 | fRegs[kTPQS1] = SimpleReg_t("TPQS1", 0x3007, 7, 0x0B );\r | |
173 | fRegs[kTPQE1] = SimpleReg_t("TPQE1", 0x3008, 7, 0x14 );\r | |
174 | fRegs[kEBD] = SimpleReg_t("EBD", 0x3009, 3, 0x0 );\r | |
175 | fRegs[kEBAQA] = SimpleReg_t("EBAQA", 0x300A, 7, 0x00 );\r | |
176 | fRegs[kEBSIA] = SimpleReg_t("EBSIA", 0x300B, 7, 0x20 );\r | |
177 | fRegs[kEBSF] = SimpleReg_t("EBSF", 0x300C, 1, 0x1 );\r | |
178 | fRegs[kEBSIM] = SimpleReg_t("EBSIM", 0x300D, 1, 0x1 );\r | |
179 | fRegs[kEBPP] = SimpleReg_t("EBPP", 0x300E, 1, 0x1 );\r | |
180 | fRegs[kEBPC] = SimpleReg_t("EBPC", 0x300F, 1, 0x1 );\r | |
181 | fRegs[kEBIS] = SimpleReg_t("EBIS", 0x3014, 10, 0x005 );\r | |
182 | fRegs[kEBIT] = SimpleReg_t("EBIT", 0x3015, 12, 0x028 );\r | |
183 | fRegs[kEBIL] = SimpleReg_t("EBIL", 0x3016, 8, 0xF0 );\r | |
184 | fRegs[kEBIN] = SimpleReg_t("EBIN", 0x3017, 1, 0x1 );\r | |
185 | fRegs[kFLBY] = SimpleReg_t("FLBY", 0x3018, 1, 0x0 );\r | |
186 | fRegs[kFPBY] = SimpleReg_t("FPBY", 0x3019, 1, 0x0 );\r | |
187 | fRegs[kFGBY] = SimpleReg_t("FGBY", 0x301A, 1, 0x0 );\r | |
188 | fRegs[kFTBY] = SimpleReg_t("FTBY", 0x301B, 1, 0x0 );\r | |
189 | fRegs[kFCBY] = SimpleReg_t("FCBY", 0x301C, 1, 0x0 );\r | |
190 | fRegs[kFPTC] = SimpleReg_t("FPTC", 0x3020, 2, 0x3 );\r | |
191 | fRegs[kFPNP] = SimpleReg_t("FPNP", 0x3021, 9, 0x078 );\r | |
192 | fRegs[kFPCL] = SimpleReg_t("FPCL", 0x3022, 1, 0x1 );\r | |
193 | fRegs[kFGTA] = SimpleReg_t("FGTA", 0x3028, 12, 0x014 );\r | |
194 | fRegs[kFGTB] = SimpleReg_t("FGTB", 0x3029, 12, 0x80C );\r | |
195 | fRegs[kFGCL] = SimpleReg_t("FGCL", 0x302A, 1, 0x1 );\r | |
196 | fRegs[kFTAL] = SimpleReg_t("FTAL", 0x3030, 10, 0x0F6 );\r | |
197 | fRegs[kFTLL] = SimpleReg_t("FTLL", 0x3031, 9, 0x11D );\r | |
198 | fRegs[kFTLS] = SimpleReg_t("FTLS", 0x3032, 9, 0x0D3 );\r | |
199 | fRegs[kFCW1] = SimpleReg_t("FCW1", 0x3038, 8, 0x1E );\r | |
200 | fRegs[kFCW2] = SimpleReg_t("FCW2", 0x3039, 8, 0xD4 );\r | |
201 | fRegs[kFCW3] = SimpleReg_t("FCW3", 0x303A, 8, 0xE6 );\r | |
202 | fRegs[kFCW4] = SimpleReg_t("FCW4", 0x303B, 8, 0x4A );\r | |
203 | fRegs[kFCW5] = SimpleReg_t("FCW5", 0x303C, 8, 0xEF );\r | |
204 | fRegs[kTPFP] = SimpleReg_t("TPFP", 0x3040, 9, 0x037 );\r | |
205 | fRegs[kTPHT] = SimpleReg_t("TPHT", 0x3041, 14, 0x00A0 );\r | |
206 | fRegs[kTPVT] = SimpleReg_t("TPVT", 0x3042, 6, 0x00 );\r | |
207 | fRegs[kTPVBY] = SimpleReg_t("TPVBY", 0x3043, 1, 0x0 );\r | |
208 | fRegs[kTPCT] = SimpleReg_t("TPCT", 0x3044, 5, 0x08 );\r | |
209 | fRegs[kTPCL] = SimpleReg_t("TPCL", 0x3045, 5, 0x01 );\r | |
210 | fRegs[kTPCBY] = SimpleReg_t("TPCBY", 0x3046, 1, 0x1 );\r | |
211 | fRegs[kTPD] = SimpleReg_t("TPD", 0x3047, 4, 0xF );\r | |
212 | fRegs[kTPCI0] = SimpleReg_t("TPCI0", 0x3048, 5, 0x00 );\r | |
213 | fRegs[kTPCI1] = SimpleReg_t("TPCI1", 0x3049, 5, 0x00 );\r | |
214 | fRegs[kTPCI2] = SimpleReg_t("TPCI2", 0x304A, 5, 0x00 );\r | |
215 | fRegs[kTPCI3] = SimpleReg_t("TPCI3", 0x304B, 5, 0x00 );\r | |
216 | fRegs[kADCMSK] = SimpleReg_t("ADCMSK", 0x3050, 21, 0x1FFFFF );\r | |
217 | fRegs[kADCINB] = SimpleReg_t("ADCINB", 0x3051, 2, 0x2 );\r | |
218 | fRegs[kADCDAC] = SimpleReg_t("ADCDAC", 0x3052, 5, 0x10 );\r | |
219 | fRegs[kADCPAR] = SimpleReg_t("ADCPAR", 0x3053, 18, 0x195EF );\r | |
220 | fRegs[kADCTST] = SimpleReg_t("ADCTST", 0x3054, 2, 0x0 );\r | |
221 | fRegs[kSADCAZ] = SimpleReg_t("SADCAZ", 0x3055, 1, 0x1 );\r | |
222 | fRegs[kFGF0] = SimpleReg_t("FGF0", 0x3080, 9, 0x000 );\r | |
223 | fRegs[kFGF1] = SimpleReg_t("FGF1", 0x3081, 9, 0x000 );\r | |
224 | fRegs[kFGF2] = SimpleReg_t("FGF2", 0x3082, 9, 0x000 );\r | |
225 | fRegs[kFGF3] = SimpleReg_t("FGF3", 0x3083, 9, 0x000 );\r | |
226 | fRegs[kFGF4] = SimpleReg_t("FGF4", 0x3084, 9, 0x000 );\r | |
227 | fRegs[kFGF5] = SimpleReg_t("FGF5", 0x3085, 9, 0x000 );\r | |
228 | fRegs[kFGF6] = SimpleReg_t("FGF6", 0x3086, 9, 0x000 );\r | |
229 | fRegs[kFGF7] = SimpleReg_t("FGF7", 0x3087, 9, 0x000 );\r | |
230 | fRegs[kFGF8] = SimpleReg_t("FGF8", 0x3088, 9, 0x000 );\r | |
231 | fRegs[kFGF9] = SimpleReg_t("FGF9", 0x3089, 9, 0x000 );\r | |
232 | fRegs[kFGF10] = SimpleReg_t("FGF10", 0x308A, 9, 0x000 );\r | |
233 | fRegs[kFGF11] = SimpleReg_t("FGF11", 0x308B, 9, 0x000 );\r | |
234 | fRegs[kFGF12] = SimpleReg_t("FGF12", 0x308C, 9, 0x000 );\r | |
235 | fRegs[kFGF13] = SimpleReg_t("FGF13", 0x308D, 9, 0x000 );\r | |
236 | fRegs[kFGF14] = SimpleReg_t("FGF14", 0x308E, 9, 0x000 );\r | |
237 | fRegs[kFGF15] = SimpleReg_t("FGF15", 0x308F, 9, 0x000 );\r | |
238 | fRegs[kFGF16] = SimpleReg_t("FGF16", 0x3090, 9, 0x000 );\r | |
239 | fRegs[kFGF17] = SimpleReg_t("FGF17", 0x3091, 9, 0x000 );\r | |
240 | fRegs[kFGF18] = SimpleReg_t("FGF18", 0x3092, 9, 0x000 );\r | |
241 | fRegs[kFGF19] = SimpleReg_t("FGF19", 0x3093, 9, 0x000 );\r | |
242 | fRegs[kFGF20] = SimpleReg_t("FGF20", 0x3094, 9, 0x000 );\r | |
243 | fRegs[kFGA0] = SimpleReg_t("FGA0", 0x30A0, 6, 0x00 );\r | |
244 | fRegs[kFGA1] = SimpleReg_t("FGA1", 0x30A1, 6, 0x00 );\r | |
245 | fRegs[kFGA2] = SimpleReg_t("FGA2", 0x30A2, 6, 0x00 );\r | |
246 | fRegs[kFGA3] = SimpleReg_t("FGA3", 0x30A3, 6, 0x00 );\r | |
247 | fRegs[kFGA4] = SimpleReg_t("FGA4", 0x30A4, 6, 0x00 );\r | |
248 | fRegs[kFGA5] = SimpleReg_t("FGA5", 0x30A5, 6, 0x00 );\r | |
249 | fRegs[kFGA6] = SimpleReg_t("FGA6", 0x30A6, 6, 0x00 );\r | |
250 | fRegs[kFGA7] = SimpleReg_t("FGA7", 0x30A7, 6, 0x00 );\r | |
251 | fRegs[kFGA8] = SimpleReg_t("FGA8", 0x30A8, 6, 0x00 );\r | |
252 | fRegs[kFGA9] = SimpleReg_t("FGA9", 0x30A9, 6, 0x00 );\r | |
253 | fRegs[kFGA10] = SimpleReg_t("FGA10", 0x30AA, 6, 0x00 );\r | |
254 | fRegs[kFGA11] = SimpleReg_t("FGA11", 0x30AB, 6, 0x00 );\r | |
255 | fRegs[kFGA12] = SimpleReg_t("FGA12", 0x30AC, 6, 0x00 );\r | |
256 | fRegs[kFGA13] = SimpleReg_t("FGA13", 0x30AD, 6, 0x00 );\r | |
257 | fRegs[kFGA14] = SimpleReg_t("FGA14", 0x30AE, 6, 0x00 );\r | |
258 | fRegs[kFGA15] = SimpleReg_t("FGA15", 0x30AF, 6, 0x00 );\r | |
259 | fRegs[kFGA16] = SimpleReg_t("FGA16", 0x30B0, 6, 0x00 );\r | |
260 | fRegs[kFGA17] = SimpleReg_t("FGA17", 0x30B1, 6, 0x00 );\r | |
261 | fRegs[kFGA18] = SimpleReg_t("FGA18", 0x30B2, 6, 0x00 );\r | |
262 | fRegs[kFGA19] = SimpleReg_t("FGA19", 0x30B3, 6, 0x00 );\r | |
263 | fRegs[kFGA20] = SimpleReg_t("FGA20", 0x30B4, 6, 0x00 );\r | |
264 | fRegs[kFLL00] = SimpleReg_t("FLL00", 0x3100, 6, 0x00 ); // non-linearity table, 64 x 6 bits\r | |
265 | fRegs[kFLL01] = SimpleReg_t("FLL01", 0x3101, 6, 0x00 );\r | |
266 | fRegs[kFLL02] = SimpleReg_t("FLL02", 0x3102, 6, 0x00 );\r | |
267 | fRegs[kFLL03] = SimpleReg_t("FLL03", 0x3103, 6, 0x00 );\r | |
268 | fRegs[kFLL04] = SimpleReg_t("FLL04", 0x3104, 6, 0x00 );\r | |
269 | fRegs[kFLL05] = SimpleReg_t("FLL05", 0x3105, 6, 0x00 );\r | |
270 | fRegs[kFLL06] = SimpleReg_t("FLL06", 0x3106, 6, 0x00 );\r | |
271 | fRegs[kFLL07] = SimpleReg_t("FLL07", 0x3107, 6, 0x00 );\r | |
272 | fRegs[kFLL08] = SimpleReg_t("FLL08", 0x3108, 6, 0x00 );\r | |
273 | fRegs[kFLL09] = SimpleReg_t("FLL09", 0x3109, 6, 0x00 );\r | |
274 | fRegs[kFLL0A] = SimpleReg_t("FLL0A", 0x310A, 6, 0x00 );\r | |
275 | fRegs[kFLL0B] = SimpleReg_t("FLL0B", 0x310B, 6, 0x00 );\r | |
276 | fRegs[kFLL0C] = SimpleReg_t("FLL0C", 0x310C, 6, 0x00 );\r | |
277 | fRegs[kFLL0D] = SimpleReg_t("FLL0D", 0x310D, 6, 0x00 );\r | |
278 | fRegs[kFLL0E] = SimpleReg_t("FLL0E", 0x310E, 6, 0x00 );\r | |
279 | fRegs[kFLL0F] = SimpleReg_t("FLL0F", 0x310F, 6, 0x00 );\r | |
280 | fRegs[kFLL10] = SimpleReg_t("FLL10", 0x3110, 6, 0x00 );\r | |
281 | fRegs[kFLL11] = SimpleReg_t("FLL11", 0x3111, 6, 0x00 );\r | |
282 | fRegs[kFLL12] = SimpleReg_t("FLL12", 0x3112, 6, 0x00 );\r | |
283 | fRegs[kFLL13] = SimpleReg_t("FLL13", 0x3113, 6, 0x00 );\r | |
284 | fRegs[kFLL14] = SimpleReg_t("FLL14", 0x3114, 6, 0x00 );\r | |
285 | fRegs[kFLL15] = SimpleReg_t("FLL15", 0x3115, 6, 0x00 );\r | |
286 | fRegs[kFLL16] = SimpleReg_t("FLL16", 0x3116, 6, 0x00 );\r | |
287 | fRegs[kFLL17] = SimpleReg_t("FLL17", 0x3117, 6, 0x00 );\r | |
288 | fRegs[kFLL18] = SimpleReg_t("FLL18", 0x3118, 6, 0x00 );\r | |
289 | fRegs[kFLL19] = SimpleReg_t("FLL19", 0x3119, 6, 0x00 );\r | |
290 | fRegs[kFLL1A] = SimpleReg_t("FLL1A", 0x311A, 6, 0x00 );\r | |
291 | fRegs[kFLL1B] = SimpleReg_t("FLL1B", 0x311B, 6, 0x00 );\r | |
292 | fRegs[kFLL1C] = SimpleReg_t("FLL1C", 0x311C, 6, 0x00 );\r | |
293 | fRegs[kFLL1D] = SimpleReg_t("FLL1D", 0x311D, 6, 0x00 );\r | |
294 | fRegs[kFLL1E] = SimpleReg_t("FLL1E", 0x311E, 6, 0x00 );\r | |
295 | fRegs[kFLL1F] = SimpleReg_t("FLL1F", 0x311F, 6, 0x00 );\r | |
296 | fRegs[kFLL20] = SimpleReg_t("FLL20", 0x3120, 6, 0x00 );\r | |
297 | fRegs[kFLL21] = SimpleReg_t("FLL21", 0x3121, 6, 0x00 );\r | |
298 | fRegs[kFLL22] = SimpleReg_t("FLL22", 0x3122, 6, 0x00 );\r | |
299 | fRegs[kFLL23] = SimpleReg_t("FLL23", 0x3123, 6, 0x00 );\r | |
300 | fRegs[kFLL24] = SimpleReg_t("FLL24", 0x3124, 6, 0x00 );\r | |
301 | fRegs[kFLL25] = SimpleReg_t("FLL25", 0x3125, 6, 0x00 );\r | |
302 | fRegs[kFLL26] = SimpleReg_t("FLL26", 0x3126, 6, 0x00 );\r | |
303 | fRegs[kFLL27] = SimpleReg_t("FLL27", 0x3127, 6, 0x00 );\r | |
304 | fRegs[kFLL28] = SimpleReg_t("FLL28", 0x3128, 6, 0x00 );\r | |
305 | fRegs[kFLL29] = SimpleReg_t("FLL29", 0x3129, 6, 0x00 );\r | |
306 | fRegs[kFLL2A] = SimpleReg_t("FLL2A", 0x312A, 6, 0x00 );\r | |
307 | fRegs[kFLL2B] = SimpleReg_t("FLL2B", 0x312B, 6, 0x00 );\r | |
308 | fRegs[kFLL2C] = SimpleReg_t("FLL2C", 0x312C, 6, 0x00 );\r | |
309 | fRegs[kFLL2D] = SimpleReg_t("FLL2D", 0x312D, 6, 0x00 );\r | |
310 | fRegs[kFLL2E] = SimpleReg_t("FLL2E", 0x312E, 6, 0x00 );\r | |
311 | fRegs[kFLL2F] = SimpleReg_t("FLL2F", 0x312F, 6, 0x00 );\r | |
312 | fRegs[kFLL30] = SimpleReg_t("FLL30", 0x3130, 6, 0x00 );\r | |
313 | fRegs[kFLL31] = SimpleReg_t("FLL31", 0x3131, 6, 0x00 );\r | |
314 | fRegs[kFLL32] = SimpleReg_t("FLL32", 0x3132, 6, 0x00 );\r | |
315 | fRegs[kFLL33] = SimpleReg_t("FLL33", 0x3133, 6, 0x00 );\r | |
316 | fRegs[kFLL34] = SimpleReg_t("FLL34", 0x3134, 6, 0x00 );\r | |
317 | fRegs[kFLL35] = SimpleReg_t("FLL35", 0x3135, 6, 0x00 );\r | |
318 | fRegs[kFLL36] = SimpleReg_t("FLL36", 0x3136, 6, 0x00 );\r | |
319 | fRegs[kFLL37] = SimpleReg_t("FLL37", 0x3137, 6, 0x00 );\r | |
320 | fRegs[kFLL38] = SimpleReg_t("FLL38", 0x3138, 6, 0x00 );\r | |
321 | fRegs[kFLL39] = SimpleReg_t("FLL39", 0x3139, 6, 0x00 );\r | |
322 | fRegs[kFLL3A] = SimpleReg_t("FLL3A", 0x313A, 6, 0x00 );\r | |
323 | fRegs[kFLL3B] = SimpleReg_t("FLL3B", 0x313B, 6, 0x00 );\r | |
324 | fRegs[kFLL3C] = SimpleReg_t("FLL3C", 0x313C, 6, 0x00 );\r | |
325 | fRegs[kFLL3D] = SimpleReg_t("FLL3D", 0x313D, 6, 0x00 );\r | |
326 | fRegs[kFLL3E] = SimpleReg_t("FLL3E", 0x313E, 6, 0x00 );\r | |
327 | fRegs[kFLL3F] = SimpleReg_t("FLL3F", 0x313F, 6, 0x00 );\r | |
328 | fRegs[kPASADEL] = SimpleReg_t("PASADEL", 0x3158, 8, 0xFF ); // end of non-lin table\r | |
329 | fRegs[kPASAPHA] = SimpleReg_t("PASAPHA", 0x3159, 6, 0x3F );\r | |
330 | fRegs[kPASAPRA] = SimpleReg_t("PASAPRA", 0x315A, 6, 0x0F );\r | |
331 | fRegs[kPASADAC] = SimpleReg_t("PASADAC", 0x315B, 8, 0x80 );\r | |
332 | fRegs[kPASACHM] = SimpleReg_t("PASACHM", 0x315C, 19, 0x7FFFF );\r | |
333 | fRegs[kPASASTL] = SimpleReg_t("PASASTL", 0x315D, 8, 0xFF );\r | |
334 | fRegs[kPASAPR1] = SimpleReg_t("PASAPR1", 0x315E, 1, 0x0 );\r | |
335 | fRegs[kPASAPR0] = SimpleReg_t("PASAPR0", 0x315F, 1, 0x0 );\r | |
336 | fRegs[kSADCTRG] = SimpleReg_t("SADCTRG", 0x3161, 1, 0x0 );\r | |
337 | fRegs[kSADCRUN] = SimpleReg_t("SADCRUN", 0x3162, 1, 0x0 );\r | |
338 | fRegs[kSADCPWR] = SimpleReg_t("SADCPWR", 0x3163, 3, 0x7 );\r | |
339 | fRegs[kL0TSIM] = SimpleReg_t("L0TSIM", 0x3165, 14, 0x0050 );\r | |
340 | fRegs[kSADCEC] = SimpleReg_t("SADCEC", 0x3166, 7, 0x00 );\r | |
341 | fRegs[kSADCMC] = SimpleReg_t("SADCMC", 0x3170, 8, 0xC0 );\r | |
342 | fRegs[kSADCOC] = SimpleReg_t("SADCOC", 0x3171, 8, 0x19 );\r | |
343 | fRegs[kSADCGTB] = SimpleReg_t("SADCGTB", 0x3172, 32, 0x37737700 );\r | |
344 | fRegs[kSEBDEN] = SimpleReg_t("SEBDEN", 0x3178, 3, 0x0 );\r | |
345 | fRegs[kSEBDOU] = SimpleReg_t("SEBDOU", 0x3179, 3, 0x0 );\r | |
346 | fRegs[kTPL00] = SimpleReg_t("TPL00", 0x3180, 5, 0x00 ); // pos table, 128 x 5 bits\r | |
347 | fRegs[kTPL01] = SimpleReg_t("TPL01", 0x3181, 5, 0x00 );\r | |
348 | fRegs[kTPL02] = SimpleReg_t("TPL02", 0x3182, 5, 0x00 );\r | |
349 | fRegs[kTPL03] = SimpleReg_t("TPL03", 0x3183, 5, 0x00 );\r | |
350 | fRegs[kTPL04] = SimpleReg_t("TPL04", 0x3184, 5, 0x00 );\r | |
351 | fRegs[kTPL05] = SimpleReg_t("TPL05", 0x3185, 5, 0x00 );\r | |
352 | fRegs[kTPL06] = SimpleReg_t("TPL06", 0x3186, 5, 0x00 );\r | |
353 | fRegs[kTPL07] = SimpleReg_t("TPL07", 0x3187, 5, 0x00 );\r | |
354 | fRegs[kTPL08] = SimpleReg_t("TPL08", 0x3188, 5, 0x00 );\r | |
355 | fRegs[kTPL09] = SimpleReg_t("TPL09", 0x3189, 5, 0x00 );\r | |
356 | fRegs[kTPL0A] = SimpleReg_t("TPL0A", 0x318A, 5, 0x00 );\r | |
357 | fRegs[kTPL0B] = SimpleReg_t("TPL0B", 0x318B, 5, 0x00 );\r | |
358 | fRegs[kTPL0C] = SimpleReg_t("TPL0C", 0x318C, 5, 0x00 );\r | |
359 | fRegs[kTPL0D] = SimpleReg_t("TPL0D", 0x318D, 5, 0x00 );\r | |
360 | fRegs[kTPL0E] = SimpleReg_t("TPL0E", 0x318E, 5, 0x00 );\r | |
361 | fRegs[kTPL0F] = SimpleReg_t("TPL0F", 0x318F, 5, 0x00 );\r | |
362 | fRegs[kTPL10] = SimpleReg_t("TPL10", 0x3190, 5, 0x00 );\r | |
363 | fRegs[kTPL11] = SimpleReg_t("TPL11", 0x3191, 5, 0x00 );\r | |
364 | fRegs[kTPL12] = SimpleReg_t("TPL12", 0x3192, 5, 0x00 );\r | |
365 | fRegs[kTPL13] = SimpleReg_t("TPL13", 0x3193, 5, 0x00 );\r | |
366 | fRegs[kTPL14] = SimpleReg_t("TPL14", 0x3194, 5, 0x00 );\r | |
367 | fRegs[kTPL15] = SimpleReg_t("TPL15", 0x3195, 5, 0x00 );\r | |
368 | fRegs[kTPL16] = SimpleReg_t("TPL16", 0x3196, 5, 0x00 );\r | |
369 | fRegs[kTPL17] = SimpleReg_t("TPL17", 0x3197, 5, 0x00 );\r | |
370 | fRegs[kTPL18] = SimpleReg_t("TPL18", 0x3198, 5, 0x00 );\r | |
371 | fRegs[kTPL19] = SimpleReg_t("TPL19", 0x3199, 5, 0x00 );\r | |
372 | fRegs[kTPL1A] = SimpleReg_t("TPL1A", 0x319A, 5, 0x00 );\r | |
373 | fRegs[kTPL1B] = SimpleReg_t("TPL1B", 0x319B, 5, 0x00 );\r | |
374 | fRegs[kTPL1C] = SimpleReg_t("TPL1C", 0x319C, 5, 0x00 );\r | |
375 | fRegs[kTPL1D] = SimpleReg_t("TPL1D", 0x319D, 5, 0x00 );\r | |
376 | fRegs[kTPL1E] = SimpleReg_t("TPL1E", 0x319E, 5, 0x00 );\r | |
377 | fRegs[kTPL1F] = SimpleReg_t("TPL1F", 0x319F, 5, 0x00 );\r | |
378 | fRegs[kTPL20] = SimpleReg_t("TPL20", 0x31A0, 5, 0x00 );\r | |
379 | fRegs[kTPL21] = SimpleReg_t("TPL21", 0x31A1, 5, 0x00 );\r | |
380 | fRegs[kTPL22] = SimpleReg_t("TPL22", 0x31A2, 5, 0x00 );\r | |
381 | fRegs[kTPL23] = SimpleReg_t("TPL23", 0x31A3, 5, 0x00 );\r | |
382 | fRegs[kTPL24] = SimpleReg_t("TPL24", 0x31A4, 5, 0x00 );\r | |
383 | fRegs[kTPL25] = SimpleReg_t("TPL25", 0x31A5, 5, 0x00 );\r | |
384 | fRegs[kTPL26] = SimpleReg_t("TPL26", 0x31A6, 5, 0x00 );\r | |
385 | fRegs[kTPL27] = SimpleReg_t("TPL27", 0x31A7, 5, 0x00 );\r | |
386 | fRegs[kTPL28] = SimpleReg_t("TPL28", 0x31A8, 5, 0x00 );\r | |
387 | fRegs[kTPL29] = SimpleReg_t("TPL29", 0x31A9, 5, 0x00 );\r | |
388 | fRegs[kTPL2A] = SimpleReg_t("TPL2A", 0x31AA, 5, 0x00 );\r | |
389 | fRegs[kTPL2B] = SimpleReg_t("TPL2B", 0x31AB, 5, 0x00 );\r | |
390 | fRegs[kTPL2C] = SimpleReg_t("TPL2C", 0x31AC, 5, 0x00 );\r | |
391 | fRegs[kTPL2D] = SimpleReg_t("TPL2D", 0x31AD, 5, 0x00 );\r | |
392 | fRegs[kTPL2E] = SimpleReg_t("TPL2E", 0x31AE, 5, 0x00 );\r | |
393 | fRegs[kTPL2F] = SimpleReg_t("TPL2F", 0x31AF, 5, 0x00 );\r | |
394 | fRegs[kTPL30] = SimpleReg_t("TPL30", 0x31B0, 5, 0x00 );\r | |
395 | fRegs[kTPL31] = SimpleReg_t("TPL31", 0x31B1, 5, 0x00 );\r | |
396 | fRegs[kTPL32] = SimpleReg_t("TPL32", 0x31B2, 5, 0x00 );\r | |
397 | fRegs[kTPL33] = SimpleReg_t("TPL33", 0x31B3, 5, 0x00 );\r | |
398 | fRegs[kTPL34] = SimpleReg_t("TPL34", 0x31B4, 5, 0x00 );\r | |
399 | fRegs[kTPL35] = SimpleReg_t("TPL35", 0x31B5, 5, 0x00 );\r | |
400 | fRegs[kTPL36] = SimpleReg_t("TPL36", 0x31B6, 5, 0x00 );\r | |
401 | fRegs[kTPL37] = SimpleReg_t("TPL37", 0x31B7, 5, 0x00 );\r | |
402 | fRegs[kTPL38] = SimpleReg_t("TPL38", 0x31B8, 5, 0x00 );\r | |
403 | fRegs[kTPL39] = SimpleReg_t("TPL39", 0x31B9, 5, 0x00 );\r | |
404 | fRegs[kTPL3A] = SimpleReg_t("TPL3A", 0x31BA, 5, 0x00 );\r | |
405 | fRegs[kTPL3B] = SimpleReg_t("TPL3B", 0x31BB, 5, 0x00 );\r | |
406 | fRegs[kTPL3C] = SimpleReg_t("TPL3C", 0x31BC, 5, 0x00 );\r | |
407 | fRegs[kTPL3D] = SimpleReg_t("TPL3D", 0x31BD, 5, 0x00 );\r | |
408 | fRegs[kTPL3E] = SimpleReg_t("TPL3E", 0x31BE, 5, 0x00 );\r | |
409 | fRegs[kTPL3F] = SimpleReg_t("TPL3F", 0x31BF, 5, 0x00 );\r | |
410 | fRegs[kTPL40] = SimpleReg_t("TPL40", 0x31C0, 5, 0x00 );\r | |
411 | fRegs[kTPL41] = SimpleReg_t("TPL41", 0x31C1, 5, 0x00 );\r | |
412 | fRegs[kTPL42] = SimpleReg_t("TPL42", 0x31C2, 5, 0x00 );\r | |
413 | fRegs[kTPL43] = SimpleReg_t("TPL43", 0x31C3, 5, 0x00 );\r | |
414 | fRegs[kTPL44] = SimpleReg_t("TPL44", 0x31C4, 5, 0x00 );\r | |
415 | fRegs[kTPL45] = SimpleReg_t("TPL45", 0x31C5, 5, 0x00 );\r | |
416 | fRegs[kTPL46] = SimpleReg_t("TPL46", 0x31C6, 5, 0x00 );\r | |
417 | fRegs[kTPL47] = SimpleReg_t("TPL47", 0x31C7, 5, 0x00 );\r | |
418 | fRegs[kTPL48] = SimpleReg_t("TPL48", 0x31C8, 5, 0x00 );\r | |
419 | fRegs[kTPL49] = SimpleReg_t("TPL49", 0x31C9, 5, 0x00 );\r | |
420 | fRegs[kTPL4A] = SimpleReg_t("TPL4A", 0x31CA, 5, 0x00 );\r | |
421 | fRegs[kTPL4B] = SimpleReg_t("TPL4B", 0x31CB, 5, 0x00 );\r | |
422 | fRegs[kTPL4C] = SimpleReg_t("TPL4C", 0x31CC, 5, 0x00 );\r | |
423 | fRegs[kTPL4D] = SimpleReg_t("TPL4D", 0x31CD, 5, 0x00 );\r | |
424 | fRegs[kTPL4E] = SimpleReg_t("TPL4E", 0x31CE, 5, 0x00 );\r | |
425 | fRegs[kTPL4F] = SimpleReg_t("TPL4F", 0x31CF, 5, 0x00 );\r | |
426 | fRegs[kTPL50] = SimpleReg_t("TPL50", 0x31D0, 5, 0x00 );\r | |
427 | fRegs[kTPL51] = SimpleReg_t("TPL51", 0x31D1, 5, 0x00 );\r | |
428 | fRegs[kTPL52] = SimpleReg_t("TPL52", 0x31D2, 5, 0x00 );\r | |
429 | fRegs[kTPL53] = SimpleReg_t("TPL53", 0x31D3, 5, 0x00 );\r | |
430 | fRegs[kTPL54] = SimpleReg_t("TPL54", 0x31D4, 5, 0x00 );\r | |
431 | fRegs[kTPL55] = SimpleReg_t("TPL55", 0x31D5, 5, 0x00 );\r | |
432 | fRegs[kTPL56] = SimpleReg_t("TPL56", 0x31D6, 5, 0x00 );\r | |
433 | fRegs[kTPL57] = SimpleReg_t("TPL57", 0x31D7, 5, 0x00 );\r | |
434 | fRegs[kTPL58] = SimpleReg_t("TPL58", 0x31D8, 5, 0x00 );\r | |
435 | fRegs[kTPL59] = SimpleReg_t("TPL59", 0x31D9, 5, 0x00 );\r | |
436 | fRegs[kTPL5A] = SimpleReg_t("TPL5A", 0x31DA, 5, 0x00 );\r | |
437 | fRegs[kTPL5B] = SimpleReg_t("TPL5B", 0x31DB, 5, 0x00 );\r | |
438 | fRegs[kTPL5C] = SimpleReg_t("TPL5C", 0x31DC, 5, 0x00 );\r | |
439 | fRegs[kTPL5D] = SimpleReg_t("TPL5D", 0x31DD, 5, 0x00 );\r | |
440 | fRegs[kTPL5E] = SimpleReg_t("TPL5E", 0x31DE, 5, 0x00 );\r | |
441 | fRegs[kTPL5F] = SimpleReg_t("TPL5F", 0x31DF, 5, 0x00 );\r | |
442 | fRegs[kTPL60] = SimpleReg_t("TPL60", 0x31E0, 5, 0x00 );\r | |
443 | fRegs[kTPL61] = SimpleReg_t("TPL61", 0x31E1, 5, 0x00 );\r | |
444 | fRegs[kTPL62] = SimpleReg_t("TPL62", 0x31E2, 5, 0x00 );\r | |
445 | fRegs[kTPL63] = SimpleReg_t("TPL63", 0x31E3, 5, 0x00 );\r | |
446 | fRegs[kTPL64] = SimpleReg_t("TPL64", 0x31E4, 5, 0x00 );\r | |
447 | fRegs[kTPL65] = SimpleReg_t("TPL65", 0x31E5, 5, 0x00 );\r | |
448 | fRegs[kTPL66] = SimpleReg_t("TPL66", 0x31E6, 5, 0x00 );\r | |
449 | fRegs[kTPL67] = SimpleReg_t("TPL67", 0x31E7, 5, 0x00 );\r | |
450 | fRegs[kTPL68] = SimpleReg_t("TPL68", 0x31E8, 5, 0x00 );\r | |
451 | fRegs[kTPL69] = SimpleReg_t("TPL69", 0x31E9, 5, 0x00 );\r | |
452 | fRegs[kTPL6A] = SimpleReg_t("TPL6A", 0x31EA, 5, 0x00 );\r | |
453 | fRegs[kTPL6B] = SimpleReg_t("TPL6B", 0x31EB, 5, 0x00 );\r | |
454 | fRegs[kTPL6C] = SimpleReg_t("TPL6C", 0x31EC, 5, 0x00 );\r | |
455 | fRegs[kTPL6D] = SimpleReg_t("TPL6D", 0x31ED, 5, 0x00 );\r | |
456 | fRegs[kTPL6E] = SimpleReg_t("TPL6E", 0x31EE, 5, 0x00 );\r | |
457 | fRegs[kTPL6F] = SimpleReg_t("TPL6F", 0x31EF, 5, 0x00 );\r | |
458 | fRegs[kTPL70] = SimpleReg_t("TPL70", 0x31F0, 5, 0x00 );\r | |
459 | fRegs[kTPL71] = SimpleReg_t("TPL71", 0x31F1, 5, 0x00 );\r | |
460 | fRegs[kTPL72] = SimpleReg_t("TPL72", 0x31F2, 5, 0x00 );\r | |
461 | fRegs[kTPL73] = SimpleReg_t("TPL73", 0x31F3, 5, 0x00 );\r | |
462 | fRegs[kTPL74] = SimpleReg_t("TPL74", 0x31F4, 5, 0x00 );\r | |
463 | fRegs[kTPL75] = SimpleReg_t("TPL75", 0x31F5, 5, 0x00 );\r | |
464 | fRegs[kTPL76] = SimpleReg_t("TPL76", 0x31F6, 5, 0x00 );\r | |
465 | fRegs[kTPL77] = SimpleReg_t("TPL77", 0x31F7, 5, 0x00 );\r | |
466 | fRegs[kTPL78] = SimpleReg_t("TPL78", 0x31F8, 5, 0x00 );\r | |
467 | fRegs[kTPL79] = SimpleReg_t("TPL79", 0x31F9, 5, 0x00 );\r | |
468 | fRegs[kTPL7A] = SimpleReg_t("TPL7A", 0x31FA, 5, 0x00 );\r | |
469 | fRegs[kTPL7B] = SimpleReg_t("TPL7B", 0x31FB, 5, 0x00 );\r | |
470 | fRegs[kTPL7C] = SimpleReg_t("TPL7C", 0x31FC, 5, 0x00 );\r | |
471 | fRegs[kTPL7D] = SimpleReg_t("TPL7D", 0x31FD, 5, 0x00 );\r | |
472 | fRegs[kTPL7E] = SimpleReg_t("TPL7E", 0x31FE, 5, 0x00 );\r | |
473 | fRegs[kTPL7F] = SimpleReg_t("TPL7F", 0x31FF, 5, 0x00 );\r | |
474 | fRegs[kMEMRW] = SimpleReg_t("MEMRW", 0xD000, 7, 0x79 ); // end of pos table\r | |
475 | fRegs[kMEMCOR] = SimpleReg_t("MEMCOR", 0xD001, 9, 0x000 );\r | |
476 | fRegs[kDMDELA] = SimpleReg_t("DMDELA", 0xD002, 4, 0x8 );\r | |
477 | fRegs[kDMDELS] = SimpleReg_t("DMDELS", 0xD003, 4, 0x8 );\r | |
478 | \r | |
78d5287e | 479 | InitRegs();\r |
7627bf12 | 480 | }\r |
481 | \r | |
7d298182 | 482 | \r |
7627bf12 | 483 | AliTRDtrapConfig* AliTRDtrapConfig::Instance()\r |
484 | {\r | |
485 | // return a pointer to an instance of this class\r | |
486 | \r | |
64e3d742 | 487 | if (!fgInstance) {\r |
7627bf12 | 488 | fgInstance = new AliTRDtrapConfig();\r |
64e3d742 | 489 | fgInstance->LoadConfig();\r |
490 | }\r | |
491 | \r | |
7627bf12 | 492 | return fgInstance;\r |
493 | }\r | |
494 | \r | |
7d298182 | 495 | \r |
78d5287e | 496 | void AliTRDtrapConfig::InitRegs(void)\r |
497 | {\r | |
498 | // Reset the content of all TRAP registers to the reset values (see TRAP User Manual)\r | |
499 | \r | |
500 | for (Int_t iReg = 0; iReg < kLastReg; iReg++) {\r | |
501 | \r | |
502 | fRegisterValue[iReg].individualValue = 0x0;\r | |
503 | \r | |
504 | fRegisterValue[iReg].globalValue = GetRegResetValue((TrapReg_t) iReg);\r | |
505 | fRegisterValue[iReg].state = RegValue_t::kGlobal;\r | |
506 | }\r | |
507 | }\r | |
508 | \r | |
7d298182 | 509 | void AliTRDtrapConfig::ResetRegs(void)\r |
510 | {\r | |
511 | // Reset the content of all TRAP registers to the reset values (see TRAP User Manual)\r | |
512 | \r | |
513 | for (Int_t iReg = 0; iReg < kLastReg; iReg++) {\r | |
514 | if(fRegisterValue[iReg].state == RegValue_t::kIndividual) {\r | |
78d5287e | 515 | if (fRegisterValue[iReg].individualValue) {\r |
516 | delete [] fRegisterValue[iReg].individualValue;\r | |
517 | fRegisterValue[iReg].individualValue = 0x0;\r | |
518 | }\r | |
7d298182 | 519 | }\r |
520 | \r | |
521 | fRegisterValue[iReg].globalValue = GetRegResetValue((TrapReg_t) iReg);\r | |
522 | fRegisterValue[iReg].state = RegValue_t::kGlobal;\r | |
523 | // printf("%-8s: 0x%08x\n", GetRegName((TrapReg_t) iReg), fRegisterValue[iReg].globalValue);\r | |
524 | }\r | |
525 | }\r | |
526 | \r | |
527 | \r | |
7627bf12 | 528 | Int_t AliTRDtrapConfig::GetTrapReg(TrapReg_t reg, Int_t det, Int_t rob, Int_t mcm)\r |
529 | {\r | |
530 | // get the value of an individual TRAP register \r | |
531 | // if it is individual for TRAPs a valid TRAP has to be specified\r | |
532 | \r | |
533 | if ((reg < 0) || (reg >= kLastReg)) {\r | |
534 | AliError("Non-existing register requested");\r | |
535 | return -1;\r | |
536 | }\r | |
537 | else {\r | |
538 | if (fRegisterValue[reg].state == RegValue_t::kGlobal) {\r | |
539 | return fRegisterValue[reg].globalValue;\r | |
540 | }\r | |
541 | else if (fRegisterValue[reg].state == RegValue_t::kIndividual) {\r | |
7d298182 | 542 | if((det >= 0 && det < AliTRDgeometry::Ndet()) && \r |
543 | (rob >= 0 && rob < AliTRDfeeParam::GetNrobC1()) && \r | |
544 | (mcm >= 0 && mcm < fgkMaxMcm)) {\r | |
545 | return fRegisterValue[reg].individualValue[det*AliTRDfeeParam::GetNrobC1()*fgkMaxMcm + rob*fgkMaxMcm + mcm];\r | |
546 | }\r | |
547 | else {\r | |
548 | AliError("Invalid MCM specified or register is individual");\r | |
549 | return -1;\r | |
550 | }\r | |
551 | }\r | |
552 | else { // should never be reached\r | |
553 | AliError("MCM register status neither kGlobal nor kIndividual");\r | |
554 | return -1;\r | |
7627bf12 | 555 | }\r |
556 | }\r | |
557 | return -1;\r | |
558 | }\r | |
559 | \r | |
7d298182 | 560 | \r |
561 | Bool_t AliTRDtrapConfig::SetTrapReg(TrapReg_t reg, Int_t value)\r | |
7627bf12 | 562 | {\r |
7d298182 | 563 | // set a global value for the given TRAP register,\r |
564 | // i.e. the same value for all TRAPs\r | |
7627bf12 | 565 | \r |
7d298182 | 566 | if (fRegisterValue[reg].state == RegValue_t::kGlobal) {\r |
7627bf12 | 567 | fRegisterValue[reg].globalValue = value;\r |
7d298182 | 568 | return kTRUE;\r |
569 | }\r | |
570 | else {\r | |
571 | AliError("Register has individual values");\r | |
572 | }\r | |
573 | return kFALSE;\r | |
574 | }\r | |
575 | \r | |
576 | \r | |
577 | Bool_t AliTRDtrapConfig::SetTrapReg(TrapReg_t reg, Int_t value, Int_t det)\r | |
578 | {\r | |
579 | // set a global value for the given TRAP register,\r | |
580 | // i.e. the same value for all TRAPs\r | |
581 | \r | |
582 | if (fRegisterValue[reg].state == RegValue_t::kGlobal) {\r | |
7627bf12 | 583 | fRegisterValue[reg].globalValue = value;\r |
7d298182 | 584 | return kTRUE;\r |
585 | }\r | |
586 | else if (fRegisterValue[reg].state == RegValue_t::kIndividual) {\r | |
587 | // if the register is in idividual mode but a broadcast is requested, the selected register is \r | |
588 | // set to value for all MCMs on the chamber\r | |
589 | \r | |
590 | if( (det>=0 && det<AliTRDgeometry::Ndet())) {\r | |
591 | for(Int_t rob=0; rob<AliTRDfeeParam::GetNrobC1(); rob++) {\r | |
592 | for(Int_t mcm=0; mcm<fgkMaxMcm; mcm++)\r | |
593 | fRegisterValue[reg].individualValue[det*AliTRDfeeParam::GetNrobC1()*fgkMaxMcm + rob*fgkMaxMcm + mcm] = value;\r | |
594 | }\r | |
595 | }\r | |
596 | else {\r | |
597 | AliError("Invalid value for det, ROB or MCM selected");\r | |
598 | return kFALSE;\r | |
599 | }\r | |
600 | }\r | |
601 | else { // should never be reached\r | |
602 | AliError("MCM register status neither kGlobal nor kIndividual");\r | |
7627bf12 | 603 | return kFALSE;\r |
7d298182 | 604 | }\r |
605 | \r | |
606 | return kFALSE;\r | |
607 | }\r | |
608 | \r | |
609 | \r | |
610 | Bool_t AliTRDtrapConfig::SetTrapReg(TrapReg_t reg, Int_t value, Int_t det, Int_t rob, Int_t mcm)\r | |
611 | {\r | |
612 | // set the value for the given TRAP register of an individual MCM \r | |
613 | \r | |
614 | //std::cout << "-- reg: 0x" << std::hex << fRegs[reg].addr << std::dec << ", data " << value << ", det " << det << ", rob " << rob << ", mcm " << mcm << std::endl;\r | |
615 | \r | |
616 | if( (det >= 0 && det < AliTRDgeometry::Ndet()) && \r | |
617 | (rob >= 0 && rob < AliTRDfeeParam::GetNrobC1()) && \r | |
618 | (mcm >= 0 && mcm < fgkMaxMcm) ) {\r | |
619 | if (fRegisterValue[reg].state == RegValue_t::kGlobal) {\r | |
620 | Int_t defaultValue = fRegisterValue[reg].globalValue;\r | |
621 | \r | |
622 | fRegisterValue[reg].state = RegValue_t::kIndividual;\r | |
623 | fRegisterValue[reg].individualValue = new Int_t[AliTRDgeometry::Ndet()*AliTRDfeeParam::GetNrobC1()*fgkMaxMcm];\r | |
624 | \r | |
625 | for(Int_t i = 0; i < AliTRDgeometry::Ndet()*AliTRDfeeParam::GetNrobC1()*fgkMaxMcm; i++)\r | |
626 | fRegisterValue[reg].individualValue[i] = defaultValue; // set the requested register of all MCMs to the value previously stored\r | |
627 | \r | |
628 | fRegisterValue[reg].individualValue[det*AliTRDfeeParam::GetNrobC1()*fgkMaxMcm + rob*fgkMaxMcm + mcm] = value;\r | |
629 | }\r | |
630 | else if (fRegisterValue[reg].state == RegValue_t::kIndividual) {\r | |
631 | fRegisterValue[reg].individualValue[det*AliTRDfeeParam::GetNrobC1()*fgkMaxMcm + rob*fgkMaxMcm + mcm] = value;\r | |
632 | }\r | |
633 | else { // should never be reached\r | |
634 | AliError("MCM register status neither kGlobal nor kIndividual");\r | |
635 | return kFALSE;\r | |
636 | }\r | |
7627bf12 | 637 | }\r |
7d298182 | 638 | else {\r |
639 | AliError("Invalid value for det, ROB or MCM selected");\r | |
640 | return kFALSE;\r | |
641 | }\r | |
642 | \r | |
7627bf12 | 643 | return kTRUE;\r |
644 | }\r | |
645 | \r | |
7d298182 | 646 | \r |
7627bf12 | 647 | Bool_t AliTRDtrapConfig::LoadConfig()\r |
648 | {\r | |
649 | // load a set of TRAP register values (configuration)\r | |
7d298182 | 650 | // here a default set is implemented for testing\r |
7627bf12 | 651 | // for a detailed description of the registers see the TRAP manual\r |
652 | \r | |
7627bf12 | 653 | // pedestal filter\r |
654 | SetTrapReg(kFPNP, 4*10);\r | |
655 | SetTrapReg(kFPTC, 0);\r | |
64e3d742 | 656 | SetTrapReg(kFPBY, 0); // bypassed!\r |
7627bf12 | 657 | \r |
658 | // gain filter\r | |
659 | for (Int_t adc = 0; adc < 20; adc++) {\r | |
660 | SetTrapReg(TrapReg_t(kFGA0+adc), 40);\r | |
661 | SetTrapReg(TrapReg_t(kFGF0+adc), 15);\r | |
662 | }\r | |
663 | SetTrapReg(kFGTA, 20);\r | |
664 | SetTrapReg(kFGTB, 2060);\r | |
665 | SetTrapReg(kFGBY, 0); // bypassed!\r | |
666 | \r | |
667 | // tail cancellation\r | |
64e3d742 | 668 | SetTrapReg(kFTAL, 267);\r |
669 | SetTrapReg(kFTLL, 356);\r | |
670 | SetTrapReg(kFTLS, 387);\r | |
4ff7ed2b | 671 | SetTrapReg(kFTBY, 0);\r |
7627bf12 | 672 | \r |
673 | // tracklet calculation\r | |
674 | SetTrapReg(kTPQS0, 5);\r | |
675 | SetTrapReg(kTPQE0, 10);\r | |
676 | SetTrapReg(kTPQS1, 11);\r | |
677 | SetTrapReg(kTPQE1, 20);\r | |
678 | SetTrapReg(kTPFS, 5);\r | |
679 | SetTrapReg(kTPFE, 20);\r | |
680 | SetTrapReg(kTPVBY, 0);\r | |
681 | SetTrapReg(kTPVT, 10);\r | |
af3880b4 | 682 | SetTrapReg(kTPHT, 60);\r |
683 | SetTrapReg(kTPFP, 10);\r | |
64e3d742 | 684 | SetTrapReg(kTPCL, 1);\r |
685 | SetTrapReg(kTPCT, 8);\r | |
7627bf12 | 686 | \r |
687 | // event buffer\r | |
688 | SetTrapReg(kEBSF, 1); // 0: store filtered; 1: store unfiltered\r | |
689 | // zs applied to data stored in event buffer (sel. by EBSF)\r | |
af3880b4 | 690 | SetTrapReg(kEBIS, 15 << 2); // single indicator threshold (plus two digits)\r |
691 | SetTrapReg(kEBIT, 30 << 2); // sum indicator threshold (plus two digits)\r | |
7627bf12 | 692 | SetTrapReg(kEBIL, 0xf0); // lookup table\r |
64e3d742 | 693 | SetTrapReg(kEBIN, 0); // neighbour sensitivity\r |
694 | \r | |
695 | // raw data\r | |
696 | SetTrapReg(kNES, (0x0000 << 16) | 0x1000);\r | |
7627bf12 | 697 | \r |
698 | return kTRUE;\r | |
699 | }\r | |
700 | \r | |
7d298182 | 701 | \r |
702 | Bool_t AliTRDtrapConfig::LoadConfig(Int_t det, TString filename)\r | |
703 | {\r | |
704 | // load a TRAP configuration from a file\r | |
705 | // The file format is the format created by the standalone \r | |
706 | // command coder: scc / show_cfdat \r | |
707 | // which are two tools to inspect/export configurations from wingDB\r | |
708 | \r | |
709 | ResetRegs(); // does not really make sense here???\r | |
710 | \r | |
711 | std::ifstream infile;\r | |
712 | infile.open(filename.Data(), std::ifstream::in);\r | |
713 | if (!infile.is_open()) {\r | |
714 | AliError("Can not open MCM configuration file");\r | |
715 | return kFALSE;\r | |
716 | }\r | |
717 | \r | |
718 | Int_t cmd, extali, addr, data;\r | |
719 | Int_t no;\r | |
720 | char tmp;\r | |
721 | \r | |
722 | while(infile.good()) {\r | |
723 | cmd=-1;\r | |
724 | extali=-1;\r | |
725 | addr=-1;\r | |
726 | data=-1;\r | |
727 | infile >> std::skipws >> no >> tmp >> cmd >> extali >> addr >> data;\r | |
728 | // std::cout << "no: " << no << ", cmd " << cmd << ", extali " << extali << ", addr " << addr << ", data " << data << endl;\r | |
729 | \r | |
730 | if(cmd!=-1 && extali!=-1 && addr != -1 && data!= -1) {\r | |
731 | AddValues(det, cmd, extali, addr, data);\r | |
732 | }\r | |
733 | else if(!infile.eof() && !infile.good()) {\r | |
734 | infile.clear();\r | |
735 | infile.ignore(256, '\n');\r | |
736 | }\r | |
737 | \r | |
738 | if(!infile.eof())\r | |
739 | infile.clear();\r | |
740 | }\r | |
741 | \r | |
742 | infile.close();\r | |
743 | \r | |
744 | return kTRUE;\r | |
745 | }\r | |
746 | \r | |
747 | \r | |
748 | Bool_t AliTRDtrapConfig::PrintTrapReg(TrapReg_t reg, Int_t det, Int_t rob, Int_t mcm)\r | |
7627bf12 | 749 | {\r |
7d298182 | 750 | // print the value stored in the given register\r |
7627bf12 | 751 | // if it is individual a valid MCM has to be specified\r |
752 | \r | |
753 | if (fRegisterValue[reg].state == RegValue_t::kGlobal) {\r | |
7d298182 | 754 | printf("%s (%i bits) at 0x%08x is 0x%08x and resets to: 0x%08x (currently global mode)\n", \r |
7627bf12 | 755 | GetRegName((TrapReg_t) reg),\r |
756 | GetRegNBits((TrapReg_t) reg),\r | |
757 | GetRegAddress((TrapReg_t) reg),\r | |
758 | fRegisterValue[reg].globalValue,\r | |
759 | GetRegResetValue((TrapReg_t) reg));\r | |
760 | }\r | |
761 | else if (fRegisterValue[reg].state == RegValue_t::kIndividual) {\r | |
7d298182 | 762 | if((det >= 0 && det < AliTRDgeometry::Ndet()) && \r |
763 | (rob >= 0 && rob < AliTRDfeeParam::GetNrobC1()) && \r | |
764 | (mcm >= 0 && mcm < fgkMaxMcm)) {\r | |
765 | printf("%s (%i bits) at 0x%08x is 0x%08x and resets to: 0x%08x (currently individual mode)\n", \r | |
7627bf12 | 766 | GetRegName((TrapReg_t) reg),\r |
767 | GetRegNBits((TrapReg_t) reg),\r | |
768 | GetRegAddress((TrapReg_t) reg),\r | |
7d298182 | 769 | fRegisterValue[reg].individualValue[det*AliTRDfeeParam::GetNrobC1()*fgkMaxMcm + rob*fgkMaxMcm + mcm],\r |
7627bf12 | 770 | GetRegResetValue((TrapReg_t) reg));\r |
771 | }\r | |
7d298182 | 772 | else {\r |
773 | AliError("Register value is MCM-specific: Invalid detector, ROB or MCM requested");\r | |
774 | return kFALSE;\r | |
775 | }\r | |
776 | }\r | |
777 | else { // should never be reached\r | |
778 | AliError("MCM register status neither kGlobal nor kIndividual");\r | |
779 | return kFALSE;\r | |
780 | }\r | |
781 | return kTRUE;\r | |
782 | }\r | |
783 | \r | |
784 | \r | |
785 | Bool_t AliTRDtrapConfig::PrintTrapAddr(Int_t addr, Int_t det, Int_t rob, Int_t mcm)\r | |
786 | {\r | |
787 | // print the value stored at the given address in the MCM chip\r | |
788 | TrapReg_t reg = GetRegByAddress(addr);\r | |
789 | if (reg >= 0 && reg < kLastReg) {\r | |
790 | return PrintTrapReg(reg, det, rob, mcm);\r | |
791 | }\r | |
792 | else {\r | |
793 | AliError(Form("There is no register at address 0x%08x in the simulator", addr));\r | |
794 | return kFALSE;\r | |
795 | }\r | |
796 | }\r | |
797 | \r | |
798 | \r | |
799 | Bool_t AliTRDtrapConfig::AddValues(UInt_t det, UInt_t cmd, UInt_t extali, UInt_t addr, UInt_t data)\r | |
800 | {\r | |
801 | // transfer the informations provided by LoadConfig to the internal class variables\r | |
802 | \r | |
803 | if(cmd != fgkScsnCmdWrite) {\r | |
804 | AliError(Form("Invalid command received: %i", cmd));\r | |
805 | return kFALSE;\r | |
806 | }\r | |
807 | \r | |
808 | TrapReg_t mcmReg = GetRegByAddress(addr);\r | |
809 | \r | |
810 | if(mcmReg >= 0 && mcmReg < kLastReg) {\r | |
811 | Int_t rocType = AliTRDgeometry::GetStack(det) == 2 ? 0 : 1;\r | |
812 | \r | |
813 | for(Int_t linkPair=0; linkPair<fgkMaxLinkPairs; linkPair++) {\r | |
814 | if(ExtAliToAli(extali, linkPair, rocType)!=0) {\r | |
815 | Int_t i=0;\r | |
36dc3337 | 816 | while(fMcmlist[i] != -1 && i<fgkMcmlistSize) {\r |
7d298182 | 817 | if(fMcmlist[i]==127)\r |
818 | SetTrapReg( (TrapReg_t) mcmReg, data, det);\r | |
819 | else\r | |
820 | SetTrapReg( (TrapReg_t) mcmReg, data, det, (fMcmlist[i]>>7), (fMcmlist[i]&0x7F));\r | |
821 | i++;\r | |
822 | }\r | |
823 | }\r | |
824 | }\r | |
825 | return kTRUE;\r | |
826 | }\r | |
827 | else \r | |
828 | return kFALSE;\r | |
829 | }\r | |
830 | \r | |
831 | \r | |
832 | Int_t AliTRDtrapConfig::ExtAliToAli( UInt_t dest, UShort_t linkpair, UShort_t rocType)\r | |
833 | {\r | |
834 | // Converts an extended ALICE ID which identifies a single MCM or a group of MCMs to\r | |
835 | // the corresponding list of MCMs. Only broadcasts (127) are encoded as 127 \r | |
836 | // The return value is the number of MCMs in the list\r | |
837 | \r | |
838 | fMcmlist[0]=-1;\r | |
839 | \r | |
840 | Short_t nmcm = 0;\r | |
841 | UInt_t mcm, rob, robAB;\r | |
842 | UInt_t cmA = 0, cmB = 0; // Chipmask for each A and B side\r | |
843 | \r | |
844 | // Default chipmask for 4 linkpairs (each bit correponds each alice-mcm)\r | |
845 | static const UInt_t gkChipmaskDefLp[4] = { 0x1FFFF, 0x1FFFF, 0x3FFFF, 0x1FFFF };\r | |
846 | \r | |
847 | rob = dest >> 7; // Extract ROB pattern from dest.\r | |
848 | mcm = dest & 0x07F; // Extract MCM pattern from dest.\r | |
849 | robAB = GetRobAB( rob, linkpair ); // Get which ROB sides are selected.\r | |
850 | \r | |
851 | // Abort if no ROB is selected\r | |
852 | if( robAB == 0 ) {\r | |
853 | return 0;\r | |
854 | }\r | |
855 | \r | |
856 | // Special case\r | |
857 | if( mcm == 127 ) {\r | |
858 | if( robAB == 3 ) { // This is very special 127 can stay only if two ROBs are selected\r | |
859 | fMcmlist[0]=127; // broadcase to ALL\r | |
860 | fMcmlist[1]=-1;\r | |
861 | return 1;\r | |
862 | }\r | |
863 | cmA = cmB = 0x3FFFF;\r | |
864 | } else if( (mcm & 0x40) != 0 ) { // If top bit is 1 but not 127, this is chip group.\r | |
865 | if( (mcm & 0x01) != 0 ) { cmA |= 0x04444; cmB |= 0x04444; } // chip_cmrg\r | |
866 | if( (mcm & 0x02) != 0 ) { cmA |= 0x10000; cmB |= 0x10000; } // chip_bmrg\r | |
867 | if( (mcm & 0x04) != 0 && rocType == 0 ) { cmA |= 0x20000; cmB |= 0x20000; } // chip_hm3\r | |
868 | if( (mcm & 0x08) != 0 && rocType == 1 ) { cmA |= 0x20000; cmB |= 0x20000; } // chip_hm4\r | |
869 | if( (mcm & 0x10) != 0 ) { cmA |= 0x01111; cmB |= 0x08888; } // chip_edge\r | |
870 | if( (mcm & 0x20) != 0 ) { cmA |= 0x0aaaa; cmB |= 0x03333; } // chip_norm\r | |
871 | } else { // Otherwise, this is normal chip ID, turn on only one chip.\r | |
872 | cmA = 1 << mcm;\r | |
873 | cmB = 1 << mcm;\r | |
7627bf12 | 874 | }\r |
7d298182 | 875 | \r |
876 | // Mask non-existing MCMs\r | |
877 | cmA &= gkChipmaskDefLp[linkpair];\r | |
878 | cmB &= gkChipmaskDefLp[linkpair];\r | |
879 | // Remove if only one side is selected\r | |
880 | if( robAB == 1 ) \r | |
881 | cmB = 0;\r | |
882 | if( robAB == 2 ) \r | |
883 | cmA = 0;\r | |
884 | if( robAB == 4 && linkpair != 2 ) \r | |
885 | cmA = cmB = 0; // Restrict to only T3A and T3B\r | |
886 | \r | |
887 | // Finally convert chipmask to list of slaves\r | |
888 | nmcm = ChipmaskToMCMlist( cmA, cmB, linkpair );\r | |
889 | \r | |
890 | return nmcm;\r | |
7627bf12 | 891 | }\r |
7d298182 | 892 | \r |
893 | \r | |
36dc3337 | 894 | Short_t AliTRDtrapConfig::GetRobAB( UShort_t robsel, UShort_t linkpair ) const\r |
7d298182 | 895 | {\r |
896 | // Converts the ROB part of the extended ALICE ID to robs\r | |
897 | \r | |
898 | if( (robsel & 0x8) != 0 ) { // 1000 .. direct ROB selection. Only one of the 8 ROBs are used.\r | |
899 | robsel = robsel & 7;\r | |
900 | if( (robsel % 2) == 0 && (robsel / 2) == linkpair ) \r | |
901 | return 1; // Even means A side (position 0,2,4,6)\r | |
902 | if( (robsel % 2) == 1 && (robsel / 2) == linkpair ) \r | |
903 | return 2; // Odd means B side (position 1,3,5,7)\r | |
904 | return 0;\r | |
905 | }\r | |
906 | \r | |
907 | // ROB group\r | |
908 | if( robsel == 0 ) { return 3; } // Both ROB\r | |
909 | if( robsel == 1 ) { return 1; } // A-side ROB\r | |
910 | if( robsel == 2 ) { return 2; } // B-side ROB\r | |
911 | if( robsel == 3 ) { return 3; } // Both ROB\r | |
912 | if( robsel == 4 ) { return 4; } // Only T3A and T3B\r | |
913 | // Other number 5 to 7 are ignored (not defined) \r | |
914 | \r | |
915 | return 0;\r | |
916 | }\r | |
917 | \r | |
918 | \r | |
919 | Short_t AliTRDtrapConfig::ChipmaskToMCMlist( Int_t cmA, Int_t cmB, UShort_t linkpair )\r | |
920 | {\r | |
921 | // Converts the chipmask to a list of MCMs \r | |
922 | \r | |
923 | Short_t nmcm = 0;\r | |
924 | Short_t i;\r | |
925 | for( i = 0 ; i < fgkMaxMcm ; i++ ) {\r | |
926 | if( (cmA & (1 << i)) != 0 ) {\r | |
927 | fMcmlist[nmcm] = (linkpair*2 << 7) | i;\r | |
928 | ++nmcm;\r | |
929 | }\r | |
930 | if( (cmB & (1 << i)) != 0 ) {\r | |
931 | fMcmlist[nmcm] = (linkpair*2+1 << 7) | i;\r | |
932 | ++nmcm;\r | |
933 | }\r | |
934 | }\r | |
935 | \r | |
936 | fMcmlist[nmcm]=-1;\r | |
937 | return nmcm;\r | |
938 | }\r | |
939 | \r | |
940 | \r | |
36dc3337 | 941 | AliTRDtrapConfig::TrapReg_t AliTRDtrapConfig::GetRegByAddress(Int_t address) const\r |
7d298182 | 942 | {\r |
36dc3337 | 943 | // get register by its address |
944 | // used for reading of configuration data as sent to real FEE | |
945 | ||
7d298182 | 946 | TrapReg_t mcmReg = kLastReg;\r |
947 | Int_t reg = 0;\r | |
948 | do {\r | |
36dc3337 | 949 | if(fRegs[reg].fAddr == address)\r |
7d298182 | 950 | mcmReg = (TrapReg_t) reg;\r |
951 | reg++;\r | |
952 | } while (mcmReg == kLastReg && reg < kLastReg);\r | |
953 | \r | |
954 | return mcmReg;\r | |
955 | }\r | |
956 | \r | |
957 | \r |