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[u/mrichter/AliRoot.git] / TRD / AliTRDtrapConfig.cxx
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36dc3337 1/**************************************************************************
2 * Copyright(c) 1998-1999, ALICE Experiment at CERN, All rights reserved. *
3 * *
4 * Author: The ALICE Off-line Project. *
5 * Contributors are mentioned in the code where appropriate. *
6 * *
7 * Permission to use, copy, modify and distribute this software and its *
8 * documentation strictly for non-commercial purposes is hereby granted *
9 * without fee, provided that the above copyright notice appears in all *
10 * copies and that both the copyright notice and this permission notice *
11 * appear in the supporting documentation. The authors make no claims *
12 * about the suitability of this software for any purpose. It is *
13 * provided "as is" without express or implied warranty. *
14 **************************************************************************/
15
16////////////////////////////////////////////////////////////////////////////
17// //
18// TRAP config //
19// //
20// Author: J. Klein (Jochen.Klein@cern.ch) //
21// //
22////////////////////////////////////////////////////////////////////////////
23
ce4786b9 24#include "AliLog.h"
25
26#include "AliTRDgeometry.h"
27#include "AliTRDfeeParam.h"
28#include "AliTRDtrapConfig.h"
29
30#include <fstream>
31#include <iostream>
32#include <iomanip>
33
34ClassImp(AliTRDtrapConfig)
35
36AliTRDtrapConfig* AliTRDtrapConfig::fgInstance = 0x0;
37const Int_t AliTRDtrapConfig::fgkMaxMcm = AliTRDfeeParam::GetNmcmRob() + 2;
38const Int_t AliTRDtrapConfig::fgkDmemStartAddress = 0xc000;
39
40AliTRDtrapConfig::AliTRDtrapConfig() :
8ea391e3 41 TObject(), fScaleQ0(0), fScaleQ1(0)
ce4786b9 42{
43 // default constructor, initializing array of TRAP registers
44
45 // Name Address Nbits Reset Value
46 fRegs[kSML0] = SimpleReg_t("SML0", 0x0A00, 15, 0x4050 ); // Global state machine
47 fRegs[kSML1] = SimpleReg_t("SML1", 0x0A01, 15, 0x4200 );
48 fRegs[kSML2] = SimpleReg_t("SML2", 0x0A02, 15, 0x4384 );
49 fRegs[kSMMODE] = SimpleReg_t("SMMODE", 0x0A03, 16, 0xF0E2 );
50 fRegs[kNITM0] = SimpleReg_t("NITM0", 0x0A08, 14, 0x3FFF );
51 fRegs[kNITM1] = SimpleReg_t("NITM1", 0x0A09, 14, 0x3FFF );
52 fRegs[kNITM2] = SimpleReg_t("NITM2", 0x0A0A, 14, 0x3FFF );
53 fRegs[kNIP4D] = SimpleReg_t("NIP4D", 0x0A0B, 7, 0x7F );
54 fRegs[kCPU0CLK] = SimpleReg_t("CPU0CLK", 0x0A20, 5, 0x07 );
55 fRegs[kCPU1CLK] = SimpleReg_t("CPU1CLK", 0x0A22, 5, 0x07 );
56 fRegs[kCPU2CLK] = SimpleReg_t("CPU2CLK", 0x0A24, 5, 0x07 );
57 fRegs[kCPU3CLK] = SimpleReg_t("CPU3CLK", 0x0A26, 5, 0x07 );
58 fRegs[kNICLK] = SimpleReg_t("NICLK", 0x0A28, 5, 0x07 );
59 fRegs[kFILCLK] = SimpleReg_t("FILCLK", 0x0A2A, 5, 0x07 );
60 fRegs[kPRECLK] = SimpleReg_t("PRECLK", 0x0A2C, 5, 0x07 );
61 fRegs[kADCEN] = SimpleReg_t("ADCEN", 0x0A2E, 5, 0x07 );
62 fRegs[kNIODE] = SimpleReg_t("NIODE", 0x0A30, 5, 0x07 );
63 fRegs[kNIOCE] = SimpleReg_t("NIOCE", 0x0A32, 6, 0x21 ); // bit 5 is status bit (read-only)!
64 fRegs[kNIIDE] = SimpleReg_t("NIIDE", 0x0A34, 5, 0x07 );
65 fRegs[kNIICE] = SimpleReg_t("NIICE", 0x0A36, 5, 0x07 );
66 fRegs[kARBTIM] = SimpleReg_t("ARBTIM", 0x0A3F, 4, 0x0 ); // Arbiter
67 fRegs[kIA0IRQ0] = SimpleReg_t("IA0IRQ0", 0x0B00, 12, 0x000 ); // IVT of CPU0
68 fRegs[kIA0IRQ1] = SimpleReg_t("IA0IRQ1", 0x0B01, 12, 0x000 );
69 fRegs[kIA0IRQ2] = SimpleReg_t("IA0IRQ2", 0x0B02, 12, 0x000 );
70 fRegs[kIA0IRQ3] = SimpleReg_t("IA0IRQ3", 0x0B03, 12, 0x000 );
71 fRegs[kIA0IRQ4] = SimpleReg_t("IA0IRQ4", 0x0B04, 12, 0x000 );
72 fRegs[kIA0IRQ5] = SimpleReg_t("IA0IRQ5", 0x0B05, 12, 0x000 );
73 fRegs[kIA0IRQ6] = SimpleReg_t("IA0IRQ6", 0x0B06, 12, 0x000 );
74 fRegs[kIA0IRQ7] = SimpleReg_t("IA0IRQ7", 0x0B07, 12, 0x000 );
75 fRegs[kIA0IRQ8] = SimpleReg_t("IA0IRQ8", 0x0B08, 12, 0x000 );
76 fRegs[kIA0IRQ9] = SimpleReg_t("IA0IRQ9", 0x0B09, 12, 0x000 );
77 fRegs[kIA0IRQA] = SimpleReg_t("IA0IRQA", 0x0B0A, 12, 0x000 );
78 fRegs[kIA0IRQB] = SimpleReg_t("IA0IRQB", 0x0B0B, 12, 0x000 );
79 fRegs[kIA0IRQC] = SimpleReg_t("IA0IRQC", 0x0B0C, 12, 0x000 );
80 fRegs[kIRQSW0] = SimpleReg_t("IRQSW0", 0x0B0D, 13, 0x1FFF );
81 fRegs[kIRQHW0] = SimpleReg_t("IRQHW0", 0x0B0E, 13, 0x0000 );
82 fRegs[kIRQHL0] = SimpleReg_t("IRQHL0", 0x0B0F, 13, 0x0000 );
83 fRegs[kIA1IRQ0] = SimpleReg_t("IA1IRQ0", 0x0B20, 12, 0x000 ); // IVT of CPU1
84 fRegs[kIA1IRQ1] = SimpleReg_t("IA1IRQ1", 0x0B21, 12, 0x000 );
85 fRegs[kIA1IRQ2] = SimpleReg_t("IA1IRQ2", 0x0B22, 12, 0x000 );
86 fRegs[kIA1IRQ3] = SimpleReg_t("IA1IRQ3", 0x0B23, 12, 0x000 );
87 fRegs[kIA1IRQ4] = SimpleReg_t("IA1IRQ4", 0x0B24, 12, 0x000 );
88 fRegs[kIA1IRQ5] = SimpleReg_t("IA1IRQ5", 0x0B25, 12, 0x000 );
89 fRegs[kIA1IRQ6] = SimpleReg_t("IA1IRQ6", 0x0B26, 12, 0x000 );
90 fRegs[kIA1IRQ7] = SimpleReg_t("IA1IRQ7", 0x0B27, 12, 0x000 );
91 fRegs[kIA1IRQ8] = SimpleReg_t("IA1IRQ8", 0x0B28, 12, 0x000 );
92 fRegs[kIA1IRQ9] = SimpleReg_t("IA1IRQ9", 0x0B29, 12, 0x000 );
93 fRegs[kIA1IRQA] = SimpleReg_t("IA1IRQA", 0x0B2A, 12, 0x000 );
94 fRegs[kIA1IRQB] = SimpleReg_t("IA1IRQB", 0x0B2B, 12, 0x000 );
95 fRegs[kIA1IRQC] = SimpleReg_t("IA1IRQC", 0x0B2C, 12, 0x000 );
96 fRegs[kIRQSW1] = SimpleReg_t("IRQSW1", 0x0B2D, 13, 0x1FFF );
97 fRegs[kIRQHW1] = SimpleReg_t("IRQHW1", 0x0B2E, 13, 0x0000 );
98 fRegs[kIRQHL1] = SimpleReg_t("IRQHL1", 0x0B2F, 13, 0x0000 );
99 fRegs[kIA2IRQ0] = SimpleReg_t("IA2IRQ0", 0x0B40, 12, 0x000 ); // IVT of CPU2
100 fRegs[kIA2IRQ1] = SimpleReg_t("IA2IRQ1", 0x0B41, 12, 0x000 );
101 fRegs[kIA2IRQ2] = SimpleReg_t("IA2IRQ2", 0x0B42, 12, 0x000 );
102 fRegs[kIA2IRQ3] = SimpleReg_t("IA2IRQ3", 0x0B43, 12, 0x000 );
103 fRegs[kIA2IRQ4] = SimpleReg_t("IA2IRQ4", 0x0B44, 12, 0x000 );
104 fRegs[kIA2IRQ5] = SimpleReg_t("IA2IRQ5", 0x0B45, 12, 0x000 );
105 fRegs[kIA2IRQ6] = SimpleReg_t("IA2IRQ6", 0x0B46, 12, 0x000 );
106 fRegs[kIA2IRQ7] = SimpleReg_t("IA2IRQ7", 0x0B47, 12, 0x000 );
107 fRegs[kIA2IRQ8] = SimpleReg_t("IA2IRQ8", 0x0B48, 12, 0x000 );
108 fRegs[kIA2IRQ9] = SimpleReg_t("IA2IRQ9", 0x0B49, 12, 0x000 );
109 fRegs[kIA2IRQA] = SimpleReg_t("IA2IRQA", 0x0B4A, 12, 0x000 );
110 fRegs[kIA2IRQB] = SimpleReg_t("IA2IRQB", 0x0B4B, 12, 0x000 );
111 fRegs[kIA2IRQC] = SimpleReg_t("IA2IRQC", 0x0B4C, 12, 0x000 );
112 fRegs[kIRQSW2] = SimpleReg_t("IRQSW2", 0x0B4D, 13, 0x1FFF );
113 fRegs[kIRQHW2] = SimpleReg_t("IRQHW2", 0x0B4E, 13, 0x0000 );
114 fRegs[kIRQHL2] = SimpleReg_t("IRQHL2", 0x0B4F, 13, 0x0000 );
115 fRegs[kIA3IRQ0] = SimpleReg_t("IA3IRQ0", 0x0B60, 12, 0x000 ); // IVT of CPU3
116 fRegs[kIA3IRQ1] = SimpleReg_t("IA3IRQ1", 0x0B61, 12, 0x000 );
117 fRegs[kIA3IRQ2] = SimpleReg_t("IA3IRQ2", 0x0B62, 12, 0x000 );
118 fRegs[kIA3IRQ3] = SimpleReg_t("IA3IRQ3", 0x0B63, 12, 0x000 );
119 fRegs[kIA3IRQ4] = SimpleReg_t("IA3IRQ4", 0x0B64, 12, 0x000 );
120 fRegs[kIA3IRQ5] = SimpleReg_t("IA3IRQ5", 0x0B65, 12, 0x000 );
121 fRegs[kIA3IRQ6] = SimpleReg_t("IA3IRQ6", 0x0B66, 12, 0x000 );
122 fRegs[kIA3IRQ7] = SimpleReg_t("IA3IRQ7", 0x0B67, 12, 0x000 );
123 fRegs[kIA3IRQ8] = SimpleReg_t("IA3IRQ8", 0x0B68, 12, 0x000 );
124 fRegs[kIA3IRQ9] = SimpleReg_t("IA3IRQ9", 0x0B69, 12, 0x000 );
125 fRegs[kIA3IRQA] = SimpleReg_t("IA3IRQA", 0x0B6A, 12, 0x000 );
126 fRegs[kIA3IRQB] = SimpleReg_t("IA3IRQB", 0x0B6B, 12, 0x000 );
127 fRegs[kIA3IRQC] = SimpleReg_t("IA3IRQC", 0x0B6C, 12, 0x000 );
128 fRegs[kIRQSW3] = SimpleReg_t("IRQSW3", 0x0B6D, 13, 0x1FFF );
129 fRegs[kIRQHW3] = SimpleReg_t("IRQHW3", 0x0B6E, 13, 0x0000 );
130 fRegs[kIRQHL3] = SimpleReg_t("IRQHL3", 0x0B6F, 13, 0x0000 );
131 fRegs[kCTGDINI] = SimpleReg_t("CTGDINI", 0x0B80, 32, 0x00000000 ); // Global Counter/Timer
132 fRegs[kCTGCTRL] = SimpleReg_t("CTGCTRL", 0x0B81, 12, 0xE3F );
133 fRegs[kC08CPU0] = SimpleReg_t("C08CPU0", 0x0C00, 32, 0x00000000 ); // CPU constants
134 fRegs[kC09CPU0] = SimpleReg_t("C09CPU0", 0x0C01, 32, 0x00000000 );
135 fRegs[kC10CPU0] = SimpleReg_t("C10CPU0", 0x0C02, 32, 0x00000000 );
136 fRegs[kC11CPU0] = SimpleReg_t("C11CPU0", 0x0C03, 32, 0x00000000 );
137 fRegs[kC12CPUA] = SimpleReg_t("C12CPUA", 0x0C04, 32, 0x00000000 );
138 fRegs[kC13CPUA] = SimpleReg_t("C13CPUA", 0x0C05, 32, 0x00000000 );
139 fRegs[kC14CPUA] = SimpleReg_t("C14CPUA", 0x0C06, 32, 0x00000000 );
140 fRegs[kC15CPUA] = SimpleReg_t("C15CPUA", 0x0C07, 32, 0x00000000 );
141 fRegs[kC08CPU1] = SimpleReg_t("C08CPU1", 0x0C08, 32, 0x00000000 );
142 fRegs[kC09CPU1] = SimpleReg_t("C09CPU1", 0x0C09, 32, 0x00000000 );
143 fRegs[kC10CPU1] = SimpleReg_t("C10CPU1", 0x0C0A, 32, 0x00000000 );
144 fRegs[kC11CPU1] = SimpleReg_t("C11CPU1", 0x0C0B, 32, 0x00000000 );
145 fRegs[kC08CPU2] = SimpleReg_t("C08CPU2", 0x0C10, 32, 0x00000000 );
146 fRegs[kC09CPU2] = SimpleReg_t("C09CPU2", 0x0C11, 32, 0x00000000 );
147 fRegs[kC10CPU2] = SimpleReg_t("C10CPU2", 0x0C12, 32, 0x00000000 );
148 fRegs[kC11CPU2] = SimpleReg_t("C11CPU2", 0x0C13, 32, 0x00000000 );
149 fRegs[kC08CPU3] = SimpleReg_t("C08CPU3", 0x0C18, 32, 0x00000000 );
150 fRegs[kC09CPU3] = SimpleReg_t("C09CPU3", 0x0C19, 32, 0x00000000 );
151 fRegs[kC10CPU3] = SimpleReg_t("C10CPU3", 0x0C1A, 32, 0x00000000 );
152 fRegs[kC11CPU3] = SimpleReg_t("C11CPU3", 0x0C1B, 32, 0x00000000 );
153 fRegs[kNMOD] = SimpleReg_t("NMOD", 0x0D40, 6, 0x08 ); // NI interface
154 fRegs[kNDLY] = SimpleReg_t("NDLY", 0x0D41, 30, 0x24924924 );
155 fRegs[kNED] = SimpleReg_t("NED", 0x0D42, 16, 0xA240 );
156 fRegs[kNTRO] = SimpleReg_t("NTRO", 0x0D43, 18, 0x3FFFC );
157 fRegs[kNRRO] = SimpleReg_t("NRRO", 0x0D44, 18, 0x3FFFC );
158 fRegs[kNES] = SimpleReg_t("NES", 0x0D45, 32, 0x00000000 );
159 fRegs[kNTP] = SimpleReg_t("NTP", 0x0D46, 32, 0x0000FFFF );
160 fRegs[kNBND] = SimpleReg_t("NBND", 0x0D47, 16, 0x6020 );
161 fRegs[kNP0] = SimpleReg_t("NP0", 0x0D48, 11, 0x44C );
162 fRegs[kNP1] = SimpleReg_t("NP1", 0x0D49, 11, 0x44C );
163 fRegs[kNP2] = SimpleReg_t("NP2", 0x0D4A, 11, 0x44C );
164 fRegs[kNP3] = SimpleReg_t("NP3", 0x0D4B, 11, 0x44C );
165 fRegs[kNCUT] = SimpleReg_t("NCUT", 0x0D4C, 32, 0xFFFFFFFF );
166 fRegs[kTPPT0] = SimpleReg_t("TPPT0", 0x3000, 7, 0x01 ); // Filter and Preprocessor
167 fRegs[kTPFS] = SimpleReg_t("TPFS", 0x3001, 7, 0x05 );
168 fRegs[kTPFE] = SimpleReg_t("TPFE", 0x3002, 7, 0x14 );
169 fRegs[kTPPGR] = SimpleReg_t("TPPGR", 0x3003, 7, 0x15 );
170 fRegs[kTPPAE] = SimpleReg_t("TPPAE", 0x3004, 7, 0x1E );
171 fRegs[kTPQS0] = SimpleReg_t("TPQS0", 0x3005, 7, 0x00 );
172 fRegs[kTPQE0] = SimpleReg_t("TPQE0", 0x3006, 7, 0x0A );
173 fRegs[kTPQS1] = SimpleReg_t("TPQS1", 0x3007, 7, 0x0B );
174 fRegs[kTPQE1] = SimpleReg_t("TPQE1", 0x3008, 7, 0x14 );
175 fRegs[kEBD] = SimpleReg_t("EBD", 0x3009, 3, 0x0 );
176 fRegs[kEBAQA] = SimpleReg_t("EBAQA", 0x300A, 7, 0x00 );
177 fRegs[kEBSIA] = SimpleReg_t("EBSIA", 0x300B, 7, 0x20 );
178 fRegs[kEBSF] = SimpleReg_t("EBSF", 0x300C, 1, 0x1 );
179 fRegs[kEBSIM] = SimpleReg_t("EBSIM", 0x300D, 1, 0x1 );
180 fRegs[kEBPP] = SimpleReg_t("EBPP", 0x300E, 1, 0x1 );
181 fRegs[kEBPC] = SimpleReg_t("EBPC", 0x300F, 1, 0x1 );
182 fRegs[kEBIS] = SimpleReg_t("EBIS", 0x3014, 10, 0x005 );
183 fRegs[kEBIT] = SimpleReg_t("EBIT", 0x3015, 12, 0x028 );
184 fRegs[kEBIL] = SimpleReg_t("EBIL", 0x3016, 8, 0xF0 );
185 fRegs[kEBIN] = SimpleReg_t("EBIN", 0x3017, 1, 0x1 );
186 fRegs[kFLBY] = SimpleReg_t("FLBY", 0x3018, 1, 0x0 );
187 fRegs[kFPBY] = SimpleReg_t("FPBY", 0x3019, 1, 0x0 );
188 fRegs[kFGBY] = SimpleReg_t("FGBY", 0x301A, 1, 0x0 );
189 fRegs[kFTBY] = SimpleReg_t("FTBY", 0x301B, 1, 0x0 );
190 fRegs[kFCBY] = SimpleReg_t("FCBY", 0x301C, 1, 0x0 );
191 fRegs[kFPTC] = SimpleReg_t("FPTC", 0x3020, 2, 0x3 );
192 fRegs[kFPNP] = SimpleReg_t("FPNP", 0x3021, 9, 0x078 );
193 fRegs[kFPCL] = SimpleReg_t("FPCL", 0x3022, 1, 0x1 );
194 fRegs[kFGTA] = SimpleReg_t("FGTA", 0x3028, 12, 0x014 );
195 fRegs[kFGTB] = SimpleReg_t("FGTB", 0x3029, 12, 0x80C );
196 fRegs[kFGCL] = SimpleReg_t("FGCL", 0x302A, 1, 0x1 );
197 fRegs[kFTAL] = SimpleReg_t("FTAL", 0x3030, 10, 0x0F6 );
198 fRegs[kFTLL] = SimpleReg_t("FTLL", 0x3031, 9, 0x11D );
199 fRegs[kFTLS] = SimpleReg_t("FTLS", 0x3032, 9, 0x0D3 );
200 fRegs[kFCW1] = SimpleReg_t("FCW1", 0x3038, 8, 0x1E );
201 fRegs[kFCW2] = SimpleReg_t("FCW2", 0x3039, 8, 0xD4 );
202 fRegs[kFCW3] = SimpleReg_t("FCW3", 0x303A, 8, 0xE6 );
203 fRegs[kFCW4] = SimpleReg_t("FCW4", 0x303B, 8, 0x4A );
204 fRegs[kFCW5] = SimpleReg_t("FCW5", 0x303C, 8, 0xEF );
205 fRegs[kTPFP] = SimpleReg_t("TPFP", 0x3040, 9, 0x037 );
206 fRegs[kTPHT] = SimpleReg_t("TPHT", 0x3041, 14, 0x00A0 );
207 fRegs[kTPVT] = SimpleReg_t("TPVT", 0x3042, 6, 0x00 );
208 fRegs[kTPVBY] = SimpleReg_t("TPVBY", 0x3043, 1, 0x0 );
209 fRegs[kTPCT] = SimpleReg_t("TPCT", 0x3044, 5, 0x08 );
210 fRegs[kTPCL] = SimpleReg_t("TPCL", 0x3045, 5, 0x01 );
211 fRegs[kTPCBY] = SimpleReg_t("TPCBY", 0x3046, 1, 0x1 );
212 fRegs[kTPD] = SimpleReg_t("TPD", 0x3047, 4, 0xF );
213 fRegs[kTPCI0] = SimpleReg_t("TPCI0", 0x3048, 5, 0x00 );
214 fRegs[kTPCI1] = SimpleReg_t("TPCI1", 0x3049, 5, 0x00 );
215 fRegs[kTPCI2] = SimpleReg_t("TPCI2", 0x304A, 5, 0x00 );
216 fRegs[kTPCI3] = SimpleReg_t("TPCI3", 0x304B, 5, 0x00 );
217 fRegs[kADCMSK] = SimpleReg_t("ADCMSK", 0x3050, 21, 0x1FFFFF );
218 fRegs[kADCINB] = SimpleReg_t("ADCINB", 0x3051, 2, 0x2 );
219 fRegs[kADCDAC] = SimpleReg_t("ADCDAC", 0x3052, 5, 0x10 );
220 fRegs[kADCPAR] = SimpleReg_t("ADCPAR", 0x3053, 18, 0x195EF );
221 fRegs[kADCTST] = SimpleReg_t("ADCTST", 0x3054, 2, 0x0 );
222 fRegs[kSADCAZ] = SimpleReg_t("SADCAZ", 0x3055, 1, 0x1 );
223 fRegs[kFGF0] = SimpleReg_t("FGF0", 0x3080, 9, 0x000 );
224 fRegs[kFGF1] = SimpleReg_t("FGF1", 0x3081, 9, 0x000 );
225 fRegs[kFGF2] = SimpleReg_t("FGF2", 0x3082, 9, 0x000 );
226 fRegs[kFGF3] = SimpleReg_t("FGF3", 0x3083, 9, 0x000 );
227 fRegs[kFGF4] = SimpleReg_t("FGF4", 0x3084, 9, 0x000 );
228 fRegs[kFGF5] = SimpleReg_t("FGF5", 0x3085, 9, 0x000 );
229 fRegs[kFGF6] = SimpleReg_t("FGF6", 0x3086, 9, 0x000 );
230 fRegs[kFGF7] = SimpleReg_t("FGF7", 0x3087, 9, 0x000 );
231 fRegs[kFGF8] = SimpleReg_t("FGF8", 0x3088, 9, 0x000 );
232 fRegs[kFGF9] = SimpleReg_t("FGF9", 0x3089, 9, 0x000 );
233 fRegs[kFGF10] = SimpleReg_t("FGF10", 0x308A, 9, 0x000 );
234 fRegs[kFGF11] = SimpleReg_t("FGF11", 0x308B, 9, 0x000 );
235 fRegs[kFGF12] = SimpleReg_t("FGF12", 0x308C, 9, 0x000 );
236 fRegs[kFGF13] = SimpleReg_t("FGF13", 0x308D, 9, 0x000 );
237 fRegs[kFGF14] = SimpleReg_t("FGF14", 0x308E, 9, 0x000 );
238 fRegs[kFGF15] = SimpleReg_t("FGF15", 0x308F, 9, 0x000 );
239 fRegs[kFGF16] = SimpleReg_t("FGF16", 0x3090, 9, 0x000 );
240 fRegs[kFGF17] = SimpleReg_t("FGF17", 0x3091, 9, 0x000 );
241 fRegs[kFGF18] = SimpleReg_t("FGF18", 0x3092, 9, 0x000 );
242 fRegs[kFGF19] = SimpleReg_t("FGF19", 0x3093, 9, 0x000 );
243 fRegs[kFGF20] = SimpleReg_t("FGF20", 0x3094, 9, 0x000 );
244 fRegs[kFGA0] = SimpleReg_t("FGA0", 0x30A0, 6, 0x00 );
245 fRegs[kFGA1] = SimpleReg_t("FGA1", 0x30A1, 6, 0x00 );
246 fRegs[kFGA2] = SimpleReg_t("FGA2", 0x30A2, 6, 0x00 );
247 fRegs[kFGA3] = SimpleReg_t("FGA3", 0x30A3, 6, 0x00 );
248 fRegs[kFGA4] = SimpleReg_t("FGA4", 0x30A4, 6, 0x00 );
249 fRegs[kFGA5] = SimpleReg_t("FGA5", 0x30A5, 6, 0x00 );
250 fRegs[kFGA6] = SimpleReg_t("FGA6", 0x30A6, 6, 0x00 );
251 fRegs[kFGA7] = SimpleReg_t("FGA7", 0x30A7, 6, 0x00 );
252 fRegs[kFGA8] = SimpleReg_t("FGA8", 0x30A8, 6, 0x00 );
253 fRegs[kFGA9] = SimpleReg_t("FGA9", 0x30A9, 6, 0x00 );
254 fRegs[kFGA10] = SimpleReg_t("FGA10", 0x30AA, 6, 0x00 );
255 fRegs[kFGA11] = SimpleReg_t("FGA11", 0x30AB, 6, 0x00 );
256 fRegs[kFGA12] = SimpleReg_t("FGA12", 0x30AC, 6, 0x00 );
257 fRegs[kFGA13] = SimpleReg_t("FGA13", 0x30AD, 6, 0x00 );
258 fRegs[kFGA14] = SimpleReg_t("FGA14", 0x30AE, 6, 0x00 );
259 fRegs[kFGA15] = SimpleReg_t("FGA15", 0x30AF, 6, 0x00 );
260 fRegs[kFGA16] = SimpleReg_t("FGA16", 0x30B0, 6, 0x00 );
261 fRegs[kFGA17] = SimpleReg_t("FGA17", 0x30B1, 6, 0x00 );
262 fRegs[kFGA18] = SimpleReg_t("FGA18", 0x30B2, 6, 0x00 );
263 fRegs[kFGA19] = SimpleReg_t("FGA19", 0x30B3, 6, 0x00 );
264 fRegs[kFGA20] = SimpleReg_t("FGA20", 0x30B4, 6, 0x00 );
265 fRegs[kFLL00] = SimpleReg_t("FLL00", 0x3100, 6, 0x00 ); // non-linearity table, 64 x 6 bits
266 fRegs[kFLL01] = SimpleReg_t("FLL01", 0x3101, 6, 0x00 );
267 fRegs[kFLL02] = SimpleReg_t("FLL02", 0x3102, 6, 0x00 );
268 fRegs[kFLL03] = SimpleReg_t("FLL03", 0x3103, 6, 0x00 );
269 fRegs[kFLL04] = SimpleReg_t("FLL04", 0x3104, 6, 0x00 );
270 fRegs[kFLL05] = SimpleReg_t("FLL05", 0x3105, 6, 0x00 );
271 fRegs[kFLL06] = SimpleReg_t("FLL06", 0x3106, 6, 0x00 );
272 fRegs[kFLL07] = SimpleReg_t("FLL07", 0x3107, 6, 0x00 );
273 fRegs[kFLL08] = SimpleReg_t("FLL08", 0x3108, 6, 0x00 );
274 fRegs[kFLL09] = SimpleReg_t("FLL09", 0x3109, 6, 0x00 );
275 fRegs[kFLL0A] = SimpleReg_t("FLL0A", 0x310A, 6, 0x00 );
276 fRegs[kFLL0B] = SimpleReg_t("FLL0B", 0x310B, 6, 0x00 );
277 fRegs[kFLL0C] = SimpleReg_t("FLL0C", 0x310C, 6, 0x00 );
278 fRegs[kFLL0D] = SimpleReg_t("FLL0D", 0x310D, 6, 0x00 );
279 fRegs[kFLL0E] = SimpleReg_t("FLL0E", 0x310E, 6, 0x00 );
280 fRegs[kFLL0F] = SimpleReg_t("FLL0F", 0x310F, 6, 0x00 );
281 fRegs[kFLL10] = SimpleReg_t("FLL10", 0x3110, 6, 0x00 );
282 fRegs[kFLL11] = SimpleReg_t("FLL11", 0x3111, 6, 0x00 );
283 fRegs[kFLL12] = SimpleReg_t("FLL12", 0x3112, 6, 0x00 );
284 fRegs[kFLL13] = SimpleReg_t("FLL13", 0x3113, 6, 0x00 );
285 fRegs[kFLL14] = SimpleReg_t("FLL14", 0x3114, 6, 0x00 );
286 fRegs[kFLL15] = SimpleReg_t("FLL15", 0x3115, 6, 0x00 );
287 fRegs[kFLL16] = SimpleReg_t("FLL16", 0x3116, 6, 0x00 );
288 fRegs[kFLL17] = SimpleReg_t("FLL17", 0x3117, 6, 0x00 );
289 fRegs[kFLL18] = SimpleReg_t("FLL18", 0x3118, 6, 0x00 );
290 fRegs[kFLL19] = SimpleReg_t("FLL19", 0x3119, 6, 0x00 );
291 fRegs[kFLL1A] = SimpleReg_t("FLL1A", 0x311A, 6, 0x00 );
292 fRegs[kFLL1B] = SimpleReg_t("FLL1B", 0x311B, 6, 0x00 );
293 fRegs[kFLL1C] = SimpleReg_t("FLL1C", 0x311C, 6, 0x00 );
294 fRegs[kFLL1D] = SimpleReg_t("FLL1D", 0x311D, 6, 0x00 );
295 fRegs[kFLL1E] = SimpleReg_t("FLL1E", 0x311E, 6, 0x00 );
296 fRegs[kFLL1F] = SimpleReg_t("FLL1F", 0x311F, 6, 0x00 );
297 fRegs[kFLL20] = SimpleReg_t("FLL20", 0x3120, 6, 0x00 );
298 fRegs[kFLL21] = SimpleReg_t("FLL21", 0x3121, 6, 0x00 );
299 fRegs[kFLL22] = SimpleReg_t("FLL22", 0x3122, 6, 0x00 );
300 fRegs[kFLL23] = SimpleReg_t("FLL23", 0x3123, 6, 0x00 );
301 fRegs[kFLL24] = SimpleReg_t("FLL24", 0x3124, 6, 0x00 );
302 fRegs[kFLL25] = SimpleReg_t("FLL25", 0x3125, 6, 0x00 );
303 fRegs[kFLL26] = SimpleReg_t("FLL26", 0x3126, 6, 0x00 );
304 fRegs[kFLL27] = SimpleReg_t("FLL27", 0x3127, 6, 0x00 );
305 fRegs[kFLL28] = SimpleReg_t("FLL28", 0x3128, 6, 0x00 );
306 fRegs[kFLL29] = SimpleReg_t("FLL29", 0x3129, 6, 0x00 );
307 fRegs[kFLL2A] = SimpleReg_t("FLL2A", 0x312A, 6, 0x00 );
308 fRegs[kFLL2B] = SimpleReg_t("FLL2B", 0x312B, 6, 0x00 );
309 fRegs[kFLL2C] = SimpleReg_t("FLL2C", 0x312C, 6, 0x00 );
310 fRegs[kFLL2D] = SimpleReg_t("FLL2D", 0x312D, 6, 0x00 );
311 fRegs[kFLL2E] = SimpleReg_t("FLL2E", 0x312E, 6, 0x00 );
312 fRegs[kFLL2F] = SimpleReg_t("FLL2F", 0x312F, 6, 0x00 );
313 fRegs[kFLL30] = SimpleReg_t("FLL30", 0x3130, 6, 0x00 );
314 fRegs[kFLL31] = SimpleReg_t("FLL31", 0x3131, 6, 0x00 );
315 fRegs[kFLL32] = SimpleReg_t("FLL32", 0x3132, 6, 0x00 );
316 fRegs[kFLL33] = SimpleReg_t("FLL33", 0x3133, 6, 0x00 );
317 fRegs[kFLL34] = SimpleReg_t("FLL34", 0x3134, 6, 0x00 );
318 fRegs[kFLL35] = SimpleReg_t("FLL35", 0x3135, 6, 0x00 );
319 fRegs[kFLL36] = SimpleReg_t("FLL36", 0x3136, 6, 0x00 );
320 fRegs[kFLL37] = SimpleReg_t("FLL37", 0x3137, 6, 0x00 );
321 fRegs[kFLL38] = SimpleReg_t("FLL38", 0x3138, 6, 0x00 );
322 fRegs[kFLL39] = SimpleReg_t("FLL39", 0x3139, 6, 0x00 );
323 fRegs[kFLL3A] = SimpleReg_t("FLL3A", 0x313A, 6, 0x00 );
324 fRegs[kFLL3B] = SimpleReg_t("FLL3B", 0x313B, 6, 0x00 );
325 fRegs[kFLL3C] = SimpleReg_t("FLL3C", 0x313C, 6, 0x00 );
326 fRegs[kFLL3D] = SimpleReg_t("FLL3D", 0x313D, 6, 0x00 );
327 fRegs[kFLL3E] = SimpleReg_t("FLL3E", 0x313E, 6, 0x00 );
328 fRegs[kFLL3F] = SimpleReg_t("FLL3F", 0x313F, 6, 0x00 );
329 fRegs[kPASADEL] = SimpleReg_t("PASADEL", 0x3158, 8, 0xFF ); // end of non-lin table
330 fRegs[kPASAPHA] = SimpleReg_t("PASAPHA", 0x3159, 6, 0x3F );
331 fRegs[kPASAPRA] = SimpleReg_t("PASAPRA", 0x315A, 6, 0x0F );
332 fRegs[kPASADAC] = SimpleReg_t("PASADAC", 0x315B, 8, 0x80 );
333 fRegs[kPASACHM] = SimpleReg_t("PASACHM", 0x315C, 19, 0x7FFFF );
334 fRegs[kPASASTL] = SimpleReg_t("PASASTL", 0x315D, 8, 0xFF );
335 fRegs[kPASAPR1] = SimpleReg_t("PASAPR1", 0x315E, 1, 0x0 );
336 fRegs[kPASAPR0] = SimpleReg_t("PASAPR0", 0x315F, 1, 0x0 );
337 fRegs[kSADCTRG] = SimpleReg_t("SADCTRG", 0x3161, 1, 0x0 );
338 fRegs[kSADCRUN] = SimpleReg_t("SADCRUN", 0x3162, 1, 0x0 );
339 fRegs[kSADCPWR] = SimpleReg_t("SADCPWR", 0x3163, 3, 0x7 );
340 fRegs[kL0TSIM] = SimpleReg_t("L0TSIM", 0x3165, 14, 0x0050 );
341 fRegs[kSADCEC] = SimpleReg_t("SADCEC", 0x3166, 7, 0x00 );
342 fRegs[kSADCMC] = SimpleReg_t("SADCMC", 0x3170, 8, 0xC0 );
343 fRegs[kSADCOC] = SimpleReg_t("SADCOC", 0x3171, 8, 0x19 );
344 fRegs[kSADCGTB] = SimpleReg_t("SADCGTB", 0x3172, 32, 0x37737700 );
345 fRegs[kSEBDEN] = SimpleReg_t("SEBDEN", 0x3178, 3, 0x0 );
346 fRegs[kSEBDOU] = SimpleReg_t("SEBDOU", 0x3179, 3, 0x0 );
347 fRegs[kTPL00] = SimpleReg_t("TPL00", 0x3180, 5, 0x00 ); // pos table, 128 x 5 bits
348 fRegs[kTPL01] = SimpleReg_t("TPL01", 0x3181, 5, 0x00 );
349 fRegs[kTPL02] = SimpleReg_t("TPL02", 0x3182, 5, 0x00 );
350 fRegs[kTPL03] = SimpleReg_t("TPL03", 0x3183, 5, 0x00 );
351 fRegs[kTPL04] = SimpleReg_t("TPL04", 0x3184, 5, 0x00 );
352 fRegs[kTPL05] = SimpleReg_t("TPL05", 0x3185, 5, 0x00 );
353 fRegs[kTPL06] = SimpleReg_t("TPL06", 0x3186, 5, 0x00 );
354 fRegs[kTPL07] = SimpleReg_t("TPL07", 0x3187, 5, 0x00 );
355 fRegs[kTPL08] = SimpleReg_t("TPL08", 0x3188, 5, 0x00 );
356 fRegs[kTPL09] = SimpleReg_t("TPL09", 0x3189, 5, 0x00 );
357 fRegs[kTPL0A] = SimpleReg_t("TPL0A", 0x318A, 5, 0x00 );
358 fRegs[kTPL0B] = SimpleReg_t("TPL0B", 0x318B, 5, 0x00 );
359 fRegs[kTPL0C] = SimpleReg_t("TPL0C", 0x318C, 5, 0x00 );
360 fRegs[kTPL0D] = SimpleReg_t("TPL0D", 0x318D, 5, 0x00 );
361 fRegs[kTPL0E] = SimpleReg_t("TPL0E", 0x318E, 5, 0x00 );
362 fRegs[kTPL0F] = SimpleReg_t("TPL0F", 0x318F, 5, 0x00 );
363 fRegs[kTPL10] = SimpleReg_t("TPL10", 0x3190, 5, 0x00 );
364 fRegs[kTPL11] = SimpleReg_t("TPL11", 0x3191, 5, 0x00 );
365 fRegs[kTPL12] = SimpleReg_t("TPL12", 0x3192, 5, 0x00 );
366 fRegs[kTPL13] = SimpleReg_t("TPL13", 0x3193, 5, 0x00 );
367 fRegs[kTPL14] = SimpleReg_t("TPL14", 0x3194, 5, 0x00 );
368 fRegs[kTPL15] = SimpleReg_t("TPL15", 0x3195, 5, 0x00 );
369 fRegs[kTPL16] = SimpleReg_t("TPL16", 0x3196, 5, 0x00 );
370 fRegs[kTPL17] = SimpleReg_t("TPL17", 0x3197, 5, 0x00 );
371 fRegs[kTPL18] = SimpleReg_t("TPL18", 0x3198, 5, 0x00 );
372 fRegs[kTPL19] = SimpleReg_t("TPL19", 0x3199, 5, 0x00 );
373 fRegs[kTPL1A] = SimpleReg_t("TPL1A", 0x319A, 5, 0x00 );
374 fRegs[kTPL1B] = SimpleReg_t("TPL1B", 0x319B, 5, 0x00 );
375 fRegs[kTPL1C] = SimpleReg_t("TPL1C", 0x319C, 5, 0x00 );
376 fRegs[kTPL1D] = SimpleReg_t("TPL1D", 0x319D, 5, 0x00 );
377 fRegs[kTPL1E] = SimpleReg_t("TPL1E", 0x319E, 5, 0x00 );
378 fRegs[kTPL1F] = SimpleReg_t("TPL1F", 0x319F, 5, 0x00 );
379 fRegs[kTPL20] = SimpleReg_t("TPL20", 0x31A0, 5, 0x00 );
380 fRegs[kTPL21] = SimpleReg_t("TPL21", 0x31A1, 5, 0x00 );
381 fRegs[kTPL22] = SimpleReg_t("TPL22", 0x31A2, 5, 0x00 );
382 fRegs[kTPL23] = SimpleReg_t("TPL23", 0x31A3, 5, 0x00 );
383 fRegs[kTPL24] = SimpleReg_t("TPL24", 0x31A4, 5, 0x00 );
384 fRegs[kTPL25] = SimpleReg_t("TPL25", 0x31A5, 5, 0x00 );
385 fRegs[kTPL26] = SimpleReg_t("TPL26", 0x31A6, 5, 0x00 );
386 fRegs[kTPL27] = SimpleReg_t("TPL27", 0x31A7, 5, 0x00 );
387 fRegs[kTPL28] = SimpleReg_t("TPL28", 0x31A8, 5, 0x00 );
388 fRegs[kTPL29] = SimpleReg_t("TPL29", 0x31A9, 5, 0x00 );
389 fRegs[kTPL2A] = SimpleReg_t("TPL2A", 0x31AA, 5, 0x00 );
390 fRegs[kTPL2B] = SimpleReg_t("TPL2B", 0x31AB, 5, 0x00 );
391 fRegs[kTPL2C] = SimpleReg_t("TPL2C", 0x31AC, 5, 0x00 );
392 fRegs[kTPL2D] = SimpleReg_t("TPL2D", 0x31AD, 5, 0x00 );
393 fRegs[kTPL2E] = SimpleReg_t("TPL2E", 0x31AE, 5, 0x00 );
394 fRegs[kTPL2F] = SimpleReg_t("TPL2F", 0x31AF, 5, 0x00 );
395 fRegs[kTPL30] = SimpleReg_t("TPL30", 0x31B0, 5, 0x00 );
396 fRegs[kTPL31] = SimpleReg_t("TPL31", 0x31B1, 5, 0x00 );
397 fRegs[kTPL32] = SimpleReg_t("TPL32", 0x31B2, 5, 0x00 );
398 fRegs[kTPL33] = SimpleReg_t("TPL33", 0x31B3, 5, 0x00 );
399 fRegs[kTPL34] = SimpleReg_t("TPL34", 0x31B4, 5, 0x00 );
400 fRegs[kTPL35] = SimpleReg_t("TPL35", 0x31B5, 5, 0x00 );
401 fRegs[kTPL36] = SimpleReg_t("TPL36", 0x31B6, 5, 0x00 );
402 fRegs[kTPL37] = SimpleReg_t("TPL37", 0x31B7, 5, 0x00 );
403 fRegs[kTPL38] = SimpleReg_t("TPL38", 0x31B8, 5, 0x00 );
404 fRegs[kTPL39] = SimpleReg_t("TPL39", 0x31B9, 5, 0x00 );
405 fRegs[kTPL3A] = SimpleReg_t("TPL3A", 0x31BA, 5, 0x00 );
406 fRegs[kTPL3B] = SimpleReg_t("TPL3B", 0x31BB, 5, 0x00 );
407 fRegs[kTPL3C] = SimpleReg_t("TPL3C", 0x31BC, 5, 0x00 );
408 fRegs[kTPL3D] = SimpleReg_t("TPL3D", 0x31BD, 5, 0x00 );
409 fRegs[kTPL3E] = SimpleReg_t("TPL3E", 0x31BE, 5, 0x00 );
410 fRegs[kTPL3F] = SimpleReg_t("TPL3F", 0x31BF, 5, 0x00 );
411 fRegs[kTPL40] = SimpleReg_t("TPL40", 0x31C0, 5, 0x00 );
412 fRegs[kTPL41] = SimpleReg_t("TPL41", 0x31C1, 5, 0x00 );
413 fRegs[kTPL42] = SimpleReg_t("TPL42", 0x31C2, 5, 0x00 );
414 fRegs[kTPL43] = SimpleReg_t("TPL43", 0x31C3, 5, 0x00 );
415 fRegs[kTPL44] = SimpleReg_t("TPL44", 0x31C4, 5, 0x00 );
416 fRegs[kTPL45] = SimpleReg_t("TPL45", 0x31C5, 5, 0x00 );
417 fRegs[kTPL46] = SimpleReg_t("TPL46", 0x31C6, 5, 0x00 );
418 fRegs[kTPL47] = SimpleReg_t("TPL47", 0x31C7, 5, 0x00 );
419 fRegs[kTPL48] = SimpleReg_t("TPL48", 0x31C8, 5, 0x00 );
420 fRegs[kTPL49] = SimpleReg_t("TPL49", 0x31C9, 5, 0x00 );
421 fRegs[kTPL4A] = SimpleReg_t("TPL4A", 0x31CA, 5, 0x00 );
422 fRegs[kTPL4B] = SimpleReg_t("TPL4B", 0x31CB, 5, 0x00 );
423 fRegs[kTPL4C] = SimpleReg_t("TPL4C", 0x31CC, 5, 0x00 );
424 fRegs[kTPL4D] = SimpleReg_t("TPL4D", 0x31CD, 5, 0x00 );
425 fRegs[kTPL4E] = SimpleReg_t("TPL4E", 0x31CE, 5, 0x00 );
426 fRegs[kTPL4F] = SimpleReg_t("TPL4F", 0x31CF, 5, 0x00 );
427 fRegs[kTPL50] = SimpleReg_t("TPL50", 0x31D0, 5, 0x00 );
428 fRegs[kTPL51] = SimpleReg_t("TPL51", 0x31D1, 5, 0x00 );
429 fRegs[kTPL52] = SimpleReg_t("TPL52", 0x31D2, 5, 0x00 );
430 fRegs[kTPL53] = SimpleReg_t("TPL53", 0x31D3, 5, 0x00 );
431 fRegs[kTPL54] = SimpleReg_t("TPL54", 0x31D4, 5, 0x00 );
432 fRegs[kTPL55] = SimpleReg_t("TPL55", 0x31D5, 5, 0x00 );
433 fRegs[kTPL56] = SimpleReg_t("TPL56", 0x31D6, 5, 0x00 );
434 fRegs[kTPL57] = SimpleReg_t("TPL57", 0x31D7, 5, 0x00 );
435 fRegs[kTPL58] = SimpleReg_t("TPL58", 0x31D8, 5, 0x00 );
436 fRegs[kTPL59] = SimpleReg_t("TPL59", 0x31D9, 5, 0x00 );
437 fRegs[kTPL5A] = SimpleReg_t("TPL5A", 0x31DA, 5, 0x00 );
438 fRegs[kTPL5B] = SimpleReg_t("TPL5B", 0x31DB, 5, 0x00 );
439 fRegs[kTPL5C] = SimpleReg_t("TPL5C", 0x31DC, 5, 0x00 );
440 fRegs[kTPL5D] = SimpleReg_t("TPL5D", 0x31DD, 5, 0x00 );
441 fRegs[kTPL5E] = SimpleReg_t("TPL5E", 0x31DE, 5, 0x00 );
442 fRegs[kTPL5F] = SimpleReg_t("TPL5F", 0x31DF, 5, 0x00 );
443 fRegs[kTPL60] = SimpleReg_t("TPL60", 0x31E0, 5, 0x00 );
444 fRegs[kTPL61] = SimpleReg_t("TPL61", 0x31E1, 5, 0x00 );
445 fRegs[kTPL62] = SimpleReg_t("TPL62", 0x31E2, 5, 0x00 );
446 fRegs[kTPL63] = SimpleReg_t("TPL63", 0x31E3, 5, 0x00 );
447 fRegs[kTPL64] = SimpleReg_t("TPL64", 0x31E4, 5, 0x00 );
448 fRegs[kTPL65] = SimpleReg_t("TPL65", 0x31E5, 5, 0x00 );
449 fRegs[kTPL66] = SimpleReg_t("TPL66", 0x31E6, 5, 0x00 );
450 fRegs[kTPL67] = SimpleReg_t("TPL67", 0x31E7, 5, 0x00 );
451 fRegs[kTPL68] = SimpleReg_t("TPL68", 0x31E8, 5, 0x00 );
452 fRegs[kTPL69] = SimpleReg_t("TPL69", 0x31E9, 5, 0x00 );
453 fRegs[kTPL6A] = SimpleReg_t("TPL6A", 0x31EA, 5, 0x00 );
454 fRegs[kTPL6B] = SimpleReg_t("TPL6B", 0x31EB, 5, 0x00 );
455 fRegs[kTPL6C] = SimpleReg_t("TPL6C", 0x31EC, 5, 0x00 );
456 fRegs[kTPL6D] = SimpleReg_t("TPL6D", 0x31ED, 5, 0x00 );
457 fRegs[kTPL6E] = SimpleReg_t("TPL6E", 0x31EE, 5, 0x00 );
458 fRegs[kTPL6F] = SimpleReg_t("TPL6F", 0x31EF, 5, 0x00 );
459 fRegs[kTPL70] = SimpleReg_t("TPL70", 0x31F0, 5, 0x00 );
460 fRegs[kTPL71] = SimpleReg_t("TPL71", 0x31F1, 5, 0x00 );
461 fRegs[kTPL72] = SimpleReg_t("TPL72", 0x31F2, 5, 0x00 );
462 fRegs[kTPL73] = SimpleReg_t("TPL73", 0x31F3, 5, 0x00 );
463 fRegs[kTPL74] = SimpleReg_t("TPL74", 0x31F4, 5, 0x00 );
464 fRegs[kTPL75] = SimpleReg_t("TPL75", 0x31F5, 5, 0x00 );
465 fRegs[kTPL76] = SimpleReg_t("TPL76", 0x31F6, 5, 0x00 );
466 fRegs[kTPL77] = SimpleReg_t("TPL77", 0x31F7, 5, 0x00 );
467 fRegs[kTPL78] = SimpleReg_t("TPL78", 0x31F8, 5, 0x00 );
468 fRegs[kTPL79] = SimpleReg_t("TPL79", 0x31F9, 5, 0x00 );
469 fRegs[kTPL7A] = SimpleReg_t("TPL7A", 0x31FA, 5, 0x00 );
470 fRegs[kTPL7B] = SimpleReg_t("TPL7B", 0x31FB, 5, 0x00 );
471 fRegs[kTPL7C] = SimpleReg_t("TPL7C", 0x31FC, 5, 0x00 );
472 fRegs[kTPL7D] = SimpleReg_t("TPL7D", 0x31FD, 5, 0x00 );
473 fRegs[kTPL7E] = SimpleReg_t("TPL7E", 0x31FE, 5, 0x00 );
474 fRegs[kTPL7F] = SimpleReg_t("TPL7F", 0x31FF, 5, 0x00 );
475 fRegs[kMEMRW] = SimpleReg_t("MEMRW", 0xD000, 7, 0x79 ); // end of pos table
476 fRegs[kMEMCOR] = SimpleReg_t("MEMCOR", 0xD001, 9, 0x000 );
477 fRegs[kDMDELA] = SimpleReg_t("DMDELA", 0xD002, 4, 0x8 );
478 fRegs[kDMDELS] = SimpleReg_t("DMDELS", 0xD003, 4, 0x8 );
479
8ea391e3 480
481
482 for(Int_t iAddr = 0; iAddr < fgkDmemWords; iAddr++) {
483
484 if(iAddr == fgkDmemAddrDeflCorr - fgkDmemStartAddress) {
485 fDmem[iAddr] = new UInt_t[fgkDmemSizeSmIndividual];
486 fDmemDepth[iAddr] = fgkDmemSizeSmIndividual;
487 }
488
489 else if(iAddr == fgkDmemAddrNdrift - fgkDmemStartAddress) {
490 fDmem[iAddr] = new UInt_t[fgkDmemSizeSmRocIndividual];
491 fDmemDepth[iAddr] = fgkDmemSizeSmRocIndividual;
492 }
493
494 else if(iAddr >= fgkDmemAddrDeflCutStart-fgkDmemStartAddress && iAddr <= fgkDmemAddrDeflCutEnd-fgkDmemStartAddress) {
495 fDmem[iAddr] = new UInt_t[fgkDmemSizeSmIndividual];
496 fDmemDepth[iAddr] = fgkDmemSizeSmIndividual;
497 }
498
499 else if(iAddr >= fgkDmemAddrTrackletStart-fgkDmemStartAddress && iAddr <= fgkDmemAddrTrackletEnd-fgkDmemStartAddress) {
500 fDmem[iAddr] = new UInt_t[fgkDmemSizeTotalIndividual];
501 fDmemDepth[iAddr] = fgkDmemSizeTotalIndividual;
502 }
503
504 else if(iAddr >= fgkDmemAddrLUTStart-fgkDmemStartAddress && iAddr <= fgkDmemAddrLUTEnd-fgkDmemStartAddress) {
505 fDmem[iAddr] = new UInt_t; // same value for all MCMs
506 fDmemDepth[iAddr] = fgkDmemSizeUniform;
507 }
508
509 else if(iAddr == fgkDmemAddrLUTcor0-fgkDmemStartAddress) {
510 fDmem[iAddr] = new UInt_t[fgkDmemSizeSmIndividual];
511 fDmemDepth[iAddr] = fgkDmemSizeSmIndividual;
512 }
513
514 else if(iAddr == fgkDmemAddrLUTcor1-fgkDmemStartAddress) {
515 fDmem[iAddr] = new UInt_t[fgkDmemSizeSmIndividual];
516 fDmemDepth[iAddr] = fgkDmemSizeSmIndividual;
517 }
518
519 else if(iAddr == fgkDmemAddrLUTnbins-fgkDmemStartAddress) {
520 fDmem[iAddr] = new UInt_t; // same value for all MCMs
521 fDmemDepth[iAddr] = fgkDmemSizeUniform;
522 }
523
524 else if(iAddr == fgkDmemAddrLUTLength-fgkDmemStartAddress) {
525 fDmem[iAddr] = new UInt_t; // same value for all MCMs
526 fDmemDepth[iAddr] = fgkDmemSizeUniform;
527 }
528
529 else {
530 fDmem[iAddr] = NULL;
531 fDmemDepth[iAddr] = fgkDmemSizeEmpty;
532 }
533
051af255 534 }
535
ce4786b9 536 InitRegs();
8ea391e3 537 ResetDmem();
ce4786b9 538}
539
540
541AliTRDtrapConfig* AliTRDtrapConfig::Instance()
542{
543 // return a pointer to an instance of this class
544
545 if (!fgInstance) {
546 fgInstance = new AliTRDtrapConfig();
547 fgInstance->LoadConfig();
548 }
549
550 return fgInstance;
551}
552
553
051af255 554AliTRDtrapConfig::~AliTRDtrapConfig()
555{
8ea391e3 556 for(Int_t iAddr = 0; iAddr < fgkDmemWords; iAddr++) {
557 if(iAddr == fgkDmemAddrDeflCorr - fgkDmemStartAddress)
558 delete [] fDmem[iAddr];
559
560 else if(iAddr == fgkDmemAddrNdrift - fgkDmemStartAddress)
561 delete [] fDmem[iAddr];
562
563 else if(iAddr >= fgkDmemAddrDeflCutStart-fgkDmemStartAddress && iAddr <= fgkDmemAddrDeflCutEnd-fgkDmemStartAddress)
564 delete [] fDmem[iAddr];
565
566 else if(iAddr >= fgkDmemAddrTrackletStart-fgkDmemStartAddress && iAddr <= fgkDmemAddrTrackletEnd-fgkDmemStartAddress)
567 delete [] fDmem[iAddr];
568
569 else if(iAddr >= fgkDmemAddrLUTStart-fgkDmemStartAddress && iAddr <= fgkDmemAddrLUTEnd-fgkDmemStartAddress)
570 delete fDmem[iAddr];
571
572 else if(iAddr == fgkDmemAddrLUTcor0-fgkDmemStartAddress)
573 delete [] fDmem[iAddr];
574
575 else if(iAddr == fgkDmemAddrLUTcor1-fgkDmemStartAddress)
576 delete [] fDmem[iAddr];
577
578 else if(iAddr == fgkDmemAddrLUTnbins-fgkDmemStartAddress)
579 delete fDmem[iAddr];
580
581 else if(iAddr == fgkDmemAddrLUTLength-fgkDmemStartAddress)
582 delete fDmem[iAddr];
051af255 583 }
584}
585
586
8ea391e3 587void AliTRDtrapConfig::InitRegs()
ce4786b9 588{
589 // Reset the content of all TRAP registers to the reset values (see TRAP User Manual)
590
591 for (Int_t iReg = 0; iReg < kLastReg; iReg++) {
592
593 fRegisterValue[iReg].individualValue = 0x0;
594
595 fRegisterValue[iReg].globalValue = GetRegResetValue((TrapReg_t) iReg);
596 fRegisterValue[iReg].state = RegValue_t::kGlobal;
597 }
598}
599
600
8ea391e3 601void AliTRDtrapConfig::ResetRegs()
ce4786b9 602{
603 // Reset the content of all TRAP registers to the reset values (see TRAP User Manual)
604
605 for (Int_t iReg = 0; iReg < kLastReg; iReg++) {
606 if(fRegisterValue[iReg].state == RegValue_t::kIndividual) {
607 if (fRegisterValue[iReg].individualValue) {
608 delete [] fRegisterValue[iReg].individualValue;
609 fRegisterValue[iReg].individualValue = 0x0;
610 }
611 }
612
613 fRegisterValue[iReg].globalValue = GetRegResetValue((TrapReg_t) iReg);
614 fRegisterValue[iReg].state = RegValue_t::kGlobal;
615 // printf("%-8s: 0x%08x\n", GetRegName((TrapReg_t) iReg), fRegisterValue[iReg].globalValue);
616 }
617}
618
619
8ea391e3 620void AliTRDtrapConfig::ResetDmem()
621{
622 for(Int_t iAddr = 0; iAddr < fgkDmemWords; iAddr++) {
623 if(fDmemDepth[iAddr] == 0)
624 continue;
625 for(Int_t j=0; j < fDmemDepth[iAddr]; j++) {
626 fDmem[iAddr][j]=0;
627 }
628 }
629}
630
631
632Int_t AliTRDtrapConfig::GetTrapReg(TrapReg_t reg, Int_t det, Int_t rob, Int_t mcm) const
ce4786b9 633{
634 // get the value of an individual TRAP register
635 // if it is individual for TRAPs a valid TRAP has to be specified
636
637 if ((reg < 0) || (reg >= kLastReg)) {
638 AliError("Non-existing register requested");
639 return -1;
640 }
641 else {
642 if (fRegisterValue[reg].state == RegValue_t::kGlobal) {
643 return fRegisterValue[reg].globalValue;
644 }
645 else if (fRegisterValue[reg].state == RegValue_t::kIndividual) {
646 if((det >= 0 && det < AliTRDgeometry::Ndet()) &&
647 (rob >= 0 && rob < AliTRDfeeParam::GetNrobC1()) &&
648 (mcm >= 0 && mcm < fgkMaxMcm)) {
649 return fRegisterValue[reg].individualValue[det*AliTRDfeeParam::GetNrobC1()*fgkMaxMcm + rob*fgkMaxMcm + mcm];
650 }
651 else {
652 AliError("Invalid MCM specified or register is individual");
653 return -1;
654 }
655 }
656 else { // should never be reached
657 AliError("MCM register status neither kGlobal nor kIndividual");
658 return -1;
659 }
660 }
661 return -1;
662}
663
664
665Bool_t AliTRDtrapConfig::SetTrapReg(TrapReg_t reg, Int_t value)
666{
667 // set a global value for the given TRAP register,
668 // i.e. the same value for all TRAPs
669
670 if (fRegisterValue[reg].state == RegValue_t::kGlobal) {
671 fRegisterValue[reg].globalValue = value;
672 return kTRUE;
673 }
674 else {
675 AliError("Register has individual values");
676 }
677 return kFALSE;
678}
679
680
681Bool_t AliTRDtrapConfig::SetTrapReg(TrapReg_t reg, Int_t value, Int_t det)
682{
683 // set a global value for the given TRAP register,
684 // i.e. the same value for all TRAPs
685
686 if (fRegisterValue[reg].state == RegValue_t::kGlobal) {
687 fRegisterValue[reg].globalValue = value;
688 return kTRUE;
689 }
690 else if (fRegisterValue[reg].state == RegValue_t::kIndividual) {
691 // if the register is in idividual mode but a broadcast is requested, the selected register is
692 // set to value for all MCMs on the chamber
693
694 if( (det>=0 && det<AliTRDgeometry::Ndet())) {
695 for(Int_t rob=0; rob<AliTRDfeeParam::GetNrobC1(); rob++) {
696 for(Int_t mcm=0; mcm<fgkMaxMcm; mcm++)
697 fRegisterValue[reg].individualValue[det*AliTRDfeeParam::GetNrobC1()*fgkMaxMcm + rob*fgkMaxMcm + mcm] = value;
698 }
699 }
700 else {
8ea391e3 701 AliError(Form("Invalid detector number: %i\n", det));
ce4786b9 702 return kFALSE;
703 }
704 }
705 else { // should never be reached
706 AliError("MCM register status neither kGlobal nor kIndividual");
707 return kFALSE;
708 }
709
710 return kFALSE;
711}
712
713
714Bool_t AliTRDtrapConfig::SetTrapReg(TrapReg_t reg, Int_t value, Int_t det, Int_t rob, Int_t mcm)
715{
716 // set the value for the given TRAP register of an individual MCM
717
051af255 718 //std::cout << "-- reg: 0x" << std::hex << fRegs[reg].addr <<
719 //std::dec << ", data " << value << ", det " << det << ", rob " << rob << ", mcm " << mcm << std::endl;
ce4786b9 720
721 if( (det >= 0 && det < AliTRDgeometry::Ndet()) &&
722 (rob >= 0 && rob < AliTRDfeeParam::GetNrobC1()) &&
723 (mcm >= 0 && mcm < fgkMaxMcm) ) {
724 if (fRegisterValue[reg].state == RegValue_t::kGlobal) {
725 Int_t defaultValue = fRegisterValue[reg].globalValue;
726
727 fRegisterValue[reg].state = RegValue_t::kIndividual;
728 fRegisterValue[reg].individualValue = new Int_t[AliTRDgeometry::Ndet()*AliTRDfeeParam::GetNrobC1()*fgkMaxMcm];
729
730 for(Int_t i = 0; i < AliTRDgeometry::Ndet()*AliTRDfeeParam::GetNrobC1()*fgkMaxMcm; i++)
731 fRegisterValue[reg].individualValue[i] = defaultValue; // set the requested register of all MCMs to the value previously stored
732
733 fRegisterValue[reg].individualValue[det*AliTRDfeeParam::GetNrobC1()*fgkMaxMcm + rob*fgkMaxMcm + mcm] = value;
734 }
735 else if (fRegisterValue[reg].state == RegValue_t::kIndividual) {
736 fRegisterValue[reg].individualValue[det*AliTRDfeeParam::GetNrobC1()*fgkMaxMcm + rob*fgkMaxMcm + mcm] = value;
737 }
738 else { // should never be reached
739 AliError("MCM register status neither kGlobal nor kIndividual");
740 return kFALSE;
741 }
742 }
743 else {
8ea391e3 744 AliError(Form("Invalid value for det, ROB or MCM selected: %i, %i, %i", det, rob, mcm));
ce4786b9 745 return kFALSE;
746 }
747
748 return kTRUE;
749}
750
751
8ea391e3 752UInt_t AliTRDtrapConfig::Peek(Int_t addr, Int_t det, Int_t rob, Int_t mcm) const
ce4786b9 753{
754 // reading from given address
ce4786b9 755
756 if ( (addr >= fgkDmemStartAddress) &&
757 (addr < (fgkDmemStartAddress + fgkDmemWords)) ) {
8ea391e3 758 return GetDmemUnsigned(addr, det, rob, mcm);
ce4786b9 759 }
760 else {
761 TrapReg_t mcmReg = GetRegByAddress(addr);
762 if ( mcmReg >= 0 && mcmReg < kLastReg) {
8ea391e3 763 return (UInt_t) GetTrapReg(mcmReg, det, rob, mcm);
ce4786b9 764 }
765 }
766
767 return -1;
768}
769
770
8ea391e3 771Bool_t AliTRDtrapConfig::Poke(Int_t addr, UInt_t value, Int_t det, Int_t rob, Int_t mcm)
ce4786b9 772{
773 // writing to given address
ce4786b9 774
775 if ( (addr >= fgkDmemStartAddress) &&
776 (addr < (fgkDmemStartAddress + fgkDmemWords)) ) {
051af255 777 AliDebug(2, Form("DMEM 0x%08x : %i", addr, value));
778 SetDmem(addr, value, det, rob, mcm);
ce4786b9 779 return kTRUE;
780 }
781 else {
782 TrapReg_t mcmReg = GetRegByAddress(addr);
783 if ( mcmReg >= 0 && mcmReg < kLastReg) {
051af255 784 AliDebug(2, Form("Register: %s : %i\n", GetRegName(mcmReg), value));
8ea391e3 785 SetTrapReg(mcmReg, (UInt_t) value, det, rob, mcm);
ce4786b9 786 return kTRUE;
787 }
788 }
051af255 789
ce4786b9 790 return kFALSE;
791}
792
793
051af255 794Bool_t AliTRDtrapConfig::SetDmem(Int_t addr, UInt_t value)
ce4786b9 795{
59f78ad5 796 // Set the content of the given DMEM address
797
8ea391e3 798 addr = addr - fgkDmemStartAddress;
ce4786b9 799
8ea391e3 800 if(addr < 0 || addr >= fgkDmemWords) {
5ac2e3b1 801 AliError(Form("No DMEM address: 0x%08x", addr+fgkDmemStartAddress));
8ea391e3 802 return kFALSE;
803 }
804
805 switch(fDmemDepth[addr]) {
806 case fgkDmemSizeEmpty:
5ac2e3b1 807 AliDebug(4, Form("DMEM address %i not active", addr));
8ea391e3 808 return kFALSE;
809 break;
810 case fgkDmemSizeUniform:
811 if(fDmem[addr][0]!=0)
812 AliDebug(5, Form("Warning: Setting new value to DMEM 0x%08x", addr+fgkDmemStartAddress));
813
814 fDmem[addr][0] = value;
815 break;
816 case fgkDmemSizeSmIndividual:
817 for(Int_t i=0; i<fgkDmemSizeSmIndividual; i++) {
818 if(fDmem[addr][i]!=0)
819 AliDebug(5, Form("Warning: Setting new value to DMEM 0x%08x", addr+fgkDmemStartAddress));
820
821 fDmem[addr][i]=value;
051af255 822 }
8ea391e3 823 break;
824 case fgkDmemSizeTotalIndividual:
825 for(Int_t i=0; i<fgkDmemSizeTotalIndividual; i++) {
826 if(fDmem[addr][i]!=0)
827 AliDebug(5, Form("Warning: Setting new value to DMEM 0x%08x", addr+fgkDmemStartAddress));
828
829 fDmem[addr][i]=value;
051af255 830 }
8ea391e3 831 break;
832 case fgkDmemSizeSmRocIndividual:
833 for(Int_t i=0; i<fgkDmemSizeSmRocIndividual; i++) {
834 if(fDmem[addr][i]!=0)
835 AliDebug(5, Form("Warning: Setting new value to DMEM 0x%08x", addr+fgkDmemStartAddress));
836
837 fDmem[addr][i]=value;
ce4786b9 838 }
8ea391e3 839 break;
840 default:
841 AliError(Form("Invalid selection type"));
842 break;
843 }
051af255 844
8ea391e3 845 return kTRUE;
ce4786b9 846}
847
848
8ea391e3 849Bool_t AliTRDtrapConfig::SetDmem(Int_t addr, UInt_t value, Int_t det, Int_t rob, Int_t mcm)
ce4786b9 850{
59f78ad5 851 // Set the content of the given DMEM address
852
8ea391e3 853 addr = addr - fgkDmemStartAddress;
854 Int_t roc = det%30;
855 Int_t loc;
856
857 if(addr < 0 || addr >= fgkDmemWords) {
858 AliError(Form("No DMEM address: 0x%08x", addr+fgkDmemStartAddress));
859 return kFALSE;
860 }
861
862 Int_t detFactor=8*16;
863 Int_t robFactor=16;
051af255 864
8ea391e3 865 switch(fDmemDepth[addr]) {
866 case fgkDmemSizeEmpty:
5ac2e3b1 867 AliDebug(4, Form("DMEM address 0x%08x not active", addr+fgkDmemStartAddress));
8ea391e3 868 return kFALSE;
869 break;
870 case fgkDmemSizeUniform:
871 if(fDmem[addr][0]!=0)
872 AliDebug(5, Form("Warning: Setting new value to DMEM 0x%08x", addr+fgkDmemStartAddress));
873
874 fDmem[addr][0] = value;
875 break;
876 case fgkDmemSizeSmIndividual:
877 loc = detFactor*roc + robFactor*rob + mcm;
878 if(loc < fgkDmemSizeSmIndividual) {
879 if(fDmem[addr][loc]!=0)
880 AliDebug(5, Form("Warning: Setting new value to DMEM 0x%08x", addr+fgkDmemStartAddress));
881
882 fDmem[addr][loc] = value;
051af255 883 }
8ea391e3 884 else {
885 AliError(Form("DMEM sub-address %i out of scope", loc));
886 return kFALSE;
051af255 887 }
8ea391e3 888 break;
889 case fgkDmemSizeTotalIndividual:
890 loc = detFactor*det + robFactor*rob + mcm;
891 if(loc < fgkDmemSizeTotalIndividual) {
892 if(fDmem[addr][loc]!=0)
893 AliDebug(5, Form("Warning: Setting new value to DMEM 0x%08x", addr+fgkDmemStartAddress));
894
895 fDmem[addr][loc]=value;
051af255 896 }
8ea391e3 897 else {
898 AliError(Form("DMEM sub-address %i out of scope", loc));
899 return kFALSE;
900 }
901 break;
902 case fgkDmemSizeSmRocIndividual:
903 if(det < fgkDmemSizeSmRocIndividual) {
904 if(fDmem[addr][det]!=0)
905 AliDebug(5, Form("Warning: Setting new value to DMEM 0x%08x", addr+fgkDmemStartAddress));
051af255 906
8ea391e3 907 fDmem[addr][det]=value;
908 }
909 else {
910 AliError(Form("DMEM sub-address %i out of scope", det));
911 return kFALSE;
912 }
913
914 break;
915 default:
916 AliError(Form("Invalid selection type"));
917 return kFALSE;
918 break;
919 }
920
921 return kTRUE;
ce4786b9 922}
923
924
8ea391e3 925UInt_t AliTRDtrapConfig::GetDmemUnsigned(Int_t addr) const
ce4786b9 926{
8ea391e3 927 addr = addr - fgkDmemStartAddress;
5ac2e3b1 928 if(addr < 0 || addr >= fgkDmemWords) {
8ea391e3 929 AliError(Form("No DMEM address: 0x%08x", addr+fgkDmemStartAddress));
930 return 0;
931 }
051af255 932
8ea391e3 933 if(fDmemDepth[addr] == fgkDmemSizeUniform)
934 return fDmem[addr][0];
935 else {
936 AliError(Form("No global DMEM value at 0x%08x", addr+fgkDmemStartAddress));
937 return 0;
938 }
939 return 0;
ce4786b9 940}
941
8ea391e3 942UInt_t AliTRDtrapConfig::GetDmemUnsigned(Int_t addr, Int_t det, Int_t rob, Int_t mcm) const
ce4786b9 943{
8ea391e3 944 addr = addr - fgkDmemStartAddress;
945 Int_t roc = det%30;
946 Int_t loc;
947
948 if(addr < 0 || addr >= fgkDmemWords) {
949 AliError(Form("No DMEM address: 0x%08x", addr+fgkDmemStartAddress));
950 return 0;
951 }
59f78ad5 952
8ea391e3 953 Int_t detFactor=8*16;
954 Int_t robFactor=16;
955
956 switch(fDmemDepth[addr]) {
957 case fgkDmemSizeEmpty:
5ac2e3b1 958 AliDebug(4, Form("DMEM address 0x%08x not active", addr+fgkDmemStartAddress));
8ea391e3 959 return 0;
960 break;
961 case fgkDmemSizeUniform:
962 return fDmem[addr][0];
963 break;
964 case fgkDmemSizeSmIndividual:
965 loc = detFactor*roc + robFactor*rob + mcm;
966 if(loc < fgkDmemSizeSmIndividual) {
967 return fDmem[addr][loc];
968 }
969 else {
970 AliError(Form("DMEM sub-address %i out of scope", loc));
971 return 0;
972 }
973 break;
974 case fgkDmemSizeTotalIndividual:
975 loc = detFactor*det + robFactor*rob + mcm;
976 if(loc < fgkDmemSizeTotalIndividual) {
977 return fDmem[addr][loc];
978 }
979 else {
980 AliError(Form("DMEM sub-address %i out of scope", loc));
981 return 0;
982 }
983 break;
984 case fgkDmemSizeSmRocIndividual:
985 if(det < fgkDmemSizeSmRocIndividual) {
986 return fDmem[addr][det];
987 }
988 else {
989 AliError(Form("DMEM sub-address %i out of scope", det));
990 return 0;
991 }
992 break;
993 default:
994 AliError(Form("Invalid selection type"));
995 return 0;
996 break;
997 }
998
999 return 0;
ce4786b9 1000}
1001
1002
1003Bool_t AliTRDtrapConfig::LoadConfig()
1004{
1005 // load a set of TRAP register values (configuration)
1006 // here a default set is implemented for testing
1007 // for a detailed description of the registers see the TRAP manual
1008
7d619a80 1009 // HC header configuration bits
1010 SetTrapReg(kC15CPUA, 0x2102); // zs, deh
1011
ce4786b9 1012 // no. of timebins
1013 SetTrapReg(kC13CPUA, 24);
1014
1015 // pedestal filter
1016 SetTrapReg(kFPNP, 4*10);
1017 SetTrapReg(kFPTC, 0);
1018 SetTrapReg(kFPBY, 0); // bypassed!
1019
1020 // gain filter
1021 for (Int_t adc = 0; adc < 20; adc++) {
1022 SetTrapReg(TrapReg_t(kFGA0+adc), 40);
1023 SetTrapReg(TrapReg_t(kFGF0+adc), 15);
1024 }
1025 SetTrapReg(kFGTA, 20);
1026 SetTrapReg(kFGTB, 2060);
1027 SetTrapReg(kFGBY, 0); // bypassed!
1028
1029 // tail cancellation
1030 SetTrapReg(kFTAL, 267);
1031 SetTrapReg(kFTLL, 356);
1032 SetTrapReg(kFTLS, 387);
1033 SetTrapReg(kFTBY, 0);
1034
1035 // tracklet calculation
1036 SetTrapReg(kTPQS0, 5);
1037 SetTrapReg(kTPQE0, 10);
1038 SetTrapReg(kTPQS1, 11);
1039 SetTrapReg(kTPQE1, 20);
1040 SetTrapReg(kTPFS, 5);
1041 SetTrapReg(kTPFE, 20);
1042 SetTrapReg(kTPVBY, 0);
1043 SetTrapReg(kTPVT, 10);
1044 SetTrapReg(kTPHT, 150);
1045 SetTrapReg(kTPFP, 40);
1046 SetTrapReg(kTPCL, 1);
1047 SetTrapReg(kTPCT, 10);
1048
1049 // ndrift (+ 5 binary digits)
1050 SetDmem(0xc025, 20 << 5);
1051 // deflection + tilt correction
1052 SetDmem(0xc022, 0);
1053 // deflection range table
1054 for (Int_t iTrklCh = 0; iTrklCh < 18; iTrklCh++) {
1055 SetDmem(0xc030 + 2 * iTrklCh, -64); // min. deflection
1056 SetDmem(0xc031 + 2 * iTrklCh, 63); // max. deflection
1057 }
1058
1059 // hit position LUT
1060 const UShort_t lutPos[128] = {
1061 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15,
1062 16, 16, 16, 17, 17, 18, 18, 19, 19, 19, 20, 20, 20, 21, 21, 22, 22, 22, 23, 23, 23, 24, 24, 24, 24, 25, 25, 25, 26, 26, 26, 26,
1063 27, 27, 27, 27, 27, 27, 27, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 27, 27, 27, 27, 26,
1064 26, 26, 26, 25, 25, 25, 24, 24, 23, 23, 22, 22, 21, 21, 20, 20, 19, 18, 18, 17, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 7};
1065 for (Int_t iCOG = 0; iCOG < 128; iCOG++)
1066 SetTrapReg((TrapReg_t) (kTPL00 + iCOG), lutPos[iCOG]);
1067
1068 // event buffer
1069 SetTrapReg(kEBSF, 1); // 0: store filtered; 1: store unfiltered
1070 // zs applied to data stored in event buffer (sel. by EBSF)
1071 SetTrapReg(kEBIS, 15 << 2); // single indicator threshold (plus two digits)
1072 SetTrapReg(kEBIT, 30 << 2); // sum indicator threshold (plus two digits)
1073 SetTrapReg(kEBIL, 0xf0); // lookup table
1074 SetTrapReg(kEBIN, 0); // neighbour sensitivity
1075
1076 // raw data
1077 SetTrapReg(kNES, (0x0000 << 16) | 0x1000);
1078
1079 return kTRUE;
1080}
1081
1082
051af255 1083Bool_t AliTRDtrapConfig::ReadPackedConfig(Int_t hc, UInt_t *data, Int_t size)
ce4786b9 1084{
59f78ad5 1085 // Read the packed configuration from the passed memory block
1086 //
1087 // To be used to retrieve the TRAP configuration from the
1088 // configuration as sent in the raw data.
1089
051af255 1090 AliDebug(1, "Reading packed configuration");
1091
1092 Int_t det = hc/2;
1093
ce4786b9 1094 Int_t idx = 0;
1095 Int_t err = 0;
59f78ad5 1096 Int_t step, bwidth, nwords, exitFlag, bitcnt;
ce4786b9 1097
1098 UShort_t caddr;
59f78ad5 1099 UInt_t dat, msk, header, dataHi;
ce4786b9 1100
051af255 1101 while (idx < size && *data != 0x00000000) {
ce4786b9 1102
051af255 1103 Int_t rob = (*data >> 28) & 0x7;
1104 Int_t mcm = (*data >> 24) & 0xf;
1105
1106 AliDebug(1, Form("Config of det. %3i MCM %i:%02i (0x%08x)", det, rob, mcm, *data));
ce4786b9 1107 data++;
ce4786b9 1108
051af255 1109 while (idx < size && *data != 0x00000000) {
ce4786b9 1110
051af255 1111 header = *data;
1112 data++;
1113 idx++;
ce4786b9 1114
051af255 1115 AliDebug(5, Form("read: 0x%08x", header));
ce4786b9 1116
8ea391e3 1117 if (header & 0x01) // single data
051af255 1118 {
8ea391e3 1119 dat = (header >> 2) & 0xFFFF; // 16 bit data
1120 caddr = (header >> 18) & 0x3FFF; // 14 bit address
051af255 1121
8ea391e3 1122 if (caddr != 0x1FFF) // temp!!! because the end marker was wrong
051af255 1123 {
8ea391e3 1124 if (header & 0x02) // check if > 16 bits
051af255 1125 {
1126 dataHi = *data;
1127 AliDebug(5, Form("read: 0x%08x", dataHi));
1128 data++;
1129 idx++;
1130 err += ((dataHi ^ (dat | 1)) & 0xFFFF) != 0;
1131 dat = (dataHi & 0xFFFF0000) | dat;
1132 }
1133 AliDebug(5, Form("addr=0x%04x (%s) data=0x%08x\n", caddr, GetRegName(GetRegByAddress(caddr)), dat));
1134 if ( ! Poke(caddr, dat, det, rob, mcm) )
1135 AliDebug(5, Form("(single-write): non-existing address 0x%04x containing 0x%08x\n", caddr, header));
1136 if (idx > size)
1137 {
1138 AliDebug(5, Form("(single-write): no more data, missing end marker\n"));
1139 return -err;
1140 }
1141 }
1142 else
1143 {
1144 AliDebug(5, Form("(single-write): address 0x%04x => old endmarker?\n", caddr));
1145 return err;
1146 }
1147 }
1148
8ea391e3 1149 else // block of data
051af255 1150 {
1151 step = (header >> 1) & 0x0003;
1152 bwidth = ((header >> 3) & 0x001F) + 1;
1153 nwords = (header >> 8) & 0x00FF;
1154 caddr = (header >> 16) & 0xFFFF;
1155 exitFlag = (step == 0) || (step == 3) || (nwords == 0);
1156
1157 if (exitFlag)
1158 break;
1159
1160 switch (bwidth)
1161 {
1162 case 15:
1163 case 10:
1164 case 7:
1165 case 6:
1166 case 5:
1167 {
1168 msk = (1 << bwidth) - 1;
1169 bitcnt = 0;
1170 while (nwords > 0)
1171 {
1172 nwords--;
1173 bitcnt -= bwidth;
1174 if (bitcnt < 0)
1175 {
1176 header = *data;
1177 AliDebug(5, Form("read 0x%08x", header));
1178 data++;
1179 idx++;
1180 err += (header & 1);
1181 header = header >> 1;
1182 bitcnt = 31 - bwidth;
1183 }
1184 AliDebug(5, Form("addr=0x%04x (%s) data=0x%08x\n", caddr, GetRegName(GetRegByAddress(caddr)), header & msk));
1185 if ( ! Poke(caddr, header & msk, det, rob, mcm) )
1186 AliDebug(5, Form("(single-write): non-existing address 0x%04x containing 0x%08x\n", caddr, header));
1187
1188 caddr += step;
1189 header = header >> bwidth;
1190 if (idx >= size)
1191 {
1192 AliDebug(5, Form("(block-write): no end marker! %d words read\n", idx));
1193 return -err;
1194 }
1195 }
1196 break;
1197 } // end case 5-15
1198 case 31:
1199 {
1200 while (nwords > 0)
1201 {
1202 header = *data;
1203 AliDebug(5, Form("read 0x%08x", header));
1204 data++;
1205 idx++;
1206 nwords--;
1207 err += (header & 1);
1208
1209 AliDebug(5, Form("addr=0x%04x (%s) data=0x%08x", caddr, GetRegName(GetRegByAddress(caddr)), header >> 1));
1210 if ( ! Poke(caddr, header >> 1, det, rob, mcm) )
1211 AliDebug(5, Form("(single-write): non-existing address 0x%04x containing 0x%08x\n", caddr, header));
1212
1213 caddr += step;
1214 if (idx >= size)
1215 {
1216 AliDebug(5, Form("no end marker! %d words read", idx));
1217 return -err;
1218 }
1219 }
1220 break;
1221 }
1222 default: return err;
8ea391e3 1223 } // end switch
1224 } // end block case
051af255 1225 }
8ea391e3 1226 } // end while
ce4786b9 1227 AliDebug(5, Form("no end marker! %d words read", idx));
1228 return -err; // only if the max length of the block reached!
1229}
1230
1231
8ea391e3 1232Bool_t AliTRDtrapConfig::PrintTrapReg(TrapReg_t reg, Int_t det, Int_t rob, Int_t mcm) const
ce4786b9 1233{
1234 // print the value stored in the given register
1235 // if it is individual a valid MCM has to be specified
1236
1237 if (fRegisterValue[reg].state == RegValue_t::kGlobal) {
1238 printf("%s (%i bits) at 0x%08x is 0x%08x and resets to: 0x%08x (currently global mode)\n",
1239 GetRegName((TrapReg_t) reg),
1240 GetRegNBits((TrapReg_t) reg),
1241 GetRegAddress((TrapReg_t) reg),
1242 fRegisterValue[reg].globalValue,
1243 GetRegResetValue((TrapReg_t) reg));
1244 }
1245 else if (fRegisterValue[reg].state == RegValue_t::kIndividual) {
1246 if((det >= 0 && det < AliTRDgeometry::Ndet()) &&
1247 (rob >= 0 && rob < AliTRDfeeParam::GetNrobC1()) &&
1248 (mcm >= 0 && mcm < fgkMaxMcm)) {
1249 printf("%s (%i bits) at 0x%08x is 0x%08x and resets to: 0x%08x (currently individual mode)\n",
1250 GetRegName((TrapReg_t) reg),
1251 GetRegNBits((TrapReg_t) reg),
1252 GetRegAddress((TrapReg_t) reg),
1253 fRegisterValue[reg].individualValue[det*AliTRDfeeParam::GetNrobC1()*fgkMaxMcm + rob*fgkMaxMcm + mcm],
1254 GetRegResetValue((TrapReg_t) reg));
1255 }
1256 else {
1257 AliError("Register value is MCM-specific: Invalid detector, ROB or MCM requested");
1258 return kFALSE;
1259 }
1260 }
1261 else { // should never be reached
1262 AliError("MCM register status neither kGlobal nor kIndividual");
1263 return kFALSE;
1264 }
1265 return kTRUE;
1266}
1267
1268
8ea391e3 1269Bool_t AliTRDtrapConfig::PrintTrapAddr(Int_t addr, Int_t det, Int_t rob, Int_t mcm) const
ce4786b9 1270{
1271 // print the value stored at the given address in the MCM chip
1272 TrapReg_t reg = GetRegByAddress(addr);
1273 if (reg >= 0 && reg < kLastReg) {
1274 return PrintTrapReg(reg, det, rob, mcm);
1275 }
1276 else {
1277 AliError(Form("There is no register at address 0x%08x in the simulator", addr));
1278 return kFALSE;
1279 }
1280}
1281
1282
1283Bool_t AliTRDtrapConfig::AddValues(UInt_t det, UInt_t cmd, UInt_t extali, Int_t addr, UInt_t data)
1284{
1285 // transfer the informations provided by LoadConfig to the internal class variables
1286
1287 if(cmd != fgkScsnCmdWrite) {
1288 AliError(Form("Invalid command received: %i", cmd));
1289 return kFALSE;
1290 }
1291
1292 TrapReg_t mcmReg = GetRegByAddress(addr);
1293 Int_t rocType = AliTRDgeometry::GetStack(det) == 2 ? 0 : 1;
1294
8ea391e3 1295 static const int mcmListSize=40; // 40 is more or less arbitrary
1296 Int_t mcmList[mcmListSize];
1297
ce4786b9 1298 // configuration registers
1299 if(mcmReg >= 0 && mcmReg < kLastReg) {
1300
1301 for(Int_t linkPair=0; linkPair<fgkMaxLinkPairs; linkPair++) {
8ea391e3 1302 if(AliTRDfeeParam::ExtAliToAli(extali, linkPair, rocType, mcmList, mcmListSize)!=0) {
1303 Int_t i=0;
1304 while(mcmList[i] != -1 && i<mcmListSize) {
1305 if(mcmList[i]==127)
ce4786b9 1306 SetTrapReg( (TrapReg_t) mcmReg, data, det);
1307 else
8ea391e3 1308 SetTrapReg( (TrapReg_t) mcmReg, data, det, (mcmList[i]>>7), (mcmList[i]&0x7F));
ce4786b9 1309 i++;
1310 }
1311 }
1312 }
1313 return kTRUE;
1314 }
1315 // DMEM
1316 else if ( (addr >= fgkDmemStartAddress) &&
1317 (addr < (fgkDmemStartAddress + fgkDmemWords))) {
1318 for(Int_t linkPair=0; linkPair<fgkMaxLinkPairs; linkPair++) {
8ea391e3 1319 if(AliTRDfeeParam::ExtAliToAli(extali, linkPair, rocType, mcmList, mcmListSize)!=0) {
ce4786b9 1320 Int_t i=0;
8ea391e3 1321 while(mcmList[i] != -1 && i < mcmListSize) {
1322 if(mcmList[i] == 127)
1323 SetDmem(addr, data, det, 0, 127);
ce4786b9 1324 else
8ea391e3 1325 SetDmem(addr, data, det, mcmList[i] >> 7, mcmList[i] & 0x7f);
ce4786b9 1326 i++;
1327 }
1328 }
1329 }
1330 return kTRUE;
1331 }
1332 else
1333 return kFALSE;
1334}
1335
1336
8ea391e3 1337AliTRDtrapConfig::TrapReg_t AliTRDtrapConfig::GetRegByAddress(Int_t address) const
ce4786b9 1338{
8ea391e3 1339 // get register by its address
1340 // used for reading of configuration data as sent to real FEE
ce4786b9 1341
8ea391e3 1342 TrapReg_t mcmReg = kLastReg;
1343 Int_t reg = 0;
1344 do {
1345 if(fRegs[reg].fAddr == address)
1346 mcmReg = (TrapReg_t) reg;
1347 reg++;
1348 } while (mcmReg == kLastReg && reg < kLastReg);
ce4786b9 1349
8ea391e3 1350 return mcmReg;
ce4786b9 1351}
1352
1353
8ea391e3 1354void AliTRDtrapConfig::PrintMemDatx(ostream &os, Int_t addr) const
ce4786b9 1355{
8ea391e3 1356 PrintMemDatx(os, addr, 0, 0, 127);
ce4786b9 1357}
1358
8ea391e3 1359void AliTRDtrapConfig::PrintMemDatx(ostream &os, Int_t addr, Int_t det, Int_t rob, Int_t mcm) const
ce4786b9 1360{
8ea391e3 1361 if(addr < fgkDmemStartAddress || addr >= fgkDmemStartAddress+fgkDmemWords) {
1362 AliError(Form("Invalid DMEM address 0x%08x!", addr));
1363 return;
1364 }
1365 PrintDatx(os, addr, GetDmemUnsigned(addr, det, rob, mcm), rob, mcm);
1366}
1367
ce4786b9 1368
8ea391e3 1369void AliTRDtrapConfig::PrintMemDatx(ostream &os, TrapReg_t reg) const
1370{
1371 PrintMemDatx(os, reg, 0, 0, 127);
ce4786b9 1372}
1373
1374
8ea391e3 1375void AliTRDtrapConfig::PrintMemDatx(ostream &os, TrapReg_t reg, Int_t det, Int_t rob, Int_t mcm) const
ce4786b9 1376{
8ea391e3 1377 if(reg>= kLastReg) {
1378 AliError(Form("Invalid register %i!", reg));
1379 return;
1380 }
1381 PrintDatx(os, GetRegAddress(reg), GetTrapReg(reg, det, rob, mcm), rob, mcm);
1382}
36dc3337 1383
ce4786b9 1384
8ea391e3 1385void AliTRDtrapConfig::PrintDatx(ostream &os, UInt_t addr, UInt_t data, Int_t rob, Int_t mcm) const
1386{
1387 os << std::setw(5) << 10
1388 << std::setw(8) << addr
1389 << std::setw(12) << data;
1390 if(mcm==127)
1391 os << std::setw(8) << 127;
1392 else
1393 os << std::setw(8) << AliTRDfeeParam::AliToExtAli(rob, mcm);
1394
1395 os << std::endl;
ce4786b9 1396}