Next round of fixes (Jochen)
[u/mrichter/AliRoot.git] / TRD / AliTRDtrapConfig.cxx
CommitLineData
36dc3337 1/**************************************************************************
2 * Copyright(c) 1998-1999, ALICE Experiment at CERN, All rights reserved. *
3 * *
4 * Author: The ALICE Off-line Project. *
5 * Contributors are mentioned in the code where appropriate. *
6 * *
7 * Permission to use, copy, modify and distribute this software and its *
8 * documentation strictly for non-commercial purposes is hereby granted *
9 * without fee, provided that the above copyright notice appears in all *
10 * copies and that both the copyright notice and this permission notice *
11 * appear in the supporting documentation. The authors make no claims *
12 * about the suitability of this software for any purpose. It is *
13 * provided "as is" without express or implied warranty. *
14 **************************************************************************/
15
16////////////////////////////////////////////////////////////////////////////
17// //
18// TRAP config //
19// //
20// Author: J. Klein (Jochen.Klein@cern.ch) //
21// //
22////////////////////////////////////////////////////////////////////////////
23
ce4786b9 24#include "AliLog.h"
25
26#include "AliTRDgeometry.h"
27#include "AliTRDfeeParam.h"
28#include "AliTRDtrapConfig.h"
29
30#include <fstream>
31#include <iostream>
32#include <iomanip>
33
34ClassImp(AliTRDtrapConfig)
35
36AliTRDtrapConfig* AliTRDtrapConfig::fgInstance = 0x0;
37const Int_t AliTRDtrapConfig::fgkMaxMcm = AliTRDfeeParam::GetNmcmRob() + 2;
38const Int_t AliTRDtrapConfig::fgkDmemStartAddress = 0xc000;
39
40AliTRDtrapConfig::AliTRDtrapConfig() :
8ea391e3 41 TObject(), fScaleQ0(0), fScaleQ1(0)
ce4786b9 42{
43 // default constructor, initializing array of TRAP registers
44
45 // Name Address Nbits Reset Value
46 fRegs[kSML0] = SimpleReg_t("SML0", 0x0A00, 15, 0x4050 ); // Global state machine
47 fRegs[kSML1] = SimpleReg_t("SML1", 0x0A01, 15, 0x4200 );
48 fRegs[kSML2] = SimpleReg_t("SML2", 0x0A02, 15, 0x4384 );
49 fRegs[kSMMODE] = SimpleReg_t("SMMODE", 0x0A03, 16, 0xF0E2 );
50 fRegs[kNITM0] = SimpleReg_t("NITM0", 0x0A08, 14, 0x3FFF );
51 fRegs[kNITM1] = SimpleReg_t("NITM1", 0x0A09, 14, 0x3FFF );
52 fRegs[kNITM2] = SimpleReg_t("NITM2", 0x0A0A, 14, 0x3FFF );
53 fRegs[kNIP4D] = SimpleReg_t("NIP4D", 0x0A0B, 7, 0x7F );
54 fRegs[kCPU0CLK] = SimpleReg_t("CPU0CLK", 0x0A20, 5, 0x07 );
55 fRegs[kCPU1CLK] = SimpleReg_t("CPU1CLK", 0x0A22, 5, 0x07 );
56 fRegs[kCPU2CLK] = SimpleReg_t("CPU2CLK", 0x0A24, 5, 0x07 );
57 fRegs[kCPU3CLK] = SimpleReg_t("CPU3CLK", 0x0A26, 5, 0x07 );
58 fRegs[kNICLK] = SimpleReg_t("NICLK", 0x0A28, 5, 0x07 );
59 fRegs[kFILCLK] = SimpleReg_t("FILCLK", 0x0A2A, 5, 0x07 );
60 fRegs[kPRECLK] = SimpleReg_t("PRECLK", 0x0A2C, 5, 0x07 );
61 fRegs[kADCEN] = SimpleReg_t("ADCEN", 0x0A2E, 5, 0x07 );
62 fRegs[kNIODE] = SimpleReg_t("NIODE", 0x0A30, 5, 0x07 );
63 fRegs[kNIOCE] = SimpleReg_t("NIOCE", 0x0A32, 6, 0x21 ); // bit 5 is status bit (read-only)!
64 fRegs[kNIIDE] = SimpleReg_t("NIIDE", 0x0A34, 5, 0x07 );
65 fRegs[kNIICE] = SimpleReg_t("NIICE", 0x0A36, 5, 0x07 );
66 fRegs[kARBTIM] = SimpleReg_t("ARBTIM", 0x0A3F, 4, 0x0 ); // Arbiter
67 fRegs[kIA0IRQ0] = SimpleReg_t("IA0IRQ0", 0x0B00, 12, 0x000 ); // IVT of CPU0
68 fRegs[kIA0IRQ1] = SimpleReg_t("IA0IRQ1", 0x0B01, 12, 0x000 );
69 fRegs[kIA0IRQ2] = SimpleReg_t("IA0IRQ2", 0x0B02, 12, 0x000 );
70 fRegs[kIA0IRQ3] = SimpleReg_t("IA0IRQ3", 0x0B03, 12, 0x000 );
71 fRegs[kIA0IRQ4] = SimpleReg_t("IA0IRQ4", 0x0B04, 12, 0x000 );
72 fRegs[kIA0IRQ5] = SimpleReg_t("IA0IRQ5", 0x0B05, 12, 0x000 );
73 fRegs[kIA0IRQ6] = SimpleReg_t("IA0IRQ6", 0x0B06, 12, 0x000 );
74 fRegs[kIA0IRQ7] = SimpleReg_t("IA0IRQ7", 0x0B07, 12, 0x000 );
75 fRegs[kIA0IRQ8] = SimpleReg_t("IA0IRQ8", 0x0B08, 12, 0x000 );
76 fRegs[kIA0IRQ9] = SimpleReg_t("IA0IRQ9", 0x0B09, 12, 0x000 );
77 fRegs[kIA0IRQA] = SimpleReg_t("IA0IRQA", 0x0B0A, 12, 0x000 );
78 fRegs[kIA0IRQB] = SimpleReg_t("IA0IRQB", 0x0B0B, 12, 0x000 );
79 fRegs[kIA0IRQC] = SimpleReg_t("IA0IRQC", 0x0B0C, 12, 0x000 );
80 fRegs[kIRQSW0] = SimpleReg_t("IRQSW0", 0x0B0D, 13, 0x1FFF );
81 fRegs[kIRQHW0] = SimpleReg_t("IRQHW0", 0x0B0E, 13, 0x0000 );
82 fRegs[kIRQHL0] = SimpleReg_t("IRQHL0", 0x0B0F, 13, 0x0000 );
83 fRegs[kIA1IRQ0] = SimpleReg_t("IA1IRQ0", 0x0B20, 12, 0x000 ); // IVT of CPU1
84 fRegs[kIA1IRQ1] = SimpleReg_t("IA1IRQ1", 0x0B21, 12, 0x000 );
85 fRegs[kIA1IRQ2] = SimpleReg_t("IA1IRQ2", 0x0B22, 12, 0x000 );
86 fRegs[kIA1IRQ3] = SimpleReg_t("IA1IRQ3", 0x0B23, 12, 0x000 );
87 fRegs[kIA1IRQ4] = SimpleReg_t("IA1IRQ4", 0x0B24, 12, 0x000 );
88 fRegs[kIA1IRQ5] = SimpleReg_t("IA1IRQ5", 0x0B25, 12, 0x000 );
89 fRegs[kIA1IRQ6] = SimpleReg_t("IA1IRQ6", 0x0B26, 12, 0x000 );
90 fRegs[kIA1IRQ7] = SimpleReg_t("IA1IRQ7", 0x0B27, 12, 0x000 );
91 fRegs[kIA1IRQ8] = SimpleReg_t("IA1IRQ8", 0x0B28, 12, 0x000 );
92 fRegs[kIA1IRQ9] = SimpleReg_t("IA1IRQ9", 0x0B29, 12, 0x000 );
93 fRegs[kIA1IRQA] = SimpleReg_t("IA1IRQA", 0x0B2A, 12, 0x000 );
94 fRegs[kIA1IRQB] = SimpleReg_t("IA1IRQB", 0x0B2B, 12, 0x000 );
95 fRegs[kIA1IRQC] = SimpleReg_t("IA1IRQC", 0x0B2C, 12, 0x000 );
96 fRegs[kIRQSW1] = SimpleReg_t("IRQSW1", 0x0B2D, 13, 0x1FFF );
97 fRegs[kIRQHW1] = SimpleReg_t("IRQHW1", 0x0B2E, 13, 0x0000 );
98 fRegs[kIRQHL1] = SimpleReg_t("IRQHL1", 0x0B2F, 13, 0x0000 );
99 fRegs[kIA2IRQ0] = SimpleReg_t("IA2IRQ0", 0x0B40, 12, 0x000 ); // IVT of CPU2
100 fRegs[kIA2IRQ1] = SimpleReg_t("IA2IRQ1", 0x0B41, 12, 0x000 );
101 fRegs[kIA2IRQ2] = SimpleReg_t("IA2IRQ2", 0x0B42, 12, 0x000 );
102 fRegs[kIA2IRQ3] = SimpleReg_t("IA2IRQ3", 0x0B43, 12, 0x000 );
103 fRegs[kIA2IRQ4] = SimpleReg_t("IA2IRQ4", 0x0B44, 12, 0x000 );
104 fRegs[kIA2IRQ5] = SimpleReg_t("IA2IRQ5", 0x0B45, 12, 0x000 );
105 fRegs[kIA2IRQ6] = SimpleReg_t("IA2IRQ6", 0x0B46, 12, 0x000 );
106 fRegs[kIA2IRQ7] = SimpleReg_t("IA2IRQ7", 0x0B47, 12, 0x000 );
107 fRegs[kIA2IRQ8] = SimpleReg_t("IA2IRQ8", 0x0B48, 12, 0x000 );
108 fRegs[kIA2IRQ9] = SimpleReg_t("IA2IRQ9", 0x0B49, 12, 0x000 );
109 fRegs[kIA2IRQA] = SimpleReg_t("IA2IRQA", 0x0B4A, 12, 0x000 );
110 fRegs[kIA2IRQB] = SimpleReg_t("IA2IRQB", 0x0B4B, 12, 0x000 );
111 fRegs[kIA2IRQC] = SimpleReg_t("IA2IRQC", 0x0B4C, 12, 0x000 );
112 fRegs[kIRQSW2] = SimpleReg_t("IRQSW2", 0x0B4D, 13, 0x1FFF );
113 fRegs[kIRQHW2] = SimpleReg_t("IRQHW2", 0x0B4E, 13, 0x0000 );
114 fRegs[kIRQHL2] = SimpleReg_t("IRQHL2", 0x0B4F, 13, 0x0000 );
115 fRegs[kIA3IRQ0] = SimpleReg_t("IA3IRQ0", 0x0B60, 12, 0x000 ); // IVT of CPU3
116 fRegs[kIA3IRQ1] = SimpleReg_t("IA3IRQ1", 0x0B61, 12, 0x000 );
117 fRegs[kIA3IRQ2] = SimpleReg_t("IA3IRQ2", 0x0B62, 12, 0x000 );
118 fRegs[kIA3IRQ3] = SimpleReg_t("IA3IRQ3", 0x0B63, 12, 0x000 );
119 fRegs[kIA3IRQ4] = SimpleReg_t("IA3IRQ4", 0x0B64, 12, 0x000 );
120 fRegs[kIA3IRQ5] = SimpleReg_t("IA3IRQ5", 0x0B65, 12, 0x000 );
121 fRegs[kIA3IRQ6] = SimpleReg_t("IA3IRQ6", 0x0B66, 12, 0x000 );
122 fRegs[kIA3IRQ7] = SimpleReg_t("IA3IRQ7", 0x0B67, 12, 0x000 );
123 fRegs[kIA3IRQ8] = SimpleReg_t("IA3IRQ8", 0x0B68, 12, 0x000 );
124 fRegs[kIA3IRQ9] = SimpleReg_t("IA3IRQ9", 0x0B69, 12, 0x000 );
125 fRegs[kIA3IRQA] = SimpleReg_t("IA3IRQA", 0x0B6A, 12, 0x000 );
126 fRegs[kIA3IRQB] = SimpleReg_t("IA3IRQB", 0x0B6B, 12, 0x000 );
127 fRegs[kIA3IRQC] = SimpleReg_t("IA3IRQC", 0x0B6C, 12, 0x000 );
128 fRegs[kIRQSW3] = SimpleReg_t("IRQSW3", 0x0B6D, 13, 0x1FFF );
129 fRegs[kIRQHW3] = SimpleReg_t("IRQHW3", 0x0B6E, 13, 0x0000 );
130 fRegs[kIRQHL3] = SimpleReg_t("IRQHL3", 0x0B6F, 13, 0x0000 );
131 fRegs[kCTGDINI] = SimpleReg_t("CTGDINI", 0x0B80, 32, 0x00000000 ); // Global Counter/Timer
132 fRegs[kCTGCTRL] = SimpleReg_t("CTGCTRL", 0x0B81, 12, 0xE3F );
133 fRegs[kC08CPU0] = SimpleReg_t("C08CPU0", 0x0C00, 32, 0x00000000 ); // CPU constants
134 fRegs[kC09CPU0] = SimpleReg_t("C09CPU0", 0x0C01, 32, 0x00000000 );
135 fRegs[kC10CPU0] = SimpleReg_t("C10CPU0", 0x0C02, 32, 0x00000000 );
136 fRegs[kC11CPU0] = SimpleReg_t("C11CPU0", 0x0C03, 32, 0x00000000 );
137 fRegs[kC12CPUA] = SimpleReg_t("C12CPUA", 0x0C04, 32, 0x00000000 );
138 fRegs[kC13CPUA] = SimpleReg_t("C13CPUA", 0x0C05, 32, 0x00000000 );
139 fRegs[kC14CPUA] = SimpleReg_t("C14CPUA", 0x0C06, 32, 0x00000000 );
140 fRegs[kC15CPUA] = SimpleReg_t("C15CPUA", 0x0C07, 32, 0x00000000 );
141 fRegs[kC08CPU1] = SimpleReg_t("C08CPU1", 0x0C08, 32, 0x00000000 );
142 fRegs[kC09CPU1] = SimpleReg_t("C09CPU1", 0x0C09, 32, 0x00000000 );
143 fRegs[kC10CPU1] = SimpleReg_t("C10CPU1", 0x0C0A, 32, 0x00000000 );
144 fRegs[kC11CPU1] = SimpleReg_t("C11CPU1", 0x0C0B, 32, 0x00000000 );
145 fRegs[kC08CPU2] = SimpleReg_t("C08CPU2", 0x0C10, 32, 0x00000000 );
146 fRegs[kC09CPU2] = SimpleReg_t("C09CPU2", 0x0C11, 32, 0x00000000 );
147 fRegs[kC10CPU2] = SimpleReg_t("C10CPU2", 0x0C12, 32, 0x00000000 );
148 fRegs[kC11CPU2] = SimpleReg_t("C11CPU2", 0x0C13, 32, 0x00000000 );
149 fRegs[kC08CPU3] = SimpleReg_t("C08CPU3", 0x0C18, 32, 0x00000000 );
150 fRegs[kC09CPU3] = SimpleReg_t("C09CPU3", 0x0C19, 32, 0x00000000 );
151 fRegs[kC10CPU3] = SimpleReg_t("C10CPU3", 0x0C1A, 32, 0x00000000 );
152 fRegs[kC11CPU3] = SimpleReg_t("C11CPU3", 0x0C1B, 32, 0x00000000 );
153 fRegs[kNMOD] = SimpleReg_t("NMOD", 0x0D40, 6, 0x08 ); // NI interface
154 fRegs[kNDLY] = SimpleReg_t("NDLY", 0x0D41, 30, 0x24924924 );
155 fRegs[kNED] = SimpleReg_t("NED", 0x0D42, 16, 0xA240 );
156 fRegs[kNTRO] = SimpleReg_t("NTRO", 0x0D43, 18, 0x3FFFC );
157 fRegs[kNRRO] = SimpleReg_t("NRRO", 0x0D44, 18, 0x3FFFC );
158 fRegs[kNES] = SimpleReg_t("NES", 0x0D45, 32, 0x00000000 );
159 fRegs[kNTP] = SimpleReg_t("NTP", 0x0D46, 32, 0x0000FFFF );
160 fRegs[kNBND] = SimpleReg_t("NBND", 0x0D47, 16, 0x6020 );
161 fRegs[kNP0] = SimpleReg_t("NP0", 0x0D48, 11, 0x44C );
162 fRegs[kNP1] = SimpleReg_t("NP1", 0x0D49, 11, 0x44C );
163 fRegs[kNP2] = SimpleReg_t("NP2", 0x0D4A, 11, 0x44C );
164 fRegs[kNP3] = SimpleReg_t("NP3", 0x0D4B, 11, 0x44C );
165 fRegs[kNCUT] = SimpleReg_t("NCUT", 0x0D4C, 32, 0xFFFFFFFF );
166 fRegs[kTPPT0] = SimpleReg_t("TPPT0", 0x3000, 7, 0x01 ); // Filter and Preprocessor
167 fRegs[kTPFS] = SimpleReg_t("TPFS", 0x3001, 7, 0x05 );
168 fRegs[kTPFE] = SimpleReg_t("TPFE", 0x3002, 7, 0x14 );
169 fRegs[kTPPGR] = SimpleReg_t("TPPGR", 0x3003, 7, 0x15 );
170 fRegs[kTPPAE] = SimpleReg_t("TPPAE", 0x3004, 7, 0x1E );
171 fRegs[kTPQS0] = SimpleReg_t("TPQS0", 0x3005, 7, 0x00 );
172 fRegs[kTPQE0] = SimpleReg_t("TPQE0", 0x3006, 7, 0x0A );
173 fRegs[kTPQS1] = SimpleReg_t("TPQS1", 0x3007, 7, 0x0B );
174 fRegs[kTPQE1] = SimpleReg_t("TPQE1", 0x3008, 7, 0x14 );
175 fRegs[kEBD] = SimpleReg_t("EBD", 0x3009, 3, 0x0 );
176 fRegs[kEBAQA] = SimpleReg_t("EBAQA", 0x300A, 7, 0x00 );
177 fRegs[kEBSIA] = SimpleReg_t("EBSIA", 0x300B, 7, 0x20 );
178 fRegs[kEBSF] = SimpleReg_t("EBSF", 0x300C, 1, 0x1 );
179 fRegs[kEBSIM] = SimpleReg_t("EBSIM", 0x300D, 1, 0x1 );
180 fRegs[kEBPP] = SimpleReg_t("EBPP", 0x300E, 1, 0x1 );
181 fRegs[kEBPC] = SimpleReg_t("EBPC", 0x300F, 1, 0x1 );
182 fRegs[kEBIS] = SimpleReg_t("EBIS", 0x3014, 10, 0x005 );
183 fRegs[kEBIT] = SimpleReg_t("EBIT", 0x3015, 12, 0x028 );
184 fRegs[kEBIL] = SimpleReg_t("EBIL", 0x3016, 8, 0xF0 );
185 fRegs[kEBIN] = SimpleReg_t("EBIN", 0x3017, 1, 0x1 );
186 fRegs[kFLBY] = SimpleReg_t("FLBY", 0x3018, 1, 0x0 );
187 fRegs[kFPBY] = SimpleReg_t("FPBY", 0x3019, 1, 0x0 );
188 fRegs[kFGBY] = SimpleReg_t("FGBY", 0x301A, 1, 0x0 );
189 fRegs[kFTBY] = SimpleReg_t("FTBY", 0x301B, 1, 0x0 );
190 fRegs[kFCBY] = SimpleReg_t("FCBY", 0x301C, 1, 0x0 );
191 fRegs[kFPTC] = SimpleReg_t("FPTC", 0x3020, 2, 0x3 );
192 fRegs[kFPNP] = SimpleReg_t("FPNP", 0x3021, 9, 0x078 );
193 fRegs[kFPCL] = SimpleReg_t("FPCL", 0x3022, 1, 0x1 );
194 fRegs[kFGTA] = SimpleReg_t("FGTA", 0x3028, 12, 0x014 );
195 fRegs[kFGTB] = SimpleReg_t("FGTB", 0x3029, 12, 0x80C );
196 fRegs[kFGCL] = SimpleReg_t("FGCL", 0x302A, 1, 0x1 );
197 fRegs[kFTAL] = SimpleReg_t("FTAL", 0x3030, 10, 0x0F6 );
198 fRegs[kFTLL] = SimpleReg_t("FTLL", 0x3031, 9, 0x11D );
199 fRegs[kFTLS] = SimpleReg_t("FTLS", 0x3032, 9, 0x0D3 );
200 fRegs[kFCW1] = SimpleReg_t("FCW1", 0x3038, 8, 0x1E );
201 fRegs[kFCW2] = SimpleReg_t("FCW2", 0x3039, 8, 0xD4 );
202 fRegs[kFCW3] = SimpleReg_t("FCW3", 0x303A, 8, 0xE6 );
203 fRegs[kFCW4] = SimpleReg_t("FCW4", 0x303B, 8, 0x4A );
204 fRegs[kFCW5] = SimpleReg_t("FCW5", 0x303C, 8, 0xEF );
205 fRegs[kTPFP] = SimpleReg_t("TPFP", 0x3040, 9, 0x037 );
206 fRegs[kTPHT] = SimpleReg_t("TPHT", 0x3041, 14, 0x00A0 );
207 fRegs[kTPVT] = SimpleReg_t("TPVT", 0x3042, 6, 0x00 );
208 fRegs[kTPVBY] = SimpleReg_t("TPVBY", 0x3043, 1, 0x0 );
209 fRegs[kTPCT] = SimpleReg_t("TPCT", 0x3044, 5, 0x08 );
210 fRegs[kTPCL] = SimpleReg_t("TPCL", 0x3045, 5, 0x01 );
211 fRegs[kTPCBY] = SimpleReg_t("TPCBY", 0x3046, 1, 0x1 );
212 fRegs[kTPD] = SimpleReg_t("TPD", 0x3047, 4, 0xF );
213 fRegs[kTPCI0] = SimpleReg_t("TPCI0", 0x3048, 5, 0x00 );
214 fRegs[kTPCI1] = SimpleReg_t("TPCI1", 0x3049, 5, 0x00 );
215 fRegs[kTPCI2] = SimpleReg_t("TPCI2", 0x304A, 5, 0x00 );
216 fRegs[kTPCI3] = SimpleReg_t("TPCI3", 0x304B, 5, 0x00 );
217 fRegs[kADCMSK] = SimpleReg_t("ADCMSK", 0x3050, 21, 0x1FFFFF );
218 fRegs[kADCINB] = SimpleReg_t("ADCINB", 0x3051, 2, 0x2 );
219 fRegs[kADCDAC] = SimpleReg_t("ADCDAC", 0x3052, 5, 0x10 );
220 fRegs[kADCPAR] = SimpleReg_t("ADCPAR", 0x3053, 18, 0x195EF );
221 fRegs[kADCTST] = SimpleReg_t("ADCTST", 0x3054, 2, 0x0 );
222 fRegs[kSADCAZ] = SimpleReg_t("SADCAZ", 0x3055, 1, 0x1 );
223 fRegs[kFGF0] = SimpleReg_t("FGF0", 0x3080, 9, 0x000 );
224 fRegs[kFGF1] = SimpleReg_t("FGF1", 0x3081, 9, 0x000 );
225 fRegs[kFGF2] = SimpleReg_t("FGF2", 0x3082, 9, 0x000 );
226 fRegs[kFGF3] = SimpleReg_t("FGF3", 0x3083, 9, 0x000 );
227 fRegs[kFGF4] = SimpleReg_t("FGF4", 0x3084, 9, 0x000 );
228 fRegs[kFGF5] = SimpleReg_t("FGF5", 0x3085, 9, 0x000 );
229 fRegs[kFGF6] = SimpleReg_t("FGF6", 0x3086, 9, 0x000 );
230 fRegs[kFGF7] = SimpleReg_t("FGF7", 0x3087, 9, 0x000 );
231 fRegs[kFGF8] = SimpleReg_t("FGF8", 0x3088, 9, 0x000 );
232 fRegs[kFGF9] = SimpleReg_t("FGF9", 0x3089, 9, 0x000 );
233 fRegs[kFGF10] = SimpleReg_t("FGF10", 0x308A, 9, 0x000 );
234 fRegs[kFGF11] = SimpleReg_t("FGF11", 0x308B, 9, 0x000 );
235 fRegs[kFGF12] = SimpleReg_t("FGF12", 0x308C, 9, 0x000 );
236 fRegs[kFGF13] = SimpleReg_t("FGF13", 0x308D, 9, 0x000 );
237 fRegs[kFGF14] = SimpleReg_t("FGF14", 0x308E, 9, 0x000 );
238 fRegs[kFGF15] = SimpleReg_t("FGF15", 0x308F, 9, 0x000 );
239 fRegs[kFGF16] = SimpleReg_t("FGF16", 0x3090, 9, 0x000 );
240 fRegs[kFGF17] = SimpleReg_t("FGF17", 0x3091, 9, 0x000 );
241 fRegs[kFGF18] = SimpleReg_t("FGF18", 0x3092, 9, 0x000 );
242 fRegs[kFGF19] = SimpleReg_t("FGF19", 0x3093, 9, 0x000 );
243 fRegs[kFGF20] = SimpleReg_t("FGF20", 0x3094, 9, 0x000 );
244 fRegs[kFGA0] = SimpleReg_t("FGA0", 0x30A0, 6, 0x00 );
245 fRegs[kFGA1] = SimpleReg_t("FGA1", 0x30A1, 6, 0x00 );
246 fRegs[kFGA2] = SimpleReg_t("FGA2", 0x30A2, 6, 0x00 );
247 fRegs[kFGA3] = SimpleReg_t("FGA3", 0x30A3, 6, 0x00 );
248 fRegs[kFGA4] = SimpleReg_t("FGA4", 0x30A4, 6, 0x00 );
249 fRegs[kFGA5] = SimpleReg_t("FGA5", 0x30A5, 6, 0x00 );
250 fRegs[kFGA6] = SimpleReg_t("FGA6", 0x30A6, 6, 0x00 );
251 fRegs[kFGA7] = SimpleReg_t("FGA7", 0x30A7, 6, 0x00 );
252 fRegs[kFGA8] = SimpleReg_t("FGA8", 0x30A8, 6, 0x00 );
253 fRegs[kFGA9] = SimpleReg_t("FGA9", 0x30A9, 6, 0x00 );
254 fRegs[kFGA10] = SimpleReg_t("FGA10", 0x30AA, 6, 0x00 );
255 fRegs[kFGA11] = SimpleReg_t("FGA11", 0x30AB, 6, 0x00 );
256 fRegs[kFGA12] = SimpleReg_t("FGA12", 0x30AC, 6, 0x00 );
257 fRegs[kFGA13] = SimpleReg_t("FGA13", 0x30AD, 6, 0x00 );
258 fRegs[kFGA14] = SimpleReg_t("FGA14", 0x30AE, 6, 0x00 );
259 fRegs[kFGA15] = SimpleReg_t("FGA15", 0x30AF, 6, 0x00 );
260 fRegs[kFGA16] = SimpleReg_t("FGA16", 0x30B0, 6, 0x00 );
261 fRegs[kFGA17] = SimpleReg_t("FGA17", 0x30B1, 6, 0x00 );
262 fRegs[kFGA18] = SimpleReg_t("FGA18", 0x30B2, 6, 0x00 );
263 fRegs[kFGA19] = SimpleReg_t("FGA19", 0x30B3, 6, 0x00 );
264 fRegs[kFGA20] = SimpleReg_t("FGA20", 0x30B4, 6, 0x00 );
265 fRegs[kFLL00] = SimpleReg_t("FLL00", 0x3100, 6, 0x00 ); // non-linearity table, 64 x 6 bits
266 fRegs[kFLL01] = SimpleReg_t("FLL01", 0x3101, 6, 0x00 );
267 fRegs[kFLL02] = SimpleReg_t("FLL02", 0x3102, 6, 0x00 );
268 fRegs[kFLL03] = SimpleReg_t("FLL03", 0x3103, 6, 0x00 );
269 fRegs[kFLL04] = SimpleReg_t("FLL04", 0x3104, 6, 0x00 );
270 fRegs[kFLL05] = SimpleReg_t("FLL05", 0x3105, 6, 0x00 );
271 fRegs[kFLL06] = SimpleReg_t("FLL06", 0x3106, 6, 0x00 );
272 fRegs[kFLL07] = SimpleReg_t("FLL07", 0x3107, 6, 0x00 );
273 fRegs[kFLL08] = SimpleReg_t("FLL08", 0x3108, 6, 0x00 );
274 fRegs[kFLL09] = SimpleReg_t("FLL09", 0x3109, 6, 0x00 );
275 fRegs[kFLL0A] = SimpleReg_t("FLL0A", 0x310A, 6, 0x00 );
276 fRegs[kFLL0B] = SimpleReg_t("FLL0B", 0x310B, 6, 0x00 );
277 fRegs[kFLL0C] = SimpleReg_t("FLL0C", 0x310C, 6, 0x00 );
278 fRegs[kFLL0D] = SimpleReg_t("FLL0D", 0x310D, 6, 0x00 );
279 fRegs[kFLL0E] = SimpleReg_t("FLL0E", 0x310E, 6, 0x00 );
280 fRegs[kFLL0F] = SimpleReg_t("FLL0F", 0x310F, 6, 0x00 );
281 fRegs[kFLL10] = SimpleReg_t("FLL10", 0x3110, 6, 0x00 );
282 fRegs[kFLL11] = SimpleReg_t("FLL11", 0x3111, 6, 0x00 );
283 fRegs[kFLL12] = SimpleReg_t("FLL12", 0x3112, 6, 0x00 );
284 fRegs[kFLL13] = SimpleReg_t("FLL13", 0x3113, 6, 0x00 );
285 fRegs[kFLL14] = SimpleReg_t("FLL14", 0x3114, 6, 0x00 );
286 fRegs[kFLL15] = SimpleReg_t("FLL15", 0x3115, 6, 0x00 );
287 fRegs[kFLL16] = SimpleReg_t("FLL16", 0x3116, 6, 0x00 );
288 fRegs[kFLL17] = SimpleReg_t("FLL17", 0x3117, 6, 0x00 );
289 fRegs[kFLL18] = SimpleReg_t("FLL18", 0x3118, 6, 0x00 );
290 fRegs[kFLL19] = SimpleReg_t("FLL19", 0x3119, 6, 0x00 );
291 fRegs[kFLL1A] = SimpleReg_t("FLL1A", 0x311A, 6, 0x00 );
292 fRegs[kFLL1B] = SimpleReg_t("FLL1B", 0x311B, 6, 0x00 );
293 fRegs[kFLL1C] = SimpleReg_t("FLL1C", 0x311C, 6, 0x00 );
294 fRegs[kFLL1D] = SimpleReg_t("FLL1D", 0x311D, 6, 0x00 );
295 fRegs[kFLL1E] = SimpleReg_t("FLL1E", 0x311E, 6, 0x00 );
296 fRegs[kFLL1F] = SimpleReg_t("FLL1F", 0x311F, 6, 0x00 );
297 fRegs[kFLL20] = SimpleReg_t("FLL20", 0x3120, 6, 0x00 );
298 fRegs[kFLL21] = SimpleReg_t("FLL21", 0x3121, 6, 0x00 );
299 fRegs[kFLL22] = SimpleReg_t("FLL22", 0x3122, 6, 0x00 );
300 fRegs[kFLL23] = SimpleReg_t("FLL23", 0x3123, 6, 0x00 );
301 fRegs[kFLL24] = SimpleReg_t("FLL24", 0x3124, 6, 0x00 );
302 fRegs[kFLL25] = SimpleReg_t("FLL25", 0x3125, 6, 0x00 );
303 fRegs[kFLL26] = SimpleReg_t("FLL26", 0x3126, 6, 0x00 );
304 fRegs[kFLL27] = SimpleReg_t("FLL27", 0x3127, 6, 0x00 );
305 fRegs[kFLL28] = SimpleReg_t("FLL28", 0x3128, 6, 0x00 );
306 fRegs[kFLL29] = SimpleReg_t("FLL29", 0x3129, 6, 0x00 );
307 fRegs[kFLL2A] = SimpleReg_t("FLL2A", 0x312A, 6, 0x00 );
308 fRegs[kFLL2B] = SimpleReg_t("FLL2B", 0x312B, 6, 0x00 );
309 fRegs[kFLL2C] = SimpleReg_t("FLL2C", 0x312C, 6, 0x00 );
310 fRegs[kFLL2D] = SimpleReg_t("FLL2D", 0x312D, 6, 0x00 );
311 fRegs[kFLL2E] = SimpleReg_t("FLL2E", 0x312E, 6, 0x00 );
312 fRegs[kFLL2F] = SimpleReg_t("FLL2F", 0x312F, 6, 0x00 );
313 fRegs[kFLL30] = SimpleReg_t("FLL30", 0x3130, 6, 0x00 );
314 fRegs[kFLL31] = SimpleReg_t("FLL31", 0x3131, 6, 0x00 );
315 fRegs[kFLL32] = SimpleReg_t("FLL32", 0x3132, 6, 0x00 );
316 fRegs[kFLL33] = SimpleReg_t("FLL33", 0x3133, 6, 0x00 );
317 fRegs[kFLL34] = SimpleReg_t("FLL34", 0x3134, 6, 0x00 );
318 fRegs[kFLL35] = SimpleReg_t("FLL35", 0x3135, 6, 0x00 );
319 fRegs[kFLL36] = SimpleReg_t("FLL36", 0x3136, 6, 0x00 );
320 fRegs[kFLL37] = SimpleReg_t("FLL37", 0x3137, 6, 0x00 );
321 fRegs[kFLL38] = SimpleReg_t("FLL38", 0x3138, 6, 0x00 );
322 fRegs[kFLL39] = SimpleReg_t("FLL39", 0x3139, 6, 0x00 );
323 fRegs[kFLL3A] = SimpleReg_t("FLL3A", 0x313A, 6, 0x00 );
324 fRegs[kFLL3B] = SimpleReg_t("FLL3B", 0x313B, 6, 0x00 );
325 fRegs[kFLL3C] = SimpleReg_t("FLL3C", 0x313C, 6, 0x00 );
326 fRegs[kFLL3D] = SimpleReg_t("FLL3D", 0x313D, 6, 0x00 );
327 fRegs[kFLL3E] = SimpleReg_t("FLL3E", 0x313E, 6, 0x00 );
328 fRegs[kFLL3F] = SimpleReg_t("FLL3F", 0x313F, 6, 0x00 );
329 fRegs[kPASADEL] = SimpleReg_t("PASADEL", 0x3158, 8, 0xFF ); // end of non-lin table
330 fRegs[kPASAPHA] = SimpleReg_t("PASAPHA", 0x3159, 6, 0x3F );
331 fRegs[kPASAPRA] = SimpleReg_t("PASAPRA", 0x315A, 6, 0x0F );
332 fRegs[kPASADAC] = SimpleReg_t("PASADAC", 0x315B, 8, 0x80 );
333 fRegs[kPASACHM] = SimpleReg_t("PASACHM", 0x315C, 19, 0x7FFFF );
334 fRegs[kPASASTL] = SimpleReg_t("PASASTL", 0x315D, 8, 0xFF );
335 fRegs[kPASAPR1] = SimpleReg_t("PASAPR1", 0x315E, 1, 0x0 );
336 fRegs[kPASAPR0] = SimpleReg_t("PASAPR0", 0x315F, 1, 0x0 );
337 fRegs[kSADCTRG] = SimpleReg_t("SADCTRG", 0x3161, 1, 0x0 );
338 fRegs[kSADCRUN] = SimpleReg_t("SADCRUN", 0x3162, 1, 0x0 );
339 fRegs[kSADCPWR] = SimpleReg_t("SADCPWR", 0x3163, 3, 0x7 );
340 fRegs[kL0TSIM] = SimpleReg_t("L0TSIM", 0x3165, 14, 0x0050 );
341 fRegs[kSADCEC] = SimpleReg_t("SADCEC", 0x3166, 7, 0x00 );
342 fRegs[kSADCMC] = SimpleReg_t("SADCMC", 0x3170, 8, 0xC0 );
343 fRegs[kSADCOC] = SimpleReg_t("SADCOC", 0x3171, 8, 0x19 );
344 fRegs[kSADCGTB] = SimpleReg_t("SADCGTB", 0x3172, 32, 0x37737700 );
345 fRegs[kSEBDEN] = SimpleReg_t("SEBDEN", 0x3178, 3, 0x0 );
346 fRegs[kSEBDOU] = SimpleReg_t("SEBDOU", 0x3179, 3, 0x0 );
347 fRegs[kTPL00] = SimpleReg_t("TPL00", 0x3180, 5, 0x00 ); // pos table, 128 x 5 bits
348 fRegs[kTPL01] = SimpleReg_t("TPL01", 0x3181, 5, 0x00 );
349 fRegs[kTPL02] = SimpleReg_t("TPL02", 0x3182, 5, 0x00 );
350 fRegs[kTPL03] = SimpleReg_t("TPL03", 0x3183, 5, 0x00 );
351 fRegs[kTPL04] = SimpleReg_t("TPL04", 0x3184, 5, 0x00 );
352 fRegs[kTPL05] = SimpleReg_t("TPL05", 0x3185, 5, 0x00 );
353 fRegs[kTPL06] = SimpleReg_t("TPL06", 0x3186, 5, 0x00 );
354 fRegs[kTPL07] = SimpleReg_t("TPL07", 0x3187, 5, 0x00 );
355 fRegs[kTPL08] = SimpleReg_t("TPL08", 0x3188, 5, 0x00 );
356 fRegs[kTPL09] = SimpleReg_t("TPL09", 0x3189, 5, 0x00 );
357 fRegs[kTPL0A] = SimpleReg_t("TPL0A", 0x318A, 5, 0x00 );
358 fRegs[kTPL0B] = SimpleReg_t("TPL0B", 0x318B, 5, 0x00 );
359 fRegs[kTPL0C] = SimpleReg_t("TPL0C", 0x318C, 5, 0x00 );
360 fRegs[kTPL0D] = SimpleReg_t("TPL0D", 0x318D, 5, 0x00 );
361 fRegs[kTPL0E] = SimpleReg_t("TPL0E", 0x318E, 5, 0x00 );
362 fRegs[kTPL0F] = SimpleReg_t("TPL0F", 0x318F, 5, 0x00 );
363 fRegs[kTPL10] = SimpleReg_t("TPL10", 0x3190, 5, 0x00 );
364 fRegs[kTPL11] = SimpleReg_t("TPL11", 0x3191, 5, 0x00 );
365 fRegs[kTPL12] = SimpleReg_t("TPL12", 0x3192, 5, 0x00 );
366 fRegs[kTPL13] = SimpleReg_t("TPL13", 0x3193, 5, 0x00 );
367 fRegs[kTPL14] = SimpleReg_t("TPL14", 0x3194, 5, 0x00 );
368 fRegs[kTPL15] = SimpleReg_t("TPL15", 0x3195, 5, 0x00 );
369 fRegs[kTPL16] = SimpleReg_t("TPL16", 0x3196, 5, 0x00 );
370 fRegs[kTPL17] = SimpleReg_t("TPL17", 0x3197, 5, 0x00 );
371 fRegs[kTPL18] = SimpleReg_t("TPL18", 0x3198, 5, 0x00 );
372 fRegs[kTPL19] = SimpleReg_t("TPL19", 0x3199, 5, 0x00 );
373 fRegs[kTPL1A] = SimpleReg_t("TPL1A", 0x319A, 5, 0x00 );
374 fRegs[kTPL1B] = SimpleReg_t("TPL1B", 0x319B, 5, 0x00 );
375 fRegs[kTPL1C] = SimpleReg_t("TPL1C", 0x319C, 5, 0x00 );
376 fRegs[kTPL1D] = SimpleReg_t("TPL1D", 0x319D, 5, 0x00 );
377 fRegs[kTPL1E] = SimpleReg_t("TPL1E", 0x319E, 5, 0x00 );
378 fRegs[kTPL1F] = SimpleReg_t("TPL1F", 0x319F, 5, 0x00 );
379 fRegs[kTPL20] = SimpleReg_t("TPL20", 0x31A0, 5, 0x00 );
380 fRegs[kTPL21] = SimpleReg_t("TPL21", 0x31A1, 5, 0x00 );
381 fRegs[kTPL22] = SimpleReg_t("TPL22", 0x31A2, 5, 0x00 );
382 fRegs[kTPL23] = SimpleReg_t("TPL23", 0x31A3, 5, 0x00 );
383 fRegs[kTPL24] = SimpleReg_t("TPL24", 0x31A4, 5, 0x00 );
384 fRegs[kTPL25] = SimpleReg_t("TPL25", 0x31A5, 5, 0x00 );
385 fRegs[kTPL26] = SimpleReg_t("TPL26", 0x31A6, 5, 0x00 );
386 fRegs[kTPL27] = SimpleReg_t("TPL27", 0x31A7, 5, 0x00 );
387 fRegs[kTPL28] = SimpleReg_t("TPL28", 0x31A8, 5, 0x00 );
388 fRegs[kTPL29] = SimpleReg_t("TPL29", 0x31A9, 5, 0x00 );
389 fRegs[kTPL2A] = SimpleReg_t("TPL2A", 0x31AA, 5, 0x00 );
390 fRegs[kTPL2B] = SimpleReg_t("TPL2B", 0x31AB, 5, 0x00 );
391 fRegs[kTPL2C] = SimpleReg_t("TPL2C", 0x31AC, 5, 0x00 );
392 fRegs[kTPL2D] = SimpleReg_t("TPL2D", 0x31AD, 5, 0x00 );
393 fRegs[kTPL2E] = SimpleReg_t("TPL2E", 0x31AE, 5, 0x00 );
394 fRegs[kTPL2F] = SimpleReg_t("TPL2F", 0x31AF, 5, 0x00 );
395 fRegs[kTPL30] = SimpleReg_t("TPL30", 0x31B0, 5, 0x00 );
396 fRegs[kTPL31] = SimpleReg_t("TPL31", 0x31B1, 5, 0x00 );
397 fRegs[kTPL32] = SimpleReg_t("TPL32", 0x31B2, 5, 0x00 );
398 fRegs[kTPL33] = SimpleReg_t("TPL33", 0x31B3, 5, 0x00 );
399 fRegs[kTPL34] = SimpleReg_t("TPL34", 0x31B4, 5, 0x00 );
400 fRegs[kTPL35] = SimpleReg_t("TPL35", 0x31B5, 5, 0x00 );
401 fRegs[kTPL36] = SimpleReg_t("TPL36", 0x31B6, 5, 0x00 );
402 fRegs[kTPL37] = SimpleReg_t("TPL37", 0x31B7, 5, 0x00 );
403 fRegs[kTPL38] = SimpleReg_t("TPL38", 0x31B8, 5, 0x00 );
404 fRegs[kTPL39] = SimpleReg_t("TPL39", 0x31B9, 5, 0x00 );
405 fRegs[kTPL3A] = SimpleReg_t("TPL3A", 0x31BA, 5, 0x00 );
406 fRegs[kTPL3B] = SimpleReg_t("TPL3B", 0x31BB, 5, 0x00 );
407 fRegs[kTPL3C] = SimpleReg_t("TPL3C", 0x31BC, 5, 0x00 );
408 fRegs[kTPL3D] = SimpleReg_t("TPL3D", 0x31BD, 5, 0x00 );
409 fRegs[kTPL3E] = SimpleReg_t("TPL3E", 0x31BE, 5, 0x00 );
410 fRegs[kTPL3F] = SimpleReg_t("TPL3F", 0x31BF, 5, 0x00 );
411 fRegs[kTPL40] = SimpleReg_t("TPL40", 0x31C0, 5, 0x00 );
412 fRegs[kTPL41] = SimpleReg_t("TPL41", 0x31C1, 5, 0x00 );
413 fRegs[kTPL42] = SimpleReg_t("TPL42", 0x31C2, 5, 0x00 );
414 fRegs[kTPL43] = SimpleReg_t("TPL43", 0x31C3, 5, 0x00 );
415 fRegs[kTPL44] = SimpleReg_t("TPL44", 0x31C4, 5, 0x00 );
416 fRegs[kTPL45] = SimpleReg_t("TPL45", 0x31C5, 5, 0x00 );
417 fRegs[kTPL46] = SimpleReg_t("TPL46", 0x31C6, 5, 0x00 );
418 fRegs[kTPL47] = SimpleReg_t("TPL47", 0x31C7, 5, 0x00 );
419 fRegs[kTPL48] = SimpleReg_t("TPL48", 0x31C8, 5, 0x00 );
420 fRegs[kTPL49] = SimpleReg_t("TPL49", 0x31C9, 5, 0x00 );
421 fRegs[kTPL4A] = SimpleReg_t("TPL4A", 0x31CA, 5, 0x00 );
422 fRegs[kTPL4B] = SimpleReg_t("TPL4B", 0x31CB, 5, 0x00 );
423 fRegs[kTPL4C] = SimpleReg_t("TPL4C", 0x31CC, 5, 0x00 );
424 fRegs[kTPL4D] = SimpleReg_t("TPL4D", 0x31CD, 5, 0x00 );
425 fRegs[kTPL4E] = SimpleReg_t("TPL4E", 0x31CE, 5, 0x00 );
426 fRegs[kTPL4F] = SimpleReg_t("TPL4F", 0x31CF, 5, 0x00 );
427 fRegs[kTPL50] = SimpleReg_t("TPL50", 0x31D0, 5, 0x00 );
428 fRegs[kTPL51] = SimpleReg_t("TPL51", 0x31D1, 5, 0x00 );
429 fRegs[kTPL52] = SimpleReg_t("TPL52", 0x31D2, 5, 0x00 );
430 fRegs[kTPL53] = SimpleReg_t("TPL53", 0x31D3, 5, 0x00 );
431 fRegs[kTPL54] = SimpleReg_t("TPL54", 0x31D4, 5, 0x00 );
432 fRegs[kTPL55] = SimpleReg_t("TPL55", 0x31D5, 5, 0x00 );
433 fRegs[kTPL56] = SimpleReg_t("TPL56", 0x31D6, 5, 0x00 );
434 fRegs[kTPL57] = SimpleReg_t("TPL57", 0x31D7, 5, 0x00 );
435 fRegs[kTPL58] = SimpleReg_t("TPL58", 0x31D8, 5, 0x00 );
436 fRegs[kTPL59] = SimpleReg_t("TPL59", 0x31D9, 5, 0x00 );
437 fRegs[kTPL5A] = SimpleReg_t("TPL5A", 0x31DA, 5, 0x00 );
438 fRegs[kTPL5B] = SimpleReg_t("TPL5B", 0x31DB, 5, 0x00 );
439 fRegs[kTPL5C] = SimpleReg_t("TPL5C", 0x31DC, 5, 0x00 );
440 fRegs[kTPL5D] = SimpleReg_t("TPL5D", 0x31DD, 5, 0x00 );
441 fRegs[kTPL5E] = SimpleReg_t("TPL5E", 0x31DE, 5, 0x00 );
442 fRegs[kTPL5F] = SimpleReg_t("TPL5F", 0x31DF, 5, 0x00 );
443 fRegs[kTPL60] = SimpleReg_t("TPL60", 0x31E0, 5, 0x00 );
444 fRegs[kTPL61] = SimpleReg_t("TPL61", 0x31E1, 5, 0x00 );
445 fRegs[kTPL62] = SimpleReg_t("TPL62", 0x31E2, 5, 0x00 );
446 fRegs[kTPL63] = SimpleReg_t("TPL63", 0x31E3, 5, 0x00 );
447 fRegs[kTPL64] = SimpleReg_t("TPL64", 0x31E4, 5, 0x00 );
448 fRegs[kTPL65] = SimpleReg_t("TPL65", 0x31E5, 5, 0x00 );
449 fRegs[kTPL66] = SimpleReg_t("TPL66", 0x31E6, 5, 0x00 );
450 fRegs[kTPL67] = SimpleReg_t("TPL67", 0x31E7, 5, 0x00 );
451 fRegs[kTPL68] = SimpleReg_t("TPL68", 0x31E8, 5, 0x00 );
452 fRegs[kTPL69] = SimpleReg_t("TPL69", 0x31E9, 5, 0x00 );
453 fRegs[kTPL6A] = SimpleReg_t("TPL6A", 0x31EA, 5, 0x00 );
454 fRegs[kTPL6B] = SimpleReg_t("TPL6B", 0x31EB, 5, 0x00 );
455 fRegs[kTPL6C] = SimpleReg_t("TPL6C", 0x31EC, 5, 0x00 );
456 fRegs[kTPL6D] = SimpleReg_t("TPL6D", 0x31ED, 5, 0x00 );
457 fRegs[kTPL6E] = SimpleReg_t("TPL6E", 0x31EE, 5, 0x00 );
458 fRegs[kTPL6F] = SimpleReg_t("TPL6F", 0x31EF, 5, 0x00 );
459 fRegs[kTPL70] = SimpleReg_t("TPL70", 0x31F0, 5, 0x00 );
460 fRegs[kTPL71] = SimpleReg_t("TPL71", 0x31F1, 5, 0x00 );
461 fRegs[kTPL72] = SimpleReg_t("TPL72", 0x31F2, 5, 0x00 );
462 fRegs[kTPL73] = SimpleReg_t("TPL73", 0x31F3, 5, 0x00 );
463 fRegs[kTPL74] = SimpleReg_t("TPL74", 0x31F4, 5, 0x00 );
464 fRegs[kTPL75] = SimpleReg_t("TPL75", 0x31F5, 5, 0x00 );
465 fRegs[kTPL76] = SimpleReg_t("TPL76", 0x31F6, 5, 0x00 );
466 fRegs[kTPL77] = SimpleReg_t("TPL77", 0x31F7, 5, 0x00 );
467 fRegs[kTPL78] = SimpleReg_t("TPL78", 0x31F8, 5, 0x00 );
468 fRegs[kTPL79] = SimpleReg_t("TPL79", 0x31F9, 5, 0x00 );
469 fRegs[kTPL7A] = SimpleReg_t("TPL7A", 0x31FA, 5, 0x00 );
470 fRegs[kTPL7B] = SimpleReg_t("TPL7B", 0x31FB, 5, 0x00 );
471 fRegs[kTPL7C] = SimpleReg_t("TPL7C", 0x31FC, 5, 0x00 );
472 fRegs[kTPL7D] = SimpleReg_t("TPL7D", 0x31FD, 5, 0x00 );
473 fRegs[kTPL7E] = SimpleReg_t("TPL7E", 0x31FE, 5, 0x00 );
474 fRegs[kTPL7F] = SimpleReg_t("TPL7F", 0x31FF, 5, 0x00 );
475 fRegs[kMEMRW] = SimpleReg_t("MEMRW", 0xD000, 7, 0x79 ); // end of pos table
476 fRegs[kMEMCOR] = SimpleReg_t("MEMCOR", 0xD001, 9, 0x000 );
477 fRegs[kDMDELA] = SimpleReg_t("DMDELA", 0xD002, 4, 0x8 );
478 fRegs[kDMDELS] = SimpleReg_t("DMDELS", 0xD003, 4, 0x8 );
479
8ea391e3 480
481
482 for(Int_t iAddr = 0; iAddr < fgkDmemWords; iAddr++) {
483
484 if(iAddr == fgkDmemAddrDeflCorr - fgkDmemStartAddress) {
485 fDmem[iAddr] = new UInt_t[fgkDmemSizeSmIndividual];
486 fDmemDepth[iAddr] = fgkDmemSizeSmIndividual;
487 }
488
489 else if(iAddr == fgkDmemAddrNdrift - fgkDmemStartAddress) {
490 fDmem[iAddr] = new UInt_t[fgkDmemSizeSmRocIndividual];
491 fDmemDepth[iAddr] = fgkDmemSizeSmRocIndividual;
492 }
493
494 else if(iAddr >= fgkDmemAddrDeflCutStart-fgkDmemStartAddress && iAddr <= fgkDmemAddrDeflCutEnd-fgkDmemStartAddress) {
495 fDmem[iAddr] = new UInt_t[fgkDmemSizeSmIndividual];
496 fDmemDepth[iAddr] = fgkDmemSizeSmIndividual;
497 }
498
499 else if(iAddr >= fgkDmemAddrTrackletStart-fgkDmemStartAddress && iAddr <= fgkDmemAddrTrackletEnd-fgkDmemStartAddress) {
500 fDmem[iAddr] = new UInt_t[fgkDmemSizeTotalIndividual];
501 fDmemDepth[iAddr] = fgkDmemSizeTotalIndividual;
502 }
503
504 else if(iAddr >= fgkDmemAddrLUTStart-fgkDmemStartAddress && iAddr <= fgkDmemAddrLUTEnd-fgkDmemStartAddress) {
505 fDmem[iAddr] = new UInt_t; // same value for all MCMs
506 fDmemDepth[iAddr] = fgkDmemSizeUniform;
507 }
508
509 else if(iAddr == fgkDmemAddrLUTcor0-fgkDmemStartAddress) {
510 fDmem[iAddr] = new UInt_t[fgkDmemSizeSmIndividual];
511 fDmemDepth[iAddr] = fgkDmemSizeSmIndividual;
512 }
513
514 else if(iAddr == fgkDmemAddrLUTcor1-fgkDmemStartAddress) {
515 fDmem[iAddr] = new UInt_t[fgkDmemSizeSmIndividual];
516 fDmemDepth[iAddr] = fgkDmemSizeSmIndividual;
517 }
518
519 else if(iAddr == fgkDmemAddrLUTnbins-fgkDmemStartAddress) {
520 fDmem[iAddr] = new UInt_t; // same value for all MCMs
521 fDmemDepth[iAddr] = fgkDmemSizeUniform;
522 }
523
524 else if(iAddr == fgkDmemAddrLUTLength-fgkDmemStartAddress) {
525 fDmem[iAddr] = new UInt_t; // same value for all MCMs
526 fDmemDepth[iAddr] = fgkDmemSizeUniform;
527 }
528
529 else {
530 fDmem[iAddr] = NULL;
531 fDmemDepth[iAddr] = fgkDmemSizeEmpty;
532 }
533
051af255 534 }
535
ce4786b9 536 InitRegs();
8ea391e3 537 ResetDmem();
ce4786b9 538}
539
540
541AliTRDtrapConfig* AliTRDtrapConfig::Instance()
542{
543 // return a pointer to an instance of this class
544
545 if (!fgInstance) {
546 fgInstance = new AliTRDtrapConfig();
547 fgInstance->LoadConfig();
548 }
549
550 return fgInstance;
551}
552
553
051af255 554AliTRDtrapConfig::~AliTRDtrapConfig()
555{
8ea391e3 556 for(Int_t iAddr = 0; iAddr < fgkDmemWords; iAddr++) {
557 if(iAddr == fgkDmemAddrDeflCorr - fgkDmemStartAddress)
558 delete [] fDmem[iAddr];
559
560 else if(iAddr == fgkDmemAddrNdrift - fgkDmemStartAddress)
561 delete [] fDmem[iAddr];
562
563 else if(iAddr >= fgkDmemAddrDeflCutStart-fgkDmemStartAddress && iAddr <= fgkDmemAddrDeflCutEnd-fgkDmemStartAddress)
564 delete [] fDmem[iAddr];
565
566 else if(iAddr >= fgkDmemAddrTrackletStart-fgkDmemStartAddress && iAddr <= fgkDmemAddrTrackletEnd-fgkDmemStartAddress)
567 delete [] fDmem[iAddr];
568
569 else if(iAddr >= fgkDmemAddrLUTStart-fgkDmemStartAddress && iAddr <= fgkDmemAddrLUTEnd-fgkDmemStartAddress)
570 delete fDmem[iAddr];
571
572 else if(iAddr == fgkDmemAddrLUTcor0-fgkDmemStartAddress)
573 delete [] fDmem[iAddr];
574
575 else if(iAddr == fgkDmemAddrLUTcor1-fgkDmemStartAddress)
576 delete [] fDmem[iAddr];
577
578 else if(iAddr == fgkDmemAddrLUTnbins-fgkDmemStartAddress)
579 delete fDmem[iAddr];
580
581 else if(iAddr == fgkDmemAddrLUTLength-fgkDmemStartAddress)
582 delete fDmem[iAddr];
051af255 583 }
584}
585
586
8ea391e3 587void AliTRDtrapConfig::InitRegs()
ce4786b9 588{
589 // Reset the content of all TRAP registers to the reset values (see TRAP User Manual)
590
591 for (Int_t iReg = 0; iReg < kLastReg; iReg++) {
592
593 fRegisterValue[iReg].individualValue = 0x0;
594
595 fRegisterValue[iReg].globalValue = GetRegResetValue((TrapReg_t) iReg);
596 fRegisterValue[iReg].state = RegValue_t::kGlobal;
597 }
598}
599
600
8ea391e3 601void AliTRDtrapConfig::ResetRegs()
ce4786b9 602{
603 // Reset the content of all TRAP registers to the reset values (see TRAP User Manual)
604
605 for (Int_t iReg = 0; iReg < kLastReg; iReg++) {
606 if(fRegisterValue[iReg].state == RegValue_t::kIndividual) {
607 if (fRegisterValue[iReg].individualValue) {
608 delete [] fRegisterValue[iReg].individualValue;
609 fRegisterValue[iReg].individualValue = 0x0;
610 }
611 }
612
613 fRegisterValue[iReg].globalValue = GetRegResetValue((TrapReg_t) iReg);
614 fRegisterValue[iReg].state = RegValue_t::kGlobal;
615 // printf("%-8s: 0x%08x\n", GetRegName((TrapReg_t) iReg), fRegisterValue[iReg].globalValue);
616 }
617}
618
619
8ea391e3 620void AliTRDtrapConfig::ResetDmem()
621{
622 for(Int_t iAddr = 0; iAddr < fgkDmemWords; iAddr++) {
623 if(fDmemDepth[iAddr] == 0)
624 continue;
625 for(Int_t j=0; j < fDmemDepth[iAddr]; j++) {
626 fDmem[iAddr][j]=0;
627 }
628 }
629}
630
631
632Int_t AliTRDtrapConfig::GetTrapReg(TrapReg_t reg, Int_t det, Int_t rob, Int_t mcm) const
ce4786b9 633{
634 // get the value of an individual TRAP register
635 // if it is individual for TRAPs a valid TRAP has to be specified
636
637 if ((reg < 0) || (reg >= kLastReg)) {
638 AliError("Non-existing register requested");
54d34aac 639 return 0;
ce4786b9 640 }
641 else {
642 if (fRegisterValue[reg].state == RegValue_t::kGlobal) {
643 return fRegisterValue[reg].globalValue;
644 }
645 else if (fRegisterValue[reg].state == RegValue_t::kIndividual) {
646 if((det >= 0 && det < AliTRDgeometry::Ndet()) &&
647 (rob >= 0 && rob < AliTRDfeeParam::GetNrobC1()) &&
648 (mcm >= 0 && mcm < fgkMaxMcm)) {
649 return fRegisterValue[reg].individualValue[det*AliTRDfeeParam::GetNrobC1()*fgkMaxMcm + rob*fgkMaxMcm + mcm];
650 }
651 else {
652 AliError("Invalid MCM specified or register is individual");
637666cd 653 return 0;
ce4786b9 654 }
655 }
656 else { // should never be reached
657 AliError("MCM register status neither kGlobal nor kIndividual");
637666cd 658 return 0;
ce4786b9 659 }
660 }
ce4786b9 661}
662
663
664Bool_t AliTRDtrapConfig::SetTrapReg(TrapReg_t reg, Int_t value)
665{
666 // set a global value for the given TRAP register,
667 // i.e. the same value for all TRAPs
668
669 if (fRegisterValue[reg].state == RegValue_t::kGlobal) {
670 fRegisterValue[reg].globalValue = value;
671 return kTRUE;
672 }
673 else {
674 AliError("Register has individual values");
675 }
676 return kFALSE;
677}
678
679
680Bool_t AliTRDtrapConfig::SetTrapReg(TrapReg_t reg, Int_t value, Int_t det)
681{
682 // set a global value for the given TRAP register,
683 // i.e. the same value for all TRAPs
684
685 if (fRegisterValue[reg].state == RegValue_t::kGlobal) {
686 fRegisterValue[reg].globalValue = value;
687 return kTRUE;
688 }
689 else if (fRegisterValue[reg].state == RegValue_t::kIndividual) {
690 // if the register is in idividual mode but a broadcast is requested, the selected register is
691 // set to value for all MCMs on the chamber
692
693 if( (det>=0 && det<AliTRDgeometry::Ndet())) {
694 for(Int_t rob=0; rob<AliTRDfeeParam::GetNrobC1(); rob++) {
695 for(Int_t mcm=0; mcm<fgkMaxMcm; mcm++)
696 fRegisterValue[reg].individualValue[det*AliTRDfeeParam::GetNrobC1()*fgkMaxMcm + rob*fgkMaxMcm + mcm] = value;
697 }
698 }
699 else {
8ea391e3 700 AliError(Form("Invalid detector number: %i\n", det));
ce4786b9 701 return kFALSE;
702 }
703 }
704 else { // should never be reached
705 AliError("MCM register status neither kGlobal nor kIndividual");
706 return kFALSE;
707 }
708
709 return kFALSE;
710}
711
712
713Bool_t AliTRDtrapConfig::SetTrapReg(TrapReg_t reg, Int_t value, Int_t det, Int_t rob, Int_t mcm)
714{
715 // set the value for the given TRAP register of an individual MCM
716
051af255 717 //std::cout << "-- reg: 0x" << std::hex << fRegs[reg].addr <<
718 //std::dec << ", data " << value << ", det " << det << ", rob " << rob << ", mcm " << mcm << std::endl;
ce4786b9 719
720 if( (det >= 0 && det < AliTRDgeometry::Ndet()) &&
721 (rob >= 0 && rob < AliTRDfeeParam::GetNrobC1()) &&
722 (mcm >= 0 && mcm < fgkMaxMcm) ) {
723 if (fRegisterValue[reg].state == RegValue_t::kGlobal) {
724 Int_t defaultValue = fRegisterValue[reg].globalValue;
725
726 fRegisterValue[reg].state = RegValue_t::kIndividual;
727 fRegisterValue[reg].individualValue = new Int_t[AliTRDgeometry::Ndet()*AliTRDfeeParam::GetNrobC1()*fgkMaxMcm];
728
729 for(Int_t i = 0; i < AliTRDgeometry::Ndet()*AliTRDfeeParam::GetNrobC1()*fgkMaxMcm; i++)
730 fRegisterValue[reg].individualValue[i] = defaultValue; // set the requested register of all MCMs to the value previously stored
731
732 fRegisterValue[reg].individualValue[det*AliTRDfeeParam::GetNrobC1()*fgkMaxMcm + rob*fgkMaxMcm + mcm] = value;
733 }
734 else if (fRegisterValue[reg].state == RegValue_t::kIndividual) {
735 fRegisterValue[reg].individualValue[det*AliTRDfeeParam::GetNrobC1()*fgkMaxMcm + rob*fgkMaxMcm + mcm] = value;
736 }
737 else { // should never be reached
738 AliError("MCM register status neither kGlobal nor kIndividual");
739 return kFALSE;
740 }
741 }
742 else {
8ea391e3 743 AliError(Form("Invalid value for det, ROB or MCM selected: %i, %i, %i", det, rob, mcm));
ce4786b9 744 return kFALSE;
745 }
746
747 return kTRUE;
748}
749
750
8ea391e3 751UInt_t AliTRDtrapConfig::Peek(Int_t addr, Int_t det, Int_t rob, Int_t mcm) const
ce4786b9 752{
753 // reading from given address
ce4786b9 754
755 if ( (addr >= fgkDmemStartAddress) &&
756 (addr < (fgkDmemStartAddress + fgkDmemWords)) ) {
8ea391e3 757 return GetDmemUnsigned(addr, det, rob, mcm);
ce4786b9 758 }
759 else {
760 TrapReg_t mcmReg = GetRegByAddress(addr);
761 if ( mcmReg >= 0 && mcmReg < kLastReg) {
8ea391e3 762 return (UInt_t) GetTrapReg(mcmReg, det, rob, mcm);
ce4786b9 763 }
764 }
765
766 return -1;
767}
768
769
8ea391e3 770Bool_t AliTRDtrapConfig::Poke(Int_t addr, UInt_t value, Int_t det, Int_t rob, Int_t mcm)
ce4786b9 771{
772 // writing to given address
ce4786b9 773
774 if ( (addr >= fgkDmemStartAddress) &&
775 (addr < (fgkDmemStartAddress + fgkDmemWords)) ) {
051af255 776 AliDebug(2, Form("DMEM 0x%08x : %i", addr, value));
777 SetDmem(addr, value, det, rob, mcm);
ce4786b9 778 return kTRUE;
779 }
780 else {
781 TrapReg_t mcmReg = GetRegByAddress(addr);
782 if ( mcmReg >= 0 && mcmReg < kLastReg) {
051af255 783 AliDebug(2, Form("Register: %s : %i\n", GetRegName(mcmReg), value));
8ea391e3 784 SetTrapReg(mcmReg, (UInt_t) value, det, rob, mcm);
ce4786b9 785 return kTRUE;
786 }
787 }
051af255 788
ce4786b9 789 return kFALSE;
790}
791
792
051af255 793Bool_t AliTRDtrapConfig::SetDmem(Int_t addr, UInt_t value)
ce4786b9 794{
59f78ad5 795 // Set the content of the given DMEM address
796
8ea391e3 797 addr = addr - fgkDmemStartAddress;
ce4786b9 798
8ea391e3 799 if(addr < 0 || addr >= fgkDmemWords) {
5ac2e3b1 800 AliError(Form("No DMEM address: 0x%08x", addr+fgkDmemStartAddress));
8ea391e3 801 return kFALSE;
802 }
803
804 switch(fDmemDepth[addr]) {
805 case fgkDmemSizeEmpty:
5ac2e3b1 806 AliDebug(4, Form("DMEM address %i not active", addr));
8ea391e3 807 return kFALSE;
808 break;
809 case fgkDmemSizeUniform:
810 if(fDmem[addr][0]!=0)
811 AliDebug(5, Form("Warning: Setting new value to DMEM 0x%08x", addr+fgkDmemStartAddress));
812
813 fDmem[addr][0] = value;
814 break;
815 case fgkDmemSizeSmIndividual:
816 for(Int_t i=0; i<fgkDmemSizeSmIndividual; i++) {
817 if(fDmem[addr][i]!=0)
818 AliDebug(5, Form("Warning: Setting new value to DMEM 0x%08x", addr+fgkDmemStartAddress));
819
820 fDmem[addr][i]=value;
051af255 821 }
8ea391e3 822 break;
823 case fgkDmemSizeTotalIndividual:
824 for(Int_t i=0; i<fgkDmemSizeTotalIndividual; i++) {
825 if(fDmem[addr][i]!=0)
826 AliDebug(5, Form("Warning: Setting new value to DMEM 0x%08x", addr+fgkDmemStartAddress));
827
828 fDmem[addr][i]=value;
051af255 829 }
8ea391e3 830 break;
831 case fgkDmemSizeSmRocIndividual:
832 for(Int_t i=0; i<fgkDmemSizeSmRocIndividual; i++) {
833 if(fDmem[addr][i]!=0)
834 AliDebug(5, Form("Warning: Setting new value to DMEM 0x%08x", addr+fgkDmemStartAddress));
835
836 fDmem[addr][i]=value;
ce4786b9 837 }
8ea391e3 838 break;
839 default:
840 AliError(Form("Invalid selection type"));
841 break;
842 }
051af255 843
8ea391e3 844 return kTRUE;
ce4786b9 845}
846
847
8ea391e3 848Bool_t AliTRDtrapConfig::SetDmem(Int_t addr, UInt_t value, Int_t det, Int_t rob, Int_t mcm)
ce4786b9 849{
59f78ad5 850 // Set the content of the given DMEM address
851
8ea391e3 852 addr = addr - fgkDmemStartAddress;
853 Int_t roc = det%30;
854 Int_t loc;
855
856 if(addr < 0 || addr >= fgkDmemWords) {
857 AliError(Form("No DMEM address: 0x%08x", addr+fgkDmemStartAddress));
858 return kFALSE;
859 }
860
861 Int_t detFactor=8*16;
862 Int_t robFactor=16;
051af255 863
8ea391e3 864 switch(fDmemDepth[addr]) {
865 case fgkDmemSizeEmpty:
5ac2e3b1 866 AliDebug(4, Form("DMEM address 0x%08x not active", addr+fgkDmemStartAddress));
8ea391e3 867 return kFALSE;
868 break;
869 case fgkDmemSizeUniform:
870 if(fDmem[addr][0]!=0)
871 AliDebug(5, Form("Warning: Setting new value to DMEM 0x%08x", addr+fgkDmemStartAddress));
872
873 fDmem[addr][0] = value;
874 break;
875 case fgkDmemSizeSmIndividual:
876 loc = detFactor*roc + robFactor*rob + mcm;
877 if(loc < fgkDmemSizeSmIndividual) {
878 if(fDmem[addr][loc]!=0)
879 AliDebug(5, Form("Warning: Setting new value to DMEM 0x%08x", addr+fgkDmemStartAddress));
880
881 fDmem[addr][loc] = value;
051af255 882 }
8ea391e3 883 else {
884 AliError(Form("DMEM sub-address %i out of scope", loc));
885 return kFALSE;
051af255 886 }
8ea391e3 887 break;
888 case fgkDmemSizeTotalIndividual:
889 loc = detFactor*det + robFactor*rob + mcm;
890 if(loc < fgkDmemSizeTotalIndividual) {
891 if(fDmem[addr][loc]!=0)
892 AliDebug(5, Form("Warning: Setting new value to DMEM 0x%08x", addr+fgkDmemStartAddress));
893
894 fDmem[addr][loc]=value;
051af255 895 }
8ea391e3 896 else {
897 AliError(Form("DMEM sub-address %i out of scope", loc));
898 return kFALSE;
899 }
900 break;
901 case fgkDmemSizeSmRocIndividual:
902 if(det < fgkDmemSizeSmRocIndividual) {
903 if(fDmem[addr][det]!=0)
904 AliDebug(5, Form("Warning: Setting new value to DMEM 0x%08x", addr+fgkDmemStartAddress));
051af255 905
8ea391e3 906 fDmem[addr][det]=value;
907 }
908 else {
909 AliError(Form("DMEM sub-address %i out of scope", det));
910 return kFALSE;
911 }
912
913 break;
914 default:
915 AliError(Form("Invalid selection type"));
916 return kFALSE;
917 break;
918 }
919
920 return kTRUE;
ce4786b9 921}
922
923
8ea391e3 924UInt_t AliTRDtrapConfig::GetDmemUnsigned(Int_t addr) const
ce4786b9 925{
8ea391e3 926 addr = addr - fgkDmemStartAddress;
5ac2e3b1 927 if(addr < 0 || addr >= fgkDmemWords) {
8ea391e3 928 AliError(Form("No DMEM address: 0x%08x", addr+fgkDmemStartAddress));
929 return 0;
930 }
051af255 931
8ea391e3 932 if(fDmemDepth[addr] == fgkDmemSizeUniform)
933 return fDmem[addr][0];
934 else {
935 AliError(Form("No global DMEM value at 0x%08x", addr+fgkDmemStartAddress));
936 return 0;
937 }
938 return 0;
ce4786b9 939}
940
8ea391e3 941UInt_t AliTRDtrapConfig::GetDmemUnsigned(Int_t addr, Int_t det, Int_t rob, Int_t mcm) const
ce4786b9 942{
8ea391e3 943 addr = addr - fgkDmemStartAddress;
944 Int_t roc = det%30;
945 Int_t loc;
946
947 if(addr < 0 || addr >= fgkDmemWords) {
948 AliError(Form("No DMEM address: 0x%08x", addr+fgkDmemStartAddress));
949 return 0;
950 }
59f78ad5 951
8ea391e3 952 Int_t detFactor=8*16;
953 Int_t robFactor=16;
954
955 switch(fDmemDepth[addr]) {
956 case fgkDmemSizeEmpty:
5ac2e3b1 957 AliDebug(4, Form("DMEM address 0x%08x not active", addr+fgkDmemStartAddress));
8ea391e3 958 return 0;
959 break;
960 case fgkDmemSizeUniform:
961 return fDmem[addr][0];
962 break;
963 case fgkDmemSizeSmIndividual:
964 loc = detFactor*roc + robFactor*rob + mcm;
965 if(loc < fgkDmemSizeSmIndividual) {
966 return fDmem[addr][loc];
967 }
968 else {
969 AliError(Form("DMEM sub-address %i out of scope", loc));
970 return 0;
971 }
972 break;
973 case fgkDmemSizeTotalIndividual:
974 loc = detFactor*det + robFactor*rob + mcm;
975 if(loc < fgkDmemSizeTotalIndividual) {
976 return fDmem[addr][loc];
977 }
978 else {
979 AliError(Form("DMEM sub-address %i out of scope", loc));
980 return 0;
981 }
982 break;
983 case fgkDmemSizeSmRocIndividual:
984 if(det < fgkDmemSizeSmRocIndividual) {
985 return fDmem[addr][det];
986 }
987 else {
988 AliError(Form("DMEM sub-address %i out of scope", det));
989 return 0;
990 }
991 break;
992 default:
993 AliError(Form("Invalid selection type"));
994 return 0;
995 break;
996 }
997
998 return 0;
ce4786b9 999}
1000
1001
1002Bool_t AliTRDtrapConfig::LoadConfig()
1003{
1004 // load a set of TRAP register values (configuration)
1005 // here a default set is implemented for testing
1006 // for a detailed description of the registers see the TRAP manual
1007
7d619a80 1008 // HC header configuration bits
1009 SetTrapReg(kC15CPUA, 0x2102); // zs, deh
1010
ce4786b9 1011 // no. of timebins
1012 SetTrapReg(kC13CPUA, 24);
1013
1014 // pedestal filter
1015 SetTrapReg(kFPNP, 4*10);
1016 SetTrapReg(kFPTC, 0);
1017 SetTrapReg(kFPBY, 0); // bypassed!
1018
1019 // gain filter
1020 for (Int_t adc = 0; adc < 20; adc++) {
1021 SetTrapReg(TrapReg_t(kFGA0+adc), 40);
1022 SetTrapReg(TrapReg_t(kFGF0+adc), 15);
1023 }
1024 SetTrapReg(kFGTA, 20);
1025 SetTrapReg(kFGTB, 2060);
1026 SetTrapReg(kFGBY, 0); // bypassed!
1027
1028 // tail cancellation
1029 SetTrapReg(kFTAL, 267);
1030 SetTrapReg(kFTLL, 356);
1031 SetTrapReg(kFTLS, 387);
1032 SetTrapReg(kFTBY, 0);
1033
1034 // tracklet calculation
1035 SetTrapReg(kTPQS0, 5);
1036 SetTrapReg(kTPQE0, 10);
1037 SetTrapReg(kTPQS1, 11);
1038 SetTrapReg(kTPQE1, 20);
1039 SetTrapReg(kTPFS, 5);
1040 SetTrapReg(kTPFE, 20);
1041 SetTrapReg(kTPVBY, 0);
1042 SetTrapReg(kTPVT, 10);
1043 SetTrapReg(kTPHT, 150);
1044 SetTrapReg(kTPFP, 40);
1045 SetTrapReg(kTPCL, 1);
1046 SetTrapReg(kTPCT, 10);
1047
1048 // ndrift (+ 5 binary digits)
1049 SetDmem(0xc025, 20 << 5);
1050 // deflection + tilt correction
1051 SetDmem(0xc022, 0);
1052 // deflection range table
1053 for (Int_t iTrklCh = 0; iTrklCh < 18; iTrklCh++) {
1054 SetDmem(0xc030 + 2 * iTrklCh, -64); // min. deflection
1055 SetDmem(0xc031 + 2 * iTrklCh, 63); // max. deflection
1056 }
1057
1058 // hit position LUT
1059 const UShort_t lutPos[128] = {
1060 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15,
1061 16, 16, 16, 17, 17, 18, 18, 19, 19, 19, 20, 20, 20, 21, 21, 22, 22, 22, 23, 23, 23, 24, 24, 24, 24, 25, 25, 25, 26, 26, 26, 26,
1062 27, 27, 27, 27, 27, 27, 27, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 27, 27, 27, 27, 26,
1063 26, 26, 26, 25, 25, 25, 24, 24, 23, 23, 22, 22, 21, 21, 20, 20, 19, 18, 18, 17, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 7};
1064 for (Int_t iCOG = 0; iCOG < 128; iCOG++)
1065 SetTrapReg((TrapReg_t) (kTPL00 + iCOG), lutPos[iCOG]);
1066
1067 // event buffer
1068 SetTrapReg(kEBSF, 1); // 0: store filtered; 1: store unfiltered
1069 // zs applied to data stored in event buffer (sel. by EBSF)
1070 SetTrapReg(kEBIS, 15 << 2); // single indicator threshold (plus two digits)
1071 SetTrapReg(kEBIT, 30 << 2); // sum indicator threshold (plus two digits)
1072 SetTrapReg(kEBIL, 0xf0); // lookup table
1073 SetTrapReg(kEBIN, 0); // neighbour sensitivity
1074
1075 // raw data
1076 SetTrapReg(kNES, (0x0000 << 16) | 0x1000);
1077
1078 return kTRUE;
1079}
1080
1081
051af255 1082Bool_t AliTRDtrapConfig::ReadPackedConfig(Int_t hc, UInt_t *data, Int_t size)
ce4786b9 1083{
59f78ad5 1084 // Read the packed configuration from the passed memory block
1085 //
1086 // To be used to retrieve the TRAP configuration from the
1087 // configuration as sent in the raw data.
1088
051af255 1089 AliDebug(1, "Reading packed configuration");
1090
1091 Int_t det = hc/2;
1092
ce4786b9 1093 Int_t idx = 0;
1094 Int_t err = 0;
59f78ad5 1095 Int_t step, bwidth, nwords, exitFlag, bitcnt;
ce4786b9 1096
1097 UShort_t caddr;
59f78ad5 1098 UInt_t dat, msk, header, dataHi;
ce4786b9 1099
051af255 1100 while (idx < size && *data != 0x00000000) {
ce4786b9 1101
051af255 1102 Int_t rob = (*data >> 28) & 0x7;
1103 Int_t mcm = (*data >> 24) & 0xf;
1104
1105 AliDebug(1, Form("Config of det. %3i MCM %i:%02i (0x%08x)", det, rob, mcm, *data));
ce4786b9 1106 data++;
ce4786b9 1107
051af255 1108 while (idx < size && *data != 0x00000000) {
ce4786b9 1109
051af255 1110 header = *data;
1111 data++;
1112 idx++;
ce4786b9 1113
051af255 1114 AliDebug(5, Form("read: 0x%08x", header));
ce4786b9 1115
8ea391e3 1116 if (header & 0x01) // single data
051af255 1117 {
8ea391e3 1118 dat = (header >> 2) & 0xFFFF; // 16 bit data
1119 caddr = (header >> 18) & 0x3FFF; // 14 bit address
051af255 1120
8ea391e3 1121 if (caddr != 0x1FFF) // temp!!! because the end marker was wrong
051af255 1122 {
8ea391e3 1123 if (header & 0x02) // check if > 16 bits
051af255 1124 {
1125 dataHi = *data;
1126 AliDebug(5, Form("read: 0x%08x", dataHi));
1127 data++;
1128 idx++;
1129 err += ((dataHi ^ (dat | 1)) & 0xFFFF) != 0;
1130 dat = (dataHi & 0xFFFF0000) | dat;
1131 }
1132 AliDebug(5, Form("addr=0x%04x (%s) data=0x%08x\n", caddr, GetRegName(GetRegByAddress(caddr)), dat));
1133 if ( ! Poke(caddr, dat, det, rob, mcm) )
1134 AliDebug(5, Form("(single-write): non-existing address 0x%04x containing 0x%08x\n", caddr, header));
1135 if (idx > size)
1136 {
1137 AliDebug(5, Form("(single-write): no more data, missing end marker\n"));
1138 return -err;
1139 }
1140 }
1141 else
1142 {
1143 AliDebug(5, Form("(single-write): address 0x%04x => old endmarker?\n", caddr));
1144 return err;
1145 }
1146 }
1147
8ea391e3 1148 else // block of data
051af255 1149 {
1150 step = (header >> 1) & 0x0003;
1151 bwidth = ((header >> 3) & 0x001F) + 1;
1152 nwords = (header >> 8) & 0x00FF;
1153 caddr = (header >> 16) & 0xFFFF;
1154 exitFlag = (step == 0) || (step == 3) || (nwords == 0);
1155
1156 if (exitFlag)
1157 break;
1158
1159 switch (bwidth)
1160 {
1161 case 15:
1162 case 10:
1163 case 7:
1164 case 6:
1165 case 5:
1166 {
1167 msk = (1 << bwidth) - 1;
1168 bitcnt = 0;
1169 while (nwords > 0)
1170 {
1171 nwords--;
1172 bitcnt -= bwidth;
1173 if (bitcnt < 0)
1174 {
1175 header = *data;
1176 AliDebug(5, Form("read 0x%08x", header));
1177 data++;
1178 idx++;
1179 err += (header & 1);
1180 header = header >> 1;
1181 bitcnt = 31 - bwidth;
1182 }
1183 AliDebug(5, Form("addr=0x%04x (%s) data=0x%08x\n", caddr, GetRegName(GetRegByAddress(caddr)), header & msk));
1184 if ( ! Poke(caddr, header & msk, det, rob, mcm) )
1185 AliDebug(5, Form("(single-write): non-existing address 0x%04x containing 0x%08x\n", caddr, header));
1186
1187 caddr += step;
1188 header = header >> bwidth;
1189 if (idx >= size)
1190 {
1191 AliDebug(5, Form("(block-write): no end marker! %d words read\n", idx));
1192 return -err;
1193 }
1194 }
1195 break;
1196 } // end case 5-15
1197 case 31:
1198 {
1199 while (nwords > 0)
1200 {
1201 header = *data;
1202 AliDebug(5, Form("read 0x%08x", header));
1203 data++;
1204 idx++;
1205 nwords--;
1206 err += (header & 1);
1207
1208 AliDebug(5, Form("addr=0x%04x (%s) data=0x%08x", caddr, GetRegName(GetRegByAddress(caddr)), header >> 1));
1209 if ( ! Poke(caddr, header >> 1, det, rob, mcm) )
1210 AliDebug(5, Form("(single-write): non-existing address 0x%04x containing 0x%08x\n", caddr, header));
1211
1212 caddr += step;
1213 if (idx >= size)
1214 {
1215 AliDebug(5, Form("no end marker! %d words read", idx));
1216 return -err;
1217 }
1218 }
1219 break;
1220 }
1221 default: return err;
8ea391e3 1222 } // end switch
1223 } // end block case
051af255 1224 }
8ea391e3 1225 } // end while
ce4786b9 1226 AliDebug(5, Form("no end marker! %d words read", idx));
1227 return -err; // only if the max length of the block reached!
1228}
1229
1230
8ea391e3 1231Bool_t AliTRDtrapConfig::PrintTrapReg(TrapReg_t reg, Int_t det, Int_t rob, Int_t mcm) const
ce4786b9 1232{
1233 // print the value stored in the given register
1234 // if it is individual a valid MCM has to be specified
1235
1236 if (fRegisterValue[reg].state == RegValue_t::kGlobal) {
1237 printf("%s (%i bits) at 0x%08x is 0x%08x and resets to: 0x%08x (currently global mode)\n",
1238 GetRegName((TrapReg_t) reg),
1239 GetRegNBits((TrapReg_t) reg),
1240 GetRegAddress((TrapReg_t) reg),
1241 fRegisterValue[reg].globalValue,
1242 GetRegResetValue((TrapReg_t) reg));
1243 }
1244 else if (fRegisterValue[reg].state == RegValue_t::kIndividual) {
1245 if((det >= 0 && det < AliTRDgeometry::Ndet()) &&
1246 (rob >= 0 && rob < AliTRDfeeParam::GetNrobC1()) &&
1247 (mcm >= 0 && mcm < fgkMaxMcm)) {
1248 printf("%s (%i bits) at 0x%08x is 0x%08x and resets to: 0x%08x (currently individual mode)\n",
1249 GetRegName((TrapReg_t) reg),
1250 GetRegNBits((TrapReg_t) reg),
1251 GetRegAddress((TrapReg_t) reg),
1252 fRegisterValue[reg].individualValue[det*AliTRDfeeParam::GetNrobC1()*fgkMaxMcm + rob*fgkMaxMcm + mcm],
1253 GetRegResetValue((TrapReg_t) reg));
1254 }
1255 else {
1256 AliError("Register value is MCM-specific: Invalid detector, ROB or MCM requested");
1257 return kFALSE;
1258 }
1259 }
1260 else { // should never be reached
1261 AliError("MCM register status neither kGlobal nor kIndividual");
1262 return kFALSE;
1263 }
1264 return kTRUE;
1265}
1266
1267
8ea391e3 1268Bool_t AliTRDtrapConfig::PrintTrapAddr(Int_t addr, Int_t det, Int_t rob, Int_t mcm) const
ce4786b9 1269{
1270 // print the value stored at the given address in the MCM chip
1271 TrapReg_t reg = GetRegByAddress(addr);
1272 if (reg >= 0 && reg < kLastReg) {
1273 return PrintTrapReg(reg, det, rob, mcm);
1274 }
1275 else {
1276 AliError(Form("There is no register at address 0x%08x in the simulator", addr));
1277 return kFALSE;
1278 }
1279}
1280
1281
1282Bool_t AliTRDtrapConfig::AddValues(UInt_t det, UInt_t cmd, UInt_t extali, Int_t addr, UInt_t data)
1283{
1284 // transfer the informations provided by LoadConfig to the internal class variables
1285
1286 if(cmd != fgkScsnCmdWrite) {
1287 AliError(Form("Invalid command received: %i", cmd));
1288 return kFALSE;
1289 }
1290
1291 TrapReg_t mcmReg = GetRegByAddress(addr);
1292 Int_t rocType = AliTRDgeometry::GetStack(det) == 2 ? 0 : 1;
1293
8ea391e3 1294 static const int mcmListSize=40; // 40 is more or less arbitrary
1295 Int_t mcmList[mcmListSize];
1296
ce4786b9 1297 // configuration registers
1298 if(mcmReg >= 0 && mcmReg < kLastReg) {
1299
1300 for(Int_t linkPair=0; linkPair<fgkMaxLinkPairs; linkPair++) {
8ea391e3 1301 if(AliTRDfeeParam::ExtAliToAli(extali, linkPair, rocType, mcmList, mcmListSize)!=0) {
1302 Int_t i=0;
1303 while(mcmList[i] != -1 && i<mcmListSize) {
1304 if(mcmList[i]==127)
ce4786b9 1305 SetTrapReg( (TrapReg_t) mcmReg, data, det);
1306 else
8ea391e3 1307 SetTrapReg( (TrapReg_t) mcmReg, data, det, (mcmList[i]>>7), (mcmList[i]&0x7F));
ce4786b9 1308 i++;
1309 }
1310 }
1311 }
1312 return kTRUE;
1313 }
1314 // DMEM
1315 else if ( (addr >= fgkDmemStartAddress) &&
1316 (addr < (fgkDmemStartAddress + fgkDmemWords))) {
1317 for(Int_t linkPair=0; linkPair<fgkMaxLinkPairs; linkPair++) {
8ea391e3 1318 if(AliTRDfeeParam::ExtAliToAli(extali, linkPair, rocType, mcmList, mcmListSize)!=0) {
ce4786b9 1319 Int_t i=0;
8ea391e3 1320 while(mcmList[i] != -1 && i < mcmListSize) {
1321 if(mcmList[i] == 127)
1322 SetDmem(addr, data, det, 0, 127);
ce4786b9 1323 else
8ea391e3 1324 SetDmem(addr, data, det, mcmList[i] >> 7, mcmList[i] & 0x7f);
ce4786b9 1325 i++;
1326 }
1327 }
1328 }
1329 return kTRUE;
1330 }
1331 else
1332 return kFALSE;
1333}
1334
1335
8ea391e3 1336AliTRDtrapConfig::TrapReg_t AliTRDtrapConfig::GetRegByAddress(Int_t address) const
ce4786b9 1337{
8ea391e3 1338 // get register by its address
1339 // used for reading of configuration data as sent to real FEE
ce4786b9 1340
8ea391e3 1341 TrapReg_t mcmReg = kLastReg;
1342 Int_t reg = 0;
1343 do {
1344 if(fRegs[reg].fAddr == address)
1345 mcmReg = (TrapReg_t) reg;
1346 reg++;
1347 } while (mcmReg == kLastReg && reg < kLastReg);
ce4786b9 1348
8ea391e3 1349 return mcmReg;
ce4786b9 1350}
1351
1352
8ea391e3 1353void AliTRDtrapConfig::PrintMemDatx(ostream &os, Int_t addr) const
ce4786b9 1354{
8ea391e3 1355 PrintMemDatx(os, addr, 0, 0, 127);
ce4786b9 1356}
1357
8ea391e3 1358void AliTRDtrapConfig::PrintMemDatx(ostream &os, Int_t addr, Int_t det, Int_t rob, Int_t mcm) const
ce4786b9 1359{
8ea391e3 1360 if(addr < fgkDmemStartAddress || addr >= fgkDmemStartAddress+fgkDmemWords) {
1361 AliError(Form("Invalid DMEM address 0x%08x!", addr));
1362 return;
1363 }
1364 PrintDatx(os, addr, GetDmemUnsigned(addr, det, rob, mcm), rob, mcm);
1365}
1366
ce4786b9 1367
8ea391e3 1368void AliTRDtrapConfig::PrintMemDatx(ostream &os, TrapReg_t reg) const
1369{
1370 PrintMemDatx(os, reg, 0, 0, 127);
ce4786b9 1371}
1372
1373
8ea391e3 1374void AliTRDtrapConfig::PrintMemDatx(ostream &os, TrapReg_t reg, Int_t det, Int_t rob, Int_t mcm) const
ce4786b9 1375{
8ea391e3 1376 if(reg>= kLastReg) {
1377 AliError(Form("Invalid register %i!", reg));
1378 return;
1379 }
1380 PrintDatx(os, GetRegAddress(reg), GetTrapReg(reg, det, rob, mcm), rob, mcm);
1381}
36dc3337 1382
ce4786b9 1383
8ea391e3 1384void AliTRDtrapConfig::PrintDatx(ostream &os, UInt_t addr, UInt_t data, Int_t rob, Int_t mcm) const
1385{
1386 os << std::setw(5) << 10
1387 << std::setw(8) << addr
1388 << std::setw(12) << data;
1389 if(mcm==127)
1390 os << std::setw(8) << 127;
1391 else
1392 os << std::setw(8) << AliTRDfeeParam::AliToExtAli(rob, mcm);
1393
1394 os << std::endl;
ce4786b9 1395}