1 #/**************************************************************************
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2 * Copyright(c) 1998-1999, ALICE Experiment at CERN, All rights reserved. *
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4 * Author: The ALICE Off-line Project. *
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5 * Contributors are mentioned in the code where appropriate. *
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7 * Permission to use, copy, modify and distribute this software and its *
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8 * documentation strictly for non-commercial purposes is hereby granted *
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9 * without fee, provided that the above copyright notice appears in all *
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10 * copies and that both the copyright notice and this permission notice *
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11 * appear in the supporting documentation. The authors make no claims *
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12 * about the suitability of this software for any purpose. It is *
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13 * provided "as is" without express or implied warranty. *
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14 **************************************************************************/
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16 /* $Id: AliTRDrawTPStream.cxx 27797 2008-08-05 14:37:22Z cblume $ */
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18 ///////////////////////////////////////////////////////////////////////////////////////
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20 // This class provides access to pattern generated TRD raw data including //
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21 // configuration data. //
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23 // It is based on Venelin Angelov's c++ code decoding standalone //
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24 // configuration data //
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25 // http://alice.physi.uni-heidelberg.de/svn/trd/wconfigurations/trunk/C/trap_cnf.cpp //
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26 // http://alice.physi.uni-heidelberg.de/svn/trd/wconfigurations/trunk/C/trap_cnf.h //
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28 // Author: MinJung Kweon(minjung@physi.uni-heidelberg.de) //
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30 ///////////////////////////////////////////////////////////////////////////////////////
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32 //#include "AliLog.h"
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34 #include "AliTRDrawStream.h"
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35 #include "AliTRDrawTPStream.h"
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38 #define GET_VALUE_AT(w,m,s) (( (w) >> (s)) & (m) )
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39 #define MCM_HEADER_MASK_ERR(w) ( ((w) & (0xf)) == (0xc) ? 0 : 1)
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40 #define MCM_ROB_NUMBER(w) GET_VALUE_AT(w,0x7,28)
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41 #define MCM_MCM_NUMBER(w) GET_VALUE_AT(w,0x0f,24)
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42 #define MCM_EVENT_COUNTER(w) GET_VALUE_AT(w,0x00fffff,4)
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46 ClassImp(AliTRDrawTPStream)
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48 //---------------------------------------------------------------------
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49 AliTRDrawTPStream::AliTRDrawTPStream(Int_t rawVMajorOpt, UInt_t * pPos)
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50 : AliTRDrawStreamBase()
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61 , fRawVMajorOpt(rawVMajorOpt)
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64 // default constructor
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67 if (FillConfig() == kFALSE)
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68 AliError("Reading reset value failed.");
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72 //---------------------------------------------------------------------
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73 AliTRDrawTPStream::AliTRDrawTPStream(const AliTRDrawTPStream& /*st*/)
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74 : AliTRDrawStreamBase()
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85 , fRawVMajorOpt()
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88 // copy constructor
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91 AliError("Not implemeneted.");
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95 //---------------------------------------------------------------------
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96 AliTRDrawTPStream &
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97 AliTRDrawTPStream::operator=(const AliTRDrawTPStream &)
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100 // we are not using this functionality
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102 AliFatal("May not use.");
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106 //---------------------------------------------------------------------
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107 AliTRDrawTPStream::~AliTRDrawTPStream()
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114 //---------------------------------------------------------------------
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115 Bool_t AliTRDrawTPStream::DecodeTPdata()
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118 // main function to decode test pattern data
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119 // fRawVMajorOpt version control different type of test pattern data
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122 if (fRawVMajorOpt == 7)
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124 AliInfo("This is configuration data event read by first trigger.");
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125 if(!AliTRDrawStream::fgEnableDecodeConfigData) return kTRUE;
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126 if (DecodeConfigdata() == kFALSE) // configuration data
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128 AliError("failed to to decode configuration data");
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135 AliError("These are different type of test pattern data. You need other reader");
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140 //---------------------------------------------------------------------
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141 Bool_t AliTRDrawTPStream::DecodeConfigdata()
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144 // main function to decode trap configuration data
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147 UInt_t packedConf[256];
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148 Int_t mcmPos, mcmsRead, lengthPacked;
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153 mcmPos = ReadPacked(fpPos, packedConf, &lengthPacked);
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157 UnPackConfN(packedConf, lengthPacked);
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160 AliInfo(Form("%d MCMs read up to now, last was MCM%02d\n",mcmsRead, mcmPos));
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162 } while ((mcmsRead < 84) && (mcmPos >= 0)); // [mj] have to think about # of mcmsRead
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163 AliInfo("Done\n");
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168 //---------------------------------------------------------------------
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169 Int_t AliTRDrawTPStream::ReadPacked(UInt_t *word, UInt_t *pData, Int_t * const nWords)
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172 // decode packed data words
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175 UInt_t vword = *word;
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178 UInt_t err, robNum, mcmNum, chipId, noEndMarker;
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183 // decode mcm header
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184 if(MCM_HEADER_MASK_ERR(vword)) err++;
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186 robNum = MCM_ROB_NUMBER(vword);
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187 mcmNum = MCM_MCM_NUMBER(vword);
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188 chipId = MCM_EVENT_COUNTER(vword);
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191 AliInfo(Form("MCM header ROB %d, MCM %02d, ChipId %d 0x%05x\n", robNum, mcmNum, chipId, chipId));
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196 // read MCM data and store into array
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203 noEndMarker = ((vword != ENDM_CONF) && (vword != (ENDM_CONF | 1)) && (vword != 0x10001000));
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207 } while (noEndMarker && (iLength < 256));
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212 *nWords = iLength;
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213 if (iLength == 0)
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219 //---------------------------------------------------------------------
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220 void AliTRDrawTPStream::PowerUp() // power up
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223 // copy the reset values
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226 for (Int_t i=0; i< NREGS; i++)
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228 fRegs[i] = fTrapReg[i].fResVal;
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231 // mark all DMEM cells as invalid
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232 for (Int_t i=0; i< NDMEM; i++) fDmemValid[i] = 0;
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233 // mark all DBANK cells as empty
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234 for (Int_t i=0; i< NDBANK; i++) fDbankPro[i] = kDbankEmpty;
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238 //---------------------------------------------------------------------
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239 Int_t AliTRDrawTPStream::UnPackConfN(const UInt_t *pData, Int_t maxLength)
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242 // unpack configuration
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245 Int_t debug = 0; // the debug mode not completely ready
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246 Int_t step, bwidth, nwords, idx, err, exitFlag, bitcnt, werr;
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248 UInt_t dat, msk, header, dataHi;
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250 idx = 0; // index in PackedConf
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252 while (idx < maxLength)
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255 if (debug) printf("read 0x%08x ",header);
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258 if (header & 0x01) // single data
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260 dat = (header >> 2) & 0xFFFF; // 16 bit data
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261 caddr = (header >> 18) & 0x3FFF; // 14 bit address
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262 if (caddr != 0x1FFF) // temp!!! because the end marker was wrong
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264 if (header & 0x02) // check if > 16 bits
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267 if (debug) printf("read 0x%08x ",dataHi);
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270 err += ((dataHi ^ (dat | 1)) & 0xFFFF) != 0;
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271 dat = (dataHi & 0xFFFF0000) | dat;
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273 if (debug) printf("addr=0x%04x (%s) data=0x%08x\n",caddr, Addr2Name(caddr), dat);
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274 werr = SetU(caddr, dat);
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277 printf("(single-write): non-existing address 0x%04x containing 0x%08x\n", caddr, header);
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279 if (idx > maxLength)
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281 printf("(single-write): no more data, missing end marker\n");
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287 printf("(single-write): address 0x%04x => old endmarker?\n",caddr);
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291 else // block of data
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293 step = (header >> 1) & 0x0003;
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294 bwidth = ((header >> 3) & 0x001F) + 1;
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295 nwords = (header >> 8) & 0x00FF;
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296 caddr = (header >> 16) & 0xFFFF;
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297 exitFlag = (step == 0) || (step == 3) || (nwords == 0);
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298 if (exitFlag) return err;
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307 msk = (1 << bwidth) - 1;
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309 while (nwords > 0)
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312 bitcnt -= bwidth;
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316 if (debug) printf("read 0x%08x ",header);
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319 err += (header & 1);
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320 header = header >> 1;
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321 bitcnt = 31 - bwidth;
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323 if (debug) printf("addr=0x%04x (%s) data=0x%08x\n",caddr, Addr2Name(caddr), header & msk);
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324 werr = SetU(caddr, header & msk);
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327 printf("(single-write): non-existing address 0x%04x containing 0x%08x\n", caddr, header);
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330 header = header >> bwidth;
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331 if (idx >= maxLength)
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333 printf("(block-write): no end marker! %d words read\n",idx);
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338 } // end case 5-15
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341 while (nwords > 0)
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344 if (debug) printf("read 0x%08x ",header);
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348 err += (header & 1);
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349 if (debug) printf("addr=0x%04x (%s) data=0x%08x\n",caddr, Addr2Name(caddr), header >> 1);
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350 werr = SetU(caddr, header >> 1);
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353 printf("(single-write): non-existing address 0x%04x containing 0x%08x\n", caddr, header);
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356 if (idx >= maxLength)
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358 printf("no end marker! %d words read\n",idx);
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364 default: return err;
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366 } // end block case
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368 printf("no end marker! %d words read\n",idx);
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369 return -err; // only if the max length of the block reached!
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372 //---------------------------------------------------------------------
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373 void AliTRDrawTPStream::DumpCnf(Int_t slv)
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376 // dump configuration
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380 for (idx = 0; idx < NREGS; idx++) // config. reg
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383 printf("%s\t0x%08x\t%3d %c\n", fTrapReg[idx].fkName, (Int_t) fRegs[idx], slv, CnfStat(fCnfPro[idx]));
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385 printf("%s\t0x%08x %c\n", fTrapReg[idx].fkName, (Int_t) fRegs[idx], CnfStat(fCnfPro[idx]));
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390 //---------------------------------------------------------------------
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391 const Char_t * AliTRDrawTPStream::Addr2Name(UInt_t addr) const
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394 // return name of a given address
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399 if ( ( ( (addr >> 4) & 0xFFE) == 0x0C0) && ( ( (addr >> 2) & 1) == 1) )
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401 addr = addr & 0x0C07;
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403 while ((idx < NREGS) && (fTrapReg[idx].fAddr != addr) ) idx++;
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405 return fTrapReg[idx].fkName;
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407 while ((idx < NCMD) && (fCmdReg[idx].fAddr != addr)) idx++;
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409 return fCmdReg[idx].fkName;
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411 while ((idx < NRO) && (fRoReg[idx].fAddr != addr)) idx++;
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413 return fRoReg[idx].fkName;
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418 //---------------------------------------------------------------------
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419 Char_t AliTRDrawTPStream::CnfStat(UInt_t prop) const
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422 // return configuration status
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425 if (prop == 0) return 'U';
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427 if (prop == 1) return 'R';
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429 if (prop == 2) return 'I';
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434 //---------------------------------------------------------------------
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435 Int_t AliTRDrawTPStream::SetU(UInt_t addr, UInt_t newVal)
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442 UInt_t maxVal = 0;
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444 if (AddrIsDmem(addr))
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446 fDmem[addr & 0x3FF] = newVal;
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447 fDmemValid[addr & 0x3FF] = 1;
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451 if (AddrIsDbank(addr))
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453 fDbank[addr & 0xFF] = newVal;
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454 fDbankPro[addr & 0xFF] = kScsnDat;
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459 i = Addr2Idx(addr);
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460 if (i < NREGS) // found
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463 if (fTrapReg[i].fNbits < 32) // create the max value from the number of bits
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466 maxVal = (maxVal << fTrapReg[i].fNbits) - 1;
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468 if ( (fTrapReg[i].fNbits == 32) || (newVal <= maxVal) ) // in range
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470 fRegs[i] = newVal;
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474 { // out of range
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475 fRegs[i] = newVal & maxVal;
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476 printf("Out of range, writing 0x%08x to %d bits at addr = 0x%04x\n",newVal, fTrapReg[i].fNbits, addr);
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480 else // not found
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482 printf("(SetU): No such address, writing 0x%08x to addr = 0x%04x\n",newVal, addr);
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483 return -1; // no such address
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488 //---------------------------------------------------------------------
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489 Int_t AliTRDrawTPStream::AddrIsDmem(UInt_t addr) const
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491 addr = (addr >> 10);
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492 return (addr == 0x30);
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495 //---------------------------------------------------------------------
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496 Int_t AliTRDrawTPStream::AddrIsDbank(UInt_t addr) const
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498 addr = (addr >> 8);
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499 return (addr == 0xF0);
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502 //---------------------------------------------------------------------
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503 UInt_t AliTRDrawTPStream::Addr2Idx(UInt_t addr) const
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506 // return index from a given address
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511 // check if global const
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512 if ( ( ( (addr >> 4) & 0xFFE) == 0x0C0) && ( ( (addr >> 2) & 1) == 1) )
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514 addr = addr & 0x0C07;
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517 while ((idx < NREGS) && (fTrapReg[idx].fAddr != addr)) idx++;
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518 // printf("Addr = 0x%04x; Idx = %d\n",addr, idx); // debugging
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522 //---------------------------------------------------------------------
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523 Bool_t AliTRDrawTPStream::FillConfig()
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526 // fill array with configuraiton information
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529 const SimpleRegs kTrapReg[NREGS] = {
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530 // Name Address Nbits Reset Value
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531 // Global state machine
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532 {"SML0", 0x0A00, 15, 0x4050},
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533 {"SML1", 0x0A01, 15, 0x4200},
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534 {"SML2", 0x0A02, 15, 0x4384},
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535 {"SMMODE", 0x0A03, 16, 0xF0E2},
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536 {"NITM0", 0x0A08, 14, 0x3FFF},
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537 {"NITM1", 0x0A09, 14, 0x3FFF},
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538 {"NITM2", 0x0A0A, 14, 0x3FFF},
\r\r
539 {"NIP4D", 0x0A0B, 7, 0x7F},
\r\r
540 {"CPU0CLK", 0x0A20, 5, 0x07},
\r\r
541 {"CPU1CLK", 0x0A22, 5, 0x07},
\r\r
542 {"CPU2CLK", 0x0A24, 5, 0x07},
\r\r
543 {"CPU3CLK", 0x0A26, 5, 0x07},
\r\r
544 {"NICLK", 0x0A28, 5, 0x07},
\r\r
545 {"FILCLK", 0x0A2A, 5, 0x07},
\r\r
546 {"PRECLK", 0x0A2C, 5, 0x07},
\r\r
547 {"ADCEN", 0x0A2E, 5, 0x07},
\r\r
548 {"NIODE", 0x0A30, 5, 0x07},
\r\r
549 {"NIOCE", 0x0A32, 5, 0x21}, // bit 5 is status bit (read-only)!
\r\r
550 {"NIIDE", 0x0A34, 5, 0x07},
\r\r
551 {"NIICE", 0x0A36, 5, 0x07},
\r\r
553 {"ARBTIM", 0x0A3F, 4, 0x0},
\r\r
555 {"IA0IRQ0", 0x0B00, 12, 0x000},
\r\r
556 {"IA0IRQ1", 0x0B01, 12, 0x000},
\r\r
557 {"IA0IRQ2", 0x0B02, 12, 0x000},
\r\r
558 {"IA0IRQ3", 0x0B03, 12, 0x000},
\r\r
559 {"IA0IRQ4", 0x0B04, 12, 0x000},
\r\r
560 {"IA0IRQ5", 0x0B05, 12, 0x000},
\r\r
561 {"IA0IRQ6", 0x0B06, 12, 0x000},
\r\r
562 {"IA0IRQ7", 0x0B07, 12, 0x000},
\r\r
563 {"IA0IRQ8", 0x0B08, 12, 0x000},
\r\r
564 {"IA0IRQ9", 0x0B09, 12, 0x000},
\r\r
565 {"IA0IRQA", 0x0B0A, 12, 0x000},
\r\r
566 {"IA0IRQB", 0x0B0B, 12, 0x000},
\r\r
567 {"IA0IRQC", 0x0B0C, 12, 0x000},
\r\r
568 {"IRQSW0", 0x0B0D, 13, 0x1FFF},
\r\r
569 {"IRQHW0", 0x0B0E, 13, 0x0000},
\r\r
570 {"IRQHL0", 0x0B0F, 13, 0x0000},
\r\r
572 {"IA1IRQ0", 0x0B20, 12, 0x000},
\r\r
573 {"IA1IRQ1", 0x0B21, 12, 0x000},
\r\r
574 {"IA1IRQ2", 0x0B22, 12, 0x000},
\r\r
575 {"IA1IRQ3", 0x0B23, 12, 0x000},
\r\r
576 {"IA1IRQ4", 0x0B24, 12, 0x000},
\r\r
577 {"IA1IRQ5", 0x0B25, 12, 0x000},
\r\r
578 {"IA1IRQ6", 0x0B26, 12, 0x000},
\r\r
579 {"IA1IRQ7", 0x0B27, 12, 0x000},
\r\r
580 {"IA1IRQ8", 0x0B28, 12, 0x000},
\r\r
581 {"IA1IRQ9", 0x0B29, 12, 0x000},
\r\r
582 {"IA1IRQA", 0x0B2A, 12, 0x000},
\r\r
583 {"IA1IRQB", 0x0B2B, 12, 0x000},
\r\r
584 {"IA1IRQC", 0x0B2C, 12, 0x000},
\r\r
585 {"IRQSW1", 0x0B2D, 13, 0x1FFF},
\r\r
586 {"IRQHW1", 0x0B2E, 13, 0x0000},
\r\r
587 {"IRQHL1", 0x0B2F, 13, 0x0000},
\r\r
589 {"IA2IRQ0", 0x0B40, 12, 0x000},
\r\r
590 {"IA2IRQ1", 0x0B41, 12, 0x000},
\r\r
591 {"IA2IRQ2", 0x0B42, 12, 0x000},
\r\r
592 {"IA2IRQ3", 0x0B43, 12, 0x000},
\r\r
593 {"IA2IRQ4", 0x0B44, 12, 0x000},
\r\r
594 {"IA2IRQ5", 0x0B45, 12, 0x000},
\r\r
595 {"IA2IRQ6", 0x0B46, 12, 0x000},
\r\r
596 {"IA2IRQ7", 0x0B47, 12, 0x000},
\r\r
597 {"IA2IRQ8", 0x0B48, 12, 0x000},
\r\r
598 {"IA2IRQ9", 0x0B49, 12, 0x000},
\r\r
599 {"IA2IRQA", 0x0B4A, 12, 0x000},
\r\r
600 {"IA2IRQB", 0x0B4B, 12, 0x000},
\r\r
601 {"IA2IRQC", 0x0B4C, 12, 0x000},
\r\r
602 {"IRQSW2", 0x0B4D, 13, 0x1FFF},
\r\r
603 {"IRQHW2", 0x0B4E, 13, 0x0000},
\r\r
604 {"IRQHL2", 0x0B4F, 13, 0x0000},
\r\r
606 {"IA3IRQ0", 0x0B60, 12, 0x000},
\r\r
607 {"IA3IRQ1", 0x0B61, 12, 0x000},
\r\r
608 {"IA3IRQ2", 0x0B62, 12, 0x000},
\r\r
609 {"IA3IRQ3", 0x0B63, 12, 0x000},
\r\r
610 {"IA3IRQ4", 0x0B64, 12, 0x000},
\r\r
611 {"IA3IRQ5", 0x0B65, 12, 0x000},
\r\r
612 {"IA3IRQ6", 0x0B66, 12, 0x000},
\r\r
613 {"IA3IRQ7", 0x0B67, 12, 0x000},
\r\r
614 {"IA3IRQ8", 0x0B68, 12, 0x000},
\r\r
615 {"IA3IRQ9", 0x0B69, 12, 0x000},
\r\r
616 {"IA3IRQA", 0x0B6A, 12, 0x000},
\r\r
617 {"IA3IRQB", 0x0B6B, 12, 0x000},
\r\r
618 {"IA3IRQC", 0x0B6C, 12, 0x000},
\r\r
619 {"IRQSW3", 0x0B6D, 13, 0x1FFF},
\r\r
620 {"IRQHW3", 0x0B6E, 13, 0x0000},
\r\r
621 {"IRQHL3", 0x0B6F, 13, 0x0000},
\r\r
622 // Global Counter/Timer
\r\r
623 {"CTGDINI", 0x0B80, 32, 0x00000000},
\r\r
624 {"CTGCTRL", 0x0B81, 12, 0xE3F},
\r\r
626 {"C08CPU0", 0x0C00, 32, 0x00000000},
\r\r
627 {"C09CPU0", 0x0C01, 32, 0x00000000},
\r\r
628 {"C10CPU0", 0x0C02, 32, 0x00000000},
\r\r
629 {"C11CPU0", 0x0C03, 32, 0x00000000},
\r\r
630 {"C12CPUA", 0x0C04, 32, 0x00000000},
\r\r
631 {"C13CPUA", 0x0C05, 32, 0x00000000},
\r\r
632 {"C14CPUA", 0x0C06, 32, 0x00000000},
\r\r
633 {"C15CPUA", 0x0C07, 32, 0x00000000},
\r\r
634 {"C08CPU1", 0x0C08, 32, 0x00000000},
\r\r
635 {"C09CPU1", 0x0C09, 32, 0x00000000},
\r\r
636 {"C10CPU1", 0x0C0A, 32, 0x00000000},
\r\r
637 {"C11CPU1", 0x0C0B, 32, 0x00000000},
\r\r
638 {"C08CPU2", 0x0C10, 32, 0x00000000},
\r\r
639 {"C09CPU2", 0x0C11, 32, 0x00000000},
\r\r
640 {"C10CPU2", 0x0C12, 32, 0x00000000},
\r\r
641 {"C11CPU2", 0x0C13, 32, 0x00000000},
\r\r
642 {"C08CPU3", 0x0C18, 32, 0x00000000},
\r\r
643 {"C09CPU3", 0x0C19, 32, 0x00000000},
\r\r
644 {"C10CPU3", 0x0C1A, 32, 0x00000000},
\r\r
645 {"C11CPU3", 0x0C1B, 32, 0x00000000},
\r\r
647 {"NMOD", 0x0D40, 6, 0x08},
\r\r
648 {"NDLY", 0x0D41, 30, 0x24924924},
\r\r
649 {"NED", 0x0D42, 16, 0xA240},
\r\r
650 {"NTRO", 0x0D43, 18, 0x3FFFC},
\r\r
651 {"NRRO", 0x0D44, 18, 0x3FFFC},
\r\r
653 {"NES", 0x0D45, 32, 0x00000000},
\r\r
654 {"NTP", 0x0D46, 32, 0x0000FFFF},
\r\r
655 {"NBND", 0x0D47, 16, 0x6020},
\r\r
656 {"NP0", 0x0D48, 11, 0x44C},
\r\r
657 {"NP1", 0x0D49, 11, 0x44C},
\r\r
658 {"NP2", 0x0D4A, 11, 0x44C},
\r\r
659 {"NP3", 0x0D4B, 11, 0x44C},
\r\r
660 {"NCUT", 0x0D4C, 32, 0xFFFFFFFF},
\r\r
661 // Filter and Preprocessor
\r\r
662 {"TPPT0", 0x3000, 7, 0x01},
\r\r
663 {"TPFS", 0x3001, 7, 0x05},
\r\r
664 {"TPFE", 0x3002, 7, 0x14},
\r\r
665 {"TPPGR", 0x3003, 7, 0x15},
\r\r
666 {"TPPAE", 0x3004, 7, 0x1E},
\r\r
667 {"TPQS0", 0x3005, 7, 0x00},
\r\r
668 {"TPQE0", 0x3006, 7, 0x0A},
\r\r
669 {"TPQS1", 0x3007, 7, 0x0B},
\r\r
670 {"TPQE1", 0x3008, 7, 0x14},
\r\r
671 {"EBD", 0x3009, 3, 0x0},
\r\r
672 {"EBAQA", 0x300A, 7, 0x00},
\r\r
673 {"EBSIA", 0x300B, 7, 0x20},
\r\r
674 {"EBSF", 0x300C, 1, 0x1},
\r\r
675 {"EBSIM", 0x300D, 1, 0x1},
\r\r
676 {"EBPP", 0x300E, 1, 0x1},
\r\r
677 {"EBPC", 0x300F, 1, 0x1},
\r\r
679 {"EBIS", 0x3014, 10, 0x005},
\r\r
680 {"EBIT", 0x3015, 12, 0x028},
\r\r
681 {"EBIL", 0x3016, 8, 0xF0},
\r\r
682 {"EBIN", 0x3017, 1, 0x1},
\r\r
683 {"FLBY", 0x3018, 1, 0x0},
\r\r
684 {"FPBY", 0x3019, 1, 0x0},
\r\r
685 {"FGBY", 0x301A, 1, 0x0},
\r\r
686 {"FTBY", 0x301B, 1, 0x0},
\r\r
687 {"FCBY", 0x301C, 1, 0x0},
\r\r
688 {"FPTC", 0x3020, 2, 0x3},
\r\r
689 {"FPNP", 0x3021, 9, 0x078},
\r\r
690 {"FPCL", 0x3022, 1, 0x1},
\r\r
691 {"FGTA", 0x3028, 12, 0x014},
\r\r
692 {"FGTB", 0x3029, 12, 0x80C},
\r\r
693 {"FGCL", 0x302A, 1, 0x1},
\r\r
694 {"FTAL", 0x3030, 10, 0x0F6},
\r\r
695 {"FTLL", 0x3031, 9, 0x11D},
\r\r
696 {"FTLS", 0x3032, 9, 0x0D3},
\r\r
697 {"FCW1", 0x3038, 8, 0x1E},
\r\r
698 {"FCW2", 0x3039, 8, 0xD4},
\r\r
699 {"FCW3", 0x303A, 8, 0xE6},
\r\r
700 {"FCW4", 0x303B, 8, 0x4A},
\r\r
701 {"FCW5", 0x303C, 8, 0xEF},
\r\r
702 {"TPFP", 0x3040, 9, 0x037},
\r\r
703 {"TPHT", 0x3041, 14, 0x00A0},
\r\r
705 {"TPVT", 0x3042, 6, 0x00},
\r\r
706 {"TPVBY", 0x3043, 1, 0x0},
\r\r
707 {"TPCT", 0x3044, 5, 0x08},
\r\r
708 {"TPCL", 0x3045, 5, 0x01},
\r\r
709 {"TPCBY", 0x3046, 1, 0x1},
\r\r
710 {"TPD", 0x3047, 4, 0xF},
\r\r
711 {"TPCI0", 0x3048, 5, 0x00},
\r\r
712 {"TPCI1", 0x3049, 5, 0x00},
\r\r
713 {"TPCI2", 0x304A, 5, 0x00},
\r\r
714 {"TPCI3", 0x304B, 5, 0x00},
\r\r
716 {"ADCMSK", 0x3050, 21, 0x1FFFFF},
\r\r
717 {"ADCINB", 0x3051, 2, 0x2},
\r\r
718 {"ADCDAC", 0x3052, 5, 0x10},
\r\r
719 {"ADCPAR", 0x3053, 18, 0x195EF},
\r\r
720 {"ADCTST", 0x3054, 2, 0x0},
\r\r
721 {"SADCAZ", 0x3055, 1, 0x1},
\r\r
723 {"FGF0", 0x3080, 9, 0x000},
\r\r
724 {"FGF1", 0x3081, 9, 0x000},
\r\r
725 {"FGF2", 0x3082, 9, 0x000},
\r\r
726 {"FGF3", 0x3083, 9, 0x000},
\r\r
727 {"FGF4", 0x3084, 9, 0x000},
\r\r
728 {"FGF5", 0x3085, 9, 0x000},
\r\r
729 {"FGF6", 0x3086, 9, 0x000},
\r\r
730 {"FGF7", 0x3087, 9, 0x000},
\r\r
731 {"FGF8", 0x3088, 9, 0x000},
\r\r
732 {"FGF9", 0x3089, 9, 0x000},
\r\r
733 {"FGF10", 0x308A, 9, 0x000},
\r\r
734 {"FGF11", 0x308B, 9, 0x000},
\r\r
735 {"FGF12", 0x308C, 9, 0x000},
\r\r
736 {"FGF13", 0x308D, 9, 0x000},
\r\r
737 {"FGF14", 0x308E, 9, 0x000},
\r\r
738 {"FGF15", 0x308F, 9, 0x000},
\r\r
739 {"FGF16", 0x3090, 9, 0x000},
\r\r
740 {"FGF17", 0x3091, 9, 0x000},
\r\r
741 {"FGF18", 0x3092, 9, 0x000},
\r\r
742 {"FGF19", 0x3093, 9, 0x000},
\r\r
743 {"FGF20", 0x3094, 9, 0x000},
\r\r
745 {"FGA0", 0x30A0, 6, 0x00},
\r\r
746 {"FGA1", 0x30A1, 6, 0x00},
\r\r
747 {"FGA2", 0x30A2, 6, 0x00},
\r\r
748 {"FGA3", 0x30A3, 6, 0x00},
\r\r
749 {"FGA4", 0x30A4, 6, 0x00},
\r\r
750 {"FGA5", 0x30A5, 6, 0x00},
\r\r
751 {"FGA6", 0x30A6, 6, 0x00},
\r\r
752 {"FGA7", 0x30A7, 6, 0x00},
\r\r
753 {"FGA8", 0x30A8, 6, 0x00},
\r\r
754 {"FGA9", 0x30A9, 6, 0x00},
\r\r
755 {"FGA10", 0x30AA, 6, 0x00},
\r\r
756 {"FGA11", 0x30AB, 6, 0x00},
\r\r
757 {"FGA12", 0x30AC, 6, 0x00},
\r\r
758 {"FGA13", 0x30AD, 6, 0x00},
\r\r
759 {"FGA14", 0x30AE, 6, 0x00},
\r\r
760 {"FGA15", 0x30AF, 6, 0x00},
\r\r
761 {"FGA16", 0x30B0, 6, 0x00},
\r\r
762 {"FGA17", 0x30B1, 6, 0x00},
\r\r
763 {"FGA18", 0x30B2, 6, 0x00},
\r\r
764 {"FGA19", 0x30B3, 6, 0x00},
\r\r
765 {"FGA20", 0x30B4, 6, 0x00},
\r\r
766 // non-linearity table, 64 x 6 bits
\r\r
767 {"FLL00", 0x3100, 6, 0x00},
\r\r
768 {"FLL01", 0x3101, 6, 0x00},
\r\r
769 {"FLL02", 0x3102, 6, 0x00},
\r\r
770 {"FLL03", 0x3103, 6, 0x00},
\r\r
771 {"FLL04", 0x3104, 6, 0x00},
\r\r
772 {"FLL05", 0x3105, 6, 0x00},
\r\r
773 {"FLL06", 0x3106, 6, 0x00},
\r\r
774 {"FLL07", 0x3107, 6, 0x00},
\r\r
775 {"FLL08", 0x3108, 6, 0x00},
\r\r
776 {"FLL09", 0x3109, 6, 0x00},
\r\r
777 {"FLL0A", 0x310A, 6, 0x00},
\r\r
778 {"FLL0B", 0x310B, 6, 0x00},
\r\r
779 {"FLL0C", 0x310C, 6, 0x00},
\r\r
780 {"FLL0D", 0x310D, 6, 0x00},
\r\r
781 {"FLL0E", 0x310E, 6, 0x00},
\r\r
782 {"FLL0F", 0x310F, 6, 0x00},
\r\r
783 {"FLL10", 0x3110, 6, 0x00},
\r\r
784 {"FLL11", 0x3111, 6, 0x00},
\r\r
785 {"FLL12", 0x3112, 6, 0x00},
\r\r
786 {"FLL13", 0x3113, 6, 0x00},
\r\r
787 {"FLL14", 0x3114, 6, 0x00},
\r\r
788 {"FLL15", 0x3115, 6, 0x00},
\r\r
789 {"FLL16", 0x3116, 6, 0x00},
\r\r
790 {"FLL17", 0x3117, 6, 0x00},
\r\r
791 {"FLL18", 0x3118, 6, 0x00},
\r\r
792 {"FLL19", 0x3119, 6, 0x00},
\r\r
793 {"FLL1A", 0x311A, 6, 0x00},
\r\r
794 {"FLL1B", 0x311B, 6, 0x00},
\r\r
795 {"FLL1C", 0x311C, 6, 0x00},
\r\r
796 {"FLL1D", 0x311D, 6, 0x00},
\r\r
797 {"FLL1E", 0x311E, 6, 0x00},
\r\r
798 {"FLL1F", 0x311F, 6, 0x00},
\r\r
799 {"FLL20", 0x3120, 6, 0x00},
\r\r
800 {"FLL21", 0x3121, 6, 0x00},
\r\r
801 {"FLL22", 0x3122, 6, 0x00},
\r\r
802 {"FLL23", 0x3123, 6, 0x00},
\r\r
803 {"FLL24", 0x3124, 6, 0x00},
\r\r
804 {"FLL25", 0x3125, 6, 0x00},
\r\r
805 {"FLL26", 0x3126, 6, 0x00},
\r\r
806 {"FLL27", 0x3127, 6, 0x00},
\r\r
807 {"FLL28", 0x3128, 6, 0x00},
\r\r
808 {"FLL29", 0x3129, 6, 0x00},
\r\r
809 {"FLL2A", 0x312A, 6, 0x00},
\r\r
810 {"FLL2B", 0x312B, 6, 0x00},
\r\r
811 {"FLL2C", 0x312C, 6, 0x00},
\r\r
812 {"FLL2D", 0x312D, 6, 0x00},
\r\r
813 {"FLL2E", 0x312E, 6, 0x00},
\r\r
814 {"FLL2F", 0x312F, 6, 0x00},
\r\r
815 {"FLL30", 0x3130, 6, 0x00},
\r\r
816 {"FLL31", 0x3131, 6, 0x00},
\r\r
817 {"FLL32", 0x3132, 6, 0x00},
\r\r
818 {"FLL33", 0x3133, 6, 0x00},
\r\r
819 {"FLL34", 0x3134, 6, 0x00},
\r\r
820 {"FLL35", 0x3135, 6, 0x00},
\r\r
821 {"FLL36", 0x3136, 6, 0x00},
\r\r
822 {"FLL37", 0x3137, 6, 0x00},
\r\r
823 {"FLL38", 0x3138, 6, 0x00},
\r\r
824 {"FLL39", 0x3139, 6, 0x00},
\r\r
825 {"FLL3A", 0x313A, 6, 0x00},
\r\r
826 {"FLL3B", 0x313B, 6, 0x00},
\r\r
827 {"FLL3C", 0x313C, 6, 0x00},
\r\r
828 {"FLL3D", 0x313D, 6, 0x00},
\r\r
829 {"FLL3E", 0x313E, 6, 0x00},
\r\r
830 {"FLL3F", 0x313F, 6, 0x00},
\r\r
831 // end of non-lin table
\r\r
832 {"PASADEL", 0x3158, 8, 0xFF},
\r\r
833 {"PASAPHA", 0x3159, 6, 0x3F},
\r\r
834 {"PASAPRA", 0x315A, 6, 0x0F},
\r\r
835 {"PASADAC", 0x315B, 8, 0x80},
\r\r
836 {"PASACHM", 0x315C, 19, 0x7FFFF},
\r\r
837 {"PASASTL", 0x315D, 8, 0xFF},
\r\r
838 {"PASAPR1", 0x315E, 1, 0x0},
\r\r
839 {"PASAPR0", 0x315F, 1, 0x0},
\r\r
840 {"SADCTRG", 0x3161, 1, 0x0},
\r\r
841 {"SADCRUN", 0x3162, 1, 0x0},
\r\r
842 {"SADCPWR", 0x3163, 3, 0x7},
\r\r
843 {"L0TSIM", 0x3165, 14, 0x0050},
\r\r
844 {"SADCEC", 0x3166, 7, 0x00},
\r\r
845 {"SADCMC", 0x3170, 8, 0xC0},
\r\r
846 {"SADCOC", 0x3171, 8, 0x19},
\r\r
847 {"SADCGTB", 0x3172, 32, 0x37737700},
\r\r
848 {"SEBDEN", 0x3178, 3, 0x0},
\r\r
849 {"SEBDOU", 0x3179, 3, 0x0},
\r\r
850 // pos table, 128 x 5 bits
\r\r
851 {"TPL00", 0x3180, 5, 0x00},
\r\r
852 {"TPL01", 0x3181, 5, 0x00},
\r\r
853 {"TPL02", 0x3182, 5, 0x00},
\r\r
854 {"TPL03", 0x3183, 5, 0x00},
\r\r
855 {"TPL04", 0x3184, 5, 0x00},
\r\r
856 {"TPL05", 0x3185, 5, 0x00},
\r\r
857 {"TPL06", 0x3186, 5, 0x00},
\r\r
858 {"TPL07", 0x3187, 5, 0x00},
\r\r
859 {"TPL08", 0x3188, 5, 0x00},
\r\r
860 {"TPL09", 0x3189, 5, 0x00},
\r\r
861 {"TPL0A", 0x318A, 5, 0x00},
\r\r
862 {"TPL0B", 0x318B, 5, 0x00},
\r\r
863 {"TPL0C", 0x318C, 5, 0x00},
\r\r
864 {"TPL0D", 0x318D, 5, 0x00},
\r\r
865 {"TPL0E", 0x318E, 5, 0x00},
\r\r
866 {"TPL0F", 0x318F, 5, 0x00},
\r\r
867 {"TPL10", 0x3190, 5, 0x00},
\r\r
868 {"TPL11", 0x3191, 5, 0x00},
\r\r
869 {"TPL12", 0x3192, 5, 0x00},
\r\r
870 {"TPL13", 0x3193, 5, 0x00},
\r\r
871 {"TPL14", 0x3194, 5, 0x00},
\r\r
872 {"TPL15", 0x3195, 5, 0x00},
\r\r
873 {"TPL16", 0x3196, 5, 0x00},
\r\r
874 {"TPL17", 0x3197, 5, 0x00},
\r\r
875 {"TPL18", 0x3198, 5, 0x00},
\r\r
876 {"TPL19", 0x3199, 5, 0x00},
\r\r
877 {"TPL1A", 0x319A, 5, 0x00},
\r\r
878 {"TPL1B", 0x319B, 5, 0x00},
\r\r
879 {"TPL1C", 0x319C, 5, 0x00},
\r\r
880 {"TPL1D", 0x319D, 5, 0x00},
\r\r
881 {"TPL1E", 0x319E, 5, 0x00},
\r\r
882 {"TPL1F", 0x319F, 5, 0x00},
\r\r
883 {"TPL20", 0x31A0, 5, 0x00},
\r\r
884 {"TPL21", 0x31A1, 5, 0x00},
\r\r
885 {"TPL22", 0x31A2, 5, 0x00},
\r\r
886 {"TPL23", 0x31A3, 5, 0x00},
\r\r
887 {"TPL24", 0x31A4, 5, 0x00},
\r\r
888 {"TPL25", 0x31A5, 5, 0x00},
\r\r
889 {"TPL26", 0x31A6, 5, 0x00},
\r\r
890 {"TPL27", 0x31A7, 5, 0x00},
\r\r
891 {"TPL28", 0x31A8, 5, 0x00},
\r\r
892 {"TPL29", 0x31A9, 5, 0x00},
\r\r
893 {"TPL2A", 0x31AA, 5, 0x00},
\r\r
894 {"TPL2B", 0x31AB, 5, 0x00},
\r\r
895 {"TPL2C", 0x31AC, 5, 0x00},
\r\r
896 {"TPL2D", 0x31AD, 5, 0x00},
\r\r
897 {"TPL2E", 0x31AE, 5, 0x00},
\r\r
898 {"TPL2F", 0x31AF, 5, 0x00},
\r\r
899 {"TPL30", 0x31B0, 5, 0x00},
\r\r
900 {"TPL31", 0x31B1, 5, 0x00},
\r\r
901 {"TPL32", 0x31B2, 5, 0x00},
\r\r
902 {"TPL33", 0x31B3, 5, 0x00},
\r\r
903 {"TPL34", 0x31B4, 5, 0x00},
\r\r
904 {"TPL35", 0x31B5, 5, 0x00},
\r\r
905 {"TPL36", 0x31B6, 5, 0x00},
\r\r
906 {"TPL37", 0x31B7, 5, 0x00},
\r\r
907 {"TPL38", 0x31B8, 5, 0x00},
\r\r
908 {"TPL39", 0x31B9, 5, 0x00},
\r\r
909 {"TPL3A", 0x31BA, 5, 0x00},
\r\r
910 {"TPL3B", 0x31BB, 5, 0x00},
\r\r
911 {"TPL3C", 0x31BC, 5, 0x00},
\r\r
912 {"TPL3D", 0x31BD, 5, 0x00},
\r\r
913 {"TPL3E", 0x31BE, 5, 0x00},
\r\r
914 {"TPL3F", 0x31BF, 5, 0x00},
\r\r
915 {"TPL40", 0x31C0, 5, 0x00},
\r\r
916 {"TPL41", 0x31C1, 5, 0x00},
\r\r
917 {"TPL42", 0x31C2, 5, 0x00},
\r\r
918 {"TPL43", 0x31C3, 5, 0x00},
\r\r
919 {"TPL44", 0x31C4, 5, 0x00},
\r\r
920 {"TPL45", 0x31C5, 5, 0x00},
\r\r
921 {"TPL46", 0x31C6, 5, 0x00},
\r\r
922 {"TPL47", 0x31C7, 5, 0x00},
\r\r
923 {"TPL48", 0x31C8, 5, 0x00},
\r\r
924 {"TPL49", 0x31C9, 5, 0x00},
\r\r
925 {"TPL4A", 0x31CA, 5, 0x00},
\r\r
926 {"TPL4B", 0x31CB, 5, 0x00},
\r\r
927 {"TPL4C", 0x31CC, 5, 0x00},
\r\r
928 {"TPL4D", 0x31CD, 5, 0x00},
\r\r
929 {"TPL4E", 0x31CE, 5, 0x00},
\r\r
930 {"TPL4F", 0x31CF, 5, 0x00},
\r\r
931 {"TPL50", 0x31D0, 5, 0x00},
\r\r
932 {"TPL51", 0x31D1, 5, 0x00},
\r\r
933 {"TPL52", 0x31D2, 5, 0x00},
\r\r
934 {"TPL53", 0x31D3, 5, 0x00},
\r\r
935 {"TPL54", 0x31D4, 5, 0x00},
\r\r
936 {"TPL55", 0x31D5, 5, 0x00},
\r\r
937 {"TPL56", 0x31D6, 5, 0x00},
\r\r
938 {"TPL57", 0x31D7, 5, 0x00},
\r\r
939 {"TPL58", 0x31D8, 5, 0x00},
\r\r
940 {"TPL59", 0x31D9, 5, 0x00},
\r\r
941 {"TPL5A", 0x31DA, 5, 0x00},
\r\r
942 {"TPL5B", 0x31DB, 5, 0x00},
\r\r
943 {"TPL5C", 0x31DC, 5, 0x00},
\r\r
944 {"TPL5D", 0x31DD, 5, 0x00},
\r\r
945 {"TPL5E", 0x31DE, 5, 0x00},
\r\r
946 {"TPL5F", 0x31DF, 5, 0x00},
\r\r
947 {"TPL60", 0x31E0, 5, 0x00},
\r\r
948 {"TPL61", 0x31E1, 5, 0x00},
\r\r
949 {"TPL62", 0x31E2, 5, 0x00},
\r\r
950 {"TPL63", 0x31E3, 5, 0x00},
\r\r
951 {"TPL64", 0x31E4, 5, 0x00},
\r\r
952 {"TPL65", 0x31E5, 5, 0x00},
\r\r
953 {"TPL66", 0x31E6, 5, 0x00},
\r\r
954 {"TPL67", 0x31E7, 5, 0x00},
\r\r
955 {"TPL68", 0x31E8, 5, 0x00},
\r\r
956 {"TPL69", 0x31E9, 5, 0x00},
\r\r
957 {"TPL6A", 0x31EA, 5, 0x00},
\r\r
958 {"TPL6B", 0x31EB, 5, 0x00},
\r\r
959 {"TPL6C", 0x31EC, 5, 0x00},
\r\r
960 {"TPL6D", 0x31ED, 5, 0x00},
\r\r
961 {"TPL6E", 0x31EE, 5, 0x00},
\r\r
962 {"TPL6F", 0x31EF, 5, 0x00},
\r\r
963 {"TPL70", 0x31F0, 5, 0x00},
\r\r
964 {"TPL71", 0x31F1, 5, 0x00},
\r\r
965 {"TPL72", 0x31F2, 5, 0x00},
\r\r
966 {"TPL73", 0x31F3, 5, 0x00},
\r\r
967 {"TPL74", 0x31F4, 5, 0x00},
\r\r
968 {"TPL75", 0x31F5, 5, 0x00},
\r\r
969 {"TPL76", 0x31F6, 5, 0x00},
\r\r
970 {"TPL77", 0x31F7, 5, 0x00},
\r\r
971 {"TPL78", 0x31F8, 5, 0x00},
\r\r
972 {"TPL79", 0x31F9, 5, 0x00},
\r\r
973 {"TPL7A", 0x31FA, 5, 0x00},
\r\r
974 {"TPL7B", 0x31FB, 5, 0x00},
\r\r
975 {"TPL7C", 0x31FC, 5, 0x00},
\r\r
976 {"TPL7D", 0x31FD, 5, 0x00},
\r\r
977 {"TPL7E", 0x31FE, 5, 0x00},
\r\r
978 {"TPL7F", 0x31FF, 5, 0x00},
\r\r
979 // end of pos table
\r\r
980 {"MEMRW", 0xD000, 7, 0x79},
\r\r
981 {"MEMCOR", 0xD001, 9, 0x000},
\r\r
982 {"DMDELA", 0xD002, 4, 0x8},
\r\r
983 {"DMDELS", 0xD003, 4, 0x8}
\r\r
986 const CmdRegs kCmdReg[NCMD] = {
\r\r
988 {"SMCMD" , 0x0A04},
\r\r
989 {"SMOFFON" , 0x0A05},
\r\r
990 {"SMON" , 0x0A06},
\r\r
991 {"SMOFF" , 0x0A07},
\r\r
992 {"CPU0SS" , 0x0A21},
\r\r
993 {"CPU1SS" , 0x0A23},
\r\r
994 {"CPU2SS" , 0x0A25},
\r\r
995 {"CPU3SS" , 0x0A27},
\r\r
996 {"NICLKSS" , 0x0A29},
\r\r
997 {"FILCLKSS", 0x0A2B},
\r\r
998 {"PRECLKSS", 0x0A2D},
\r\r
999 {"ADCENSS" , 0x0A2F},
\r\r
1000 {"NIODESS" , 0x0A31},
\r\r
1001 {"NIOCESS" , 0x0A33},
\r\r
1002 {"NIIDESS" , 0x0A35},
\r\r
1003 {"NIICESS" , 0x0A37}
\r\r
1006 const CmdRegs kRoReg[NRO] = {
\r\r
1008 {"NCTRL" , 0x0DC0},
\r\r
1009 {"NFE" , 0x0DC1},
\r\r
1010 {"NFSM" , 0x0DC2},
\r\r
1011 // event buffer parity violation counters
\r\r
1012 {"EBP0" , 0x3010},
\r\r
1013 {"EBP1" , 0x3011},
\r\r
1014 {"EBP2" , 0x3012},
\r\r
1015 {"EBP3" , 0x3013},
\r\r
1017 {"SADCC0" , 0x3168},
\r\r
1018 {"SADCC1" , 0x3169},
\r\r
1019 {"SADCC2" , 0x316A},
\r\r
1020 {"SADCC3" , 0x316B},
\r\r
1021 {"SADCC4" , 0x316C},
\r\r
1022 {"SADCC5" , 0x316D},
\r\r
1023 {"SADCC6" , 0x316E},
\r\r
1024 {"SADCC7" , 0x316F},
\r\r
1025 // hamming counters
\r\r
1026 {"HCNTI0" , 0xD010},
\r\r
1027 {"HCNTI1" , 0xD011},
\r\r
1028 {"HCNTI2" , 0xD012},
\r\r
1029 {"HCNTI3" , 0xD013},
\r\r
1030 {"HCNTD0" , 0xD014},
\r\r
1031 {"HCNTD1" , 0xD015},
\r\r
1032 {"HCNTD2" , 0xD016},
\r\r
1033 {"HCNTD3" , 0xD017},
\r\r
1035 {"CHIPID" , 0x3160},
\r\r
1037 {"SEBDIN" , 0x317A}
\r\r
1041 for (Int_t i = 0; i < NREGS; i++) {
\r\r
1042 fTrapReg[i] = kTrapReg[i];
\r\r
1044 for (Int_t i = 0; i < NCMD; i++) {
\r\r
1045 fCmdReg[i] = kCmdReg[i];
\r\r
1047 for (Int_t i = 0; i < NRO; i++) {
\r\r
1048 fRoReg[i] = kRoReg[i];
\r\r