1 #/**************************************************************************
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2 * Copyright(c) 1998-1999, ALICE Experiment at CERN, All rights reserved. *
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4 * Author: The ALICE Off-line Project. *
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5 * Contributors are mentioned in the code where appropriate. *
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7 * Permission to use, copy, modify and distribute this software and its *
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8 * documentation strictly for non-commercial purposes is hereby granted *
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9 * without fee, provided that the above copyright notice appears in all *
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10 * copies and that both the copyright notice and this permission notice *
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11 * appear in the supporting documentation. The authors make no claims *
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12 * about the suitability of this software for any purpose. It is *
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13 * provided "as is" without express or implied warranty. *
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14 **************************************************************************/
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16 /* $Id: AliTRDrawTPStream.cxx 27797 2008-08-05 14:37:22Z cblume $ */
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18 ///////////////////////////////////////////////////////////////////////////////////////
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20 // This class provides access to pattern generated TRD raw data including //
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21 // configuration data. //
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23 // It is based on Venelin Angelov's c++ code decoding standalone //
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24 // configuration data //
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25 // http://alice.physi.uni-heidelberg.de/svn/trd/wconfigurations/trunk/C/trap_cnf.cpp //
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26 // http://alice.physi.uni-heidelberg.de/svn/trd/wconfigurations/trunk/C/trap_cnf.h //
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28 // Author: MinJung Kweon(minjung@physi.uni-heidelberg.de) //
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30 ///////////////////////////////////////////////////////////////////////////////////////
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34 #include "AliTRDrawStream.h"
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35 #include "AliTRDrawTPStream.h"
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38 #define GET_VALUE_AT(w,m,s) (( (w) >> (s)) & (m) )
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39 #define MCM_HEADER_MASK_ERR(w) ( ((w) & (0xf)) == (0xc) ? 0 : 1)
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40 #define MCM_ROB_NUMBER(w) GET_VALUE_AT(w,0x7,28)
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41 #define MCM_MCM_NUMBER(w) GET_VALUE_AT(w,0x0f,24)
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42 #define MCM_EVENT_COUNTER(w) GET_VALUE_AT(w,0x00fffff,4)
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46 ClassImp(AliTRDrawTPStream)
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48 //---------------------------------------------------------------------
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49 AliTRDrawTPStream::AliTRDrawTPStream(Int_t rawVMajorOpt, UInt_t * pPos)
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50 : AliTRDrawStreamBase()
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61 , fRawVMajorOpt(rawVMajorOpt)
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64 // default constructor
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67 if (FillConfig() == kFALSE)
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68 AliError("Reading reset value failed.");
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72 //---------------------------------------------------------------------
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73 AliTRDrawTPStream::AliTRDrawTPStream(const AliTRDrawTPStream& /*st*/)
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74 : AliTRDrawStreamBase()
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91 AliError("Not implemeneted.");
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95 //---------------------------------------------------------------------
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97 AliTRDrawTPStream::operator=(const AliTRDrawTPStream &)
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100 // we are not using this functionality
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102 AliFatal("May not use.");
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106 //---------------------------------------------------------------------
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107 AliTRDrawTPStream::~AliTRDrawTPStream()
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114 //---------------------------------------------------------------------
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115 Bool_t AliTRDrawTPStream::DecodeTPdata()
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118 // main function to decode test pattern data
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119 // fRawVMajorOpt version control different type of test pattern data
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122 if (fRawVMajorOpt == 7)
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124 AliInfo("This is configuration data event read by first trigger.");
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125 if(!AliTRDrawStream::fgEnableDecodeConfigData) return kTRUE;
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126 if (DecodeConfigdata() == kFALSE) // configuration data
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128 AliError("failed to to decode configuration data");
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135 AliError("These are different type of test pattern data. You need other reader");
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140 //---------------------------------------------------------------------
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141 Bool_t AliTRDrawTPStream::DecodeConfigdata()
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144 // main function to decode trap configuration data
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147 UInt_t packedConf[256];
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148 Int_t mcmPos, mcmsRead, lengthPacked;
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153 mcmPos = ReadPacked(fpPos, packedConf, &lengthPacked);
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157 UnPackConfN(packedConf, lengthPacked);
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160 AliInfo(Form("%d MCMs read up to now, last was MCM%02d\n",mcmsRead, mcmPos));
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162 } while ((mcmsRead < 84) && (mcmPos >= 0)); // [mj] have to think about # of mcmsRead
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168 //---------------------------------------------------------------------
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169 Int_t AliTRDrawTPStream::ReadPacked(UInt_t *word, UInt_t *pData, Int_t * const nWords)
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172 // decode packed data words
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175 UInt_t vword = *word;
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178 UInt_t err, robNum, mcmNum, chipId, noEndMarker;
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183 // decode mcm header
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184 if(MCM_HEADER_MASK_ERR(vword)) err++;
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186 robNum = MCM_ROB_NUMBER(vword);
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187 mcmNum = MCM_MCM_NUMBER(vword);
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188 chipId = MCM_EVENT_COUNTER(vword);
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191 AliInfo(Form("MCM header ROB %d, MCM %02d, ChipId %d 0x%05x\n", robNum, mcmNum, chipId, chipId));
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196 // read MCM data and store into array
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203 noEndMarker = ((vword != ENDM_CONF) && (vword != (ENDM_CONF | 1)) && (vword != 0x10001000));
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207 } while (noEndMarker && (iLength < 256));
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219 //---------------------------------------------------------------------
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220 void AliTRDrawTPStream::PowerUp() // power up
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223 // copy the reset values
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224 for (Int_t i=0; i< NREGS; i++)
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226 fRegs[i] = fTrapReg[i].fResVal;
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229 // mark all DMEM cells as invalid
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230 for (Int_t i=0; i< NDMEM; i++) fDmemValid[i] = 0;
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231 // mark all DBANK cells as empty
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232 for (Int_t i=0; i< NDBANK; i++) fDbankPro[i] = kDbankEmpty;
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236 //---------------------------------------------------------------------
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237 Int_t AliTRDrawTPStream::UnPackConfN(const UInt_t *pData, Int_t maxLength)
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241 Int_t debug = 0; // the debug mode not completely ready
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242 Int_t step, bwidth, nwords, idx, err, exitFlag, bitcnt, werr;
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244 UInt_t dat, msk, header, dataHi;
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246 idx = 0; // index in PackedConf
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248 while (idx < maxLength)
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251 if (debug) printf("read 0x%08x ",header);
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254 if (header & 0x01) // single data
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256 dat = (header >> 2) & 0xFFFF; // 16 bit data
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257 caddr = (header >> 18) & 0x3FFF; // 14 bit address
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258 if (caddr != 0x1FFF) // temp!!! because the end marker was wrong
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260 if (header & 0x02) // check if > 16 bits
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263 if (debug) printf("read 0x%08x ",dataHi);
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266 err += ((dataHi ^ (dat | 1)) & 0xFFFF) != 0;
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267 dat = (dataHi & 0xFFFF0000) | dat;
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269 if (debug) printf("addr=0x%04x (%s) data=0x%08x\n",caddr, Addr2Name(caddr), dat);
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270 werr = SetU(caddr, dat);
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273 printf("(single-write): non-existing address 0x%04x containing 0x%08x\n", caddr, header);
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275 if (idx > maxLength)
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277 printf("(single-write): no more data, missing end marker\n");
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283 printf("(single-write): address 0x%04x => old endmarker?\n",caddr);
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287 else // block of data
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289 step = (header >> 1) & 0x0003;
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290 bwidth = ((header >> 3) & 0x001F) + 1;
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291 nwords = (header >> 8) & 0x00FF;
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292 caddr = (header >> 16) & 0xFFFF;
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293 exitFlag = (step == 0) || (step == 3) || (nwords == 0);
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294 if (exitFlag) return err;
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303 msk = (1 << bwidth) - 1;
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312 if (debug) printf("read 0x%08x ",header);
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315 err += (header & 1);
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316 header = header >> 1;
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317 bitcnt = 31 - bwidth;
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319 if (debug) printf("addr=0x%04x (%s) data=0x%08x\n",caddr, Addr2Name(caddr), header & msk);
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320 werr = SetU(caddr, header & msk);
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323 printf("(single-write): non-existing address 0x%04x containing 0x%08x\n", caddr, header);
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326 header = header >> bwidth;
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327 if (idx >= maxLength)
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329 printf("(block-write): no end marker! %d words read\n",idx);
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340 if (debug) printf("read 0x%08x ",header);
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344 err += (header & 1);
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345 if (debug) printf("addr=0x%04x (%s) data=0x%08x\n",caddr, Addr2Name(caddr), header >> 1);
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346 werr = SetU(caddr, header >> 1);
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349 printf("(single-write): non-existing address 0x%04x containing 0x%08x\n", caddr, header);
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352 if (idx >= maxLength)
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354 printf("no end marker! %d words read\n",idx);
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360 default: return err;
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362 } // end block case
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364 printf("no end marker! %d words read\n",idx);
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365 return -err; // only if the max length of the block reached!
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368 //---------------------------------------------------------------------
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369 void AliTRDrawTPStream::DumpCnf(Int_t slv)
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373 for (idx = 0; idx < NREGS; idx++) // config. reg
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376 printf("%s\t0x%08x\t%3d %c\n", fTrapReg[idx].fName, (Int_t) fRegs[idx], slv, CnfStat(fCnfPro[idx]));
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378 printf("%s\t0x%08x %c\n", fTrapReg[idx].fName, (Int_t) fRegs[idx], CnfStat(fCnfPro[idx]));
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383 //---------------------------------------------------------------------
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384 const Char_t * AliTRDrawTPStream::Addr2Name(UInt_t addr) const
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389 if ( ( ( (addr >> 4) & 0xFFE) == 0x0C0) && ( ( (addr >> 2) & 1) == 1) )
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391 addr = addr & 0x0C07;
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393 while ((idx < NREGS) && (fTrapReg[idx].fAddr != addr) ) idx++;
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395 return fTrapReg[idx].fName;
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397 while ((idx < NCMD) && (fCmdReg[idx].fAddr != addr)) idx++;
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399 return fCmdReg[idx].fName;
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401 while ((idx < NRO) && (fRoReg[idx].fAddr != addr)) idx++;
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403 return fRoReg[idx].fName;
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408 //---------------------------------------------------------------------
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409 Char_t AliTRDrawTPStream::CnfStat(UInt_t prop) const
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412 if (prop == 0) return 'U';
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414 if (prop == 1) return 'R';
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416 if (prop == 2) return 'I';
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421 //---------------------------------------------------------------------
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422 Int_t AliTRDrawTPStream::SetU(UInt_t addr, UInt_t newVal)
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428 if (AddrIsDmem(addr))
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430 fDmem[addr & 0x3FF] = newVal;
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431 fDmemValid[addr & 0x3FF] = 1;
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435 if (AddrIsDbank(addr))
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437 fDbank[addr & 0xFF] = newVal;
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438 fDbankPro[addr & 0xFF] = kScsnDat;
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443 i = Addr2Idx(addr);
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444 if (i < NREGS) // found
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447 if (fTrapReg[i].fNbits < 32) // create the max value from the number of bits
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450 maxVal = (maxVal << fTrapReg[i].fNbits) - 1;
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452 if ( (fTrapReg[i].fNbits == 32) || (newVal <= maxVal) ) // in range
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459 fRegs[i] = newVal & maxVal;
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460 printf("Out of range, writing 0x%08x to %d bits at addr = 0x%04x\n",newVal, fTrapReg[i].fNbits, addr);
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466 printf("(SetU): No such address, writing 0x%08x to addr = 0x%04x\n",newVal, addr);
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467 return -1; // no such address
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472 //---------------------------------------------------------------------
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473 Int_t AliTRDrawTPStream::AddrIsDmem(UInt_t addr) const
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475 addr = (addr >> 10);
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476 return (addr == 0x30);
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479 //---------------------------------------------------------------------
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480 Int_t AliTRDrawTPStream::AddrIsDbank(UInt_t addr) const
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482 addr = (addr >> 8);
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483 return (addr == 0xF0);
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486 //---------------------------------------------------------------------
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487 UInt_t AliTRDrawTPStream::Addr2Idx(UInt_t addr) const
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492 // check if global const
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493 if ( ( ( (addr >> 4) & 0xFFE) == 0x0C0) && ( ( (addr >> 2) & 1) == 1) )
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495 addr = addr & 0x0C07;
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498 while ((idx < NREGS) && (fTrapReg[idx].fAddr != addr)) idx++;
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499 // printf("Addr = 0x%04x; Idx = %d\n",addr, idx); // debugging
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503 //---------------------------------------------------------------------
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504 Bool_t AliTRDrawTPStream::FillConfig()
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506 // fill array with configuraiton information
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508 const SimpleRegs kTrapReg[NREGS] = {
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509 // Name Address Nbits Reset Value
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510 // Global state machine
\r
511 {"SML0", 0x0A00, 15, 0x4050},
\r
512 {"SML1", 0x0A01, 15, 0x4200},
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513 {"SML2", 0x0A02, 15, 0x4384},
\r
514 {"SMMODE", 0x0A03, 16, 0xF0E2},
\r
515 {"NITM0", 0x0A08, 14, 0x3FFF},
\r
516 {"NITM1", 0x0A09, 14, 0x3FFF},
\r
517 {"NITM2", 0x0A0A, 14, 0x3FFF},
\r
518 {"NIP4D", 0x0A0B, 7, 0x7F},
\r
519 {"CPU0CLK", 0x0A20, 5, 0x07},
\r
520 {"CPU1CLK", 0x0A22, 5, 0x07},
\r
521 {"CPU2CLK", 0x0A24, 5, 0x07},
\r
522 {"CPU3CLK", 0x0A26, 5, 0x07},
\r
523 {"NICLK", 0x0A28, 5, 0x07},
\r
524 {"FILCLK", 0x0A2A, 5, 0x07},
\r
525 {"PRECLK", 0x0A2C, 5, 0x07},
\r
526 {"ADCEN", 0x0A2E, 5, 0x07},
\r
527 {"NIODE", 0x0A30, 5, 0x07},
\r
528 {"NIOCE", 0x0A32, 5, 0x21}, // bit 5 is status bit (read-only)!
\r
529 {"NIIDE", 0x0A34, 5, 0x07},
\r
530 {"NIICE", 0x0A36, 5, 0x07},
\r
532 {"ARBTIM", 0x0A3F, 4, 0x0},
\r
534 {"IA0IRQ0", 0x0B00, 12, 0x000},
\r
535 {"IA0IRQ1", 0x0B01, 12, 0x000},
\r
536 {"IA0IRQ2", 0x0B02, 12, 0x000},
\r
537 {"IA0IRQ3", 0x0B03, 12, 0x000},
\r
538 {"IA0IRQ4", 0x0B04, 12, 0x000},
\r
539 {"IA0IRQ5", 0x0B05, 12, 0x000},
\r
540 {"IA0IRQ6", 0x0B06, 12, 0x000},
\r
541 {"IA0IRQ7", 0x0B07, 12, 0x000},
\r
542 {"IA0IRQ8", 0x0B08, 12, 0x000},
\r
543 {"IA0IRQ9", 0x0B09, 12, 0x000},
\r
544 {"IA0IRQA", 0x0B0A, 12, 0x000},
\r
545 {"IA0IRQB", 0x0B0B, 12, 0x000},
\r
546 {"IA0IRQC", 0x0B0C, 12, 0x000},
\r
547 {"IRQSW0", 0x0B0D, 13, 0x1FFF},
\r
548 {"IRQHW0", 0x0B0E, 13, 0x0000},
\r
549 {"IRQHL0", 0x0B0F, 13, 0x0000},
\r
551 {"IA1IRQ0", 0x0B20, 12, 0x000},
\r
552 {"IA1IRQ1", 0x0B21, 12, 0x000},
\r
553 {"IA1IRQ2", 0x0B22, 12, 0x000},
\r
554 {"IA1IRQ3", 0x0B23, 12, 0x000},
\r
555 {"IA1IRQ4", 0x0B24, 12, 0x000},
\r
556 {"IA1IRQ5", 0x0B25, 12, 0x000},
\r
557 {"IA1IRQ6", 0x0B26, 12, 0x000},
\r
558 {"IA1IRQ7", 0x0B27, 12, 0x000},
\r
559 {"IA1IRQ8", 0x0B28, 12, 0x000},
\r
560 {"IA1IRQ9", 0x0B29, 12, 0x000},
\r
561 {"IA1IRQA", 0x0B2A, 12, 0x000},
\r
562 {"IA1IRQB", 0x0B2B, 12, 0x000},
\r
563 {"IA1IRQC", 0x0B2C, 12, 0x000},
\r
564 {"IRQSW1", 0x0B2D, 13, 0x1FFF},
\r
565 {"IRQHW1", 0x0B2E, 13, 0x0000},
\r
566 {"IRQHL1", 0x0B2F, 13, 0x0000},
\r
568 {"IA2IRQ0", 0x0B40, 12, 0x000},
\r
569 {"IA2IRQ1", 0x0B41, 12, 0x000},
\r
570 {"IA2IRQ2", 0x0B42, 12, 0x000},
\r
571 {"IA2IRQ3", 0x0B43, 12, 0x000},
\r
572 {"IA2IRQ4", 0x0B44, 12, 0x000},
\r
573 {"IA2IRQ5", 0x0B45, 12, 0x000},
\r
574 {"IA2IRQ6", 0x0B46, 12, 0x000},
\r
575 {"IA2IRQ7", 0x0B47, 12, 0x000},
\r
576 {"IA2IRQ8", 0x0B48, 12, 0x000},
\r
577 {"IA2IRQ9", 0x0B49, 12, 0x000},
\r
578 {"IA2IRQA", 0x0B4A, 12, 0x000},
\r
579 {"IA2IRQB", 0x0B4B, 12, 0x000},
\r
580 {"IA2IRQC", 0x0B4C, 12, 0x000},
\r
581 {"IRQSW2", 0x0B4D, 13, 0x1FFF},
\r
582 {"IRQHW2", 0x0B4E, 13, 0x0000},
\r
583 {"IRQHL2", 0x0B4F, 13, 0x0000},
\r
585 {"IA3IRQ0", 0x0B60, 12, 0x000},
\r
586 {"IA3IRQ1", 0x0B61, 12, 0x000},
\r
587 {"IA3IRQ2", 0x0B62, 12, 0x000},
\r
588 {"IA3IRQ3", 0x0B63, 12, 0x000},
\r
589 {"IA3IRQ4", 0x0B64, 12, 0x000},
\r
590 {"IA3IRQ5", 0x0B65, 12, 0x000},
\r
591 {"IA3IRQ6", 0x0B66, 12, 0x000},
\r
592 {"IA3IRQ7", 0x0B67, 12, 0x000},
\r
593 {"IA3IRQ8", 0x0B68, 12, 0x000},
\r
594 {"IA3IRQ9", 0x0B69, 12, 0x000},
\r
595 {"IA3IRQA", 0x0B6A, 12, 0x000},
\r
596 {"IA3IRQB", 0x0B6B, 12, 0x000},
\r
597 {"IA3IRQC", 0x0B6C, 12, 0x000},
\r
598 {"IRQSW3", 0x0B6D, 13, 0x1FFF},
\r
599 {"IRQHW3", 0x0B6E, 13, 0x0000},
\r
600 {"IRQHL3", 0x0B6F, 13, 0x0000},
\r
601 // Global Counter/Timer
\r
602 {"CTGDINI", 0x0B80, 32, 0x00000000},
\r
603 {"CTGCTRL", 0x0B81, 12, 0xE3F},
\r
605 {"C08CPU0", 0x0C00, 32, 0x00000000},
\r
606 {"C09CPU0", 0x0C01, 32, 0x00000000},
\r
607 {"C10CPU0", 0x0C02, 32, 0x00000000},
\r
608 {"C11CPU0", 0x0C03, 32, 0x00000000},
\r
609 {"C12CPUA", 0x0C04, 32, 0x00000000},
\r
610 {"C13CPUA", 0x0C05, 32, 0x00000000},
\r
611 {"C14CPUA", 0x0C06, 32, 0x00000000},
\r
612 {"C15CPUA", 0x0C07, 32, 0x00000000},
\r
613 {"C08CPU1", 0x0C08, 32, 0x00000000},
\r
614 {"C09CPU1", 0x0C09, 32, 0x00000000},
\r
615 {"C10CPU1", 0x0C0A, 32, 0x00000000},
\r
616 {"C11CPU1", 0x0C0B, 32, 0x00000000},
\r
617 {"C08CPU2", 0x0C10, 32, 0x00000000},
\r
618 {"C09CPU2", 0x0C11, 32, 0x00000000},
\r
619 {"C10CPU2", 0x0C12, 32, 0x00000000},
\r
620 {"C11CPU2", 0x0C13, 32, 0x00000000},
\r
621 {"C08CPU3", 0x0C18, 32, 0x00000000},
\r
622 {"C09CPU3", 0x0C19, 32, 0x00000000},
\r
623 {"C10CPU3", 0x0C1A, 32, 0x00000000},
\r
624 {"C11CPU3", 0x0C1B, 32, 0x00000000},
\r
626 {"NMOD", 0x0D40, 6, 0x08},
\r
627 {"NDLY", 0x0D41, 30, 0x24924924},
\r
628 {"NED", 0x0D42, 16, 0xA240},
\r
629 {"NTRO", 0x0D43, 18, 0x3FFFC},
\r
630 {"NRRO", 0x0D44, 18, 0x3FFFC},
\r
632 {"NES", 0x0D45, 32, 0x00000000},
\r
633 {"NTP", 0x0D46, 32, 0x0000FFFF},
\r
634 {"NBND", 0x0D47, 16, 0x6020},
\r
635 {"NP0", 0x0D48, 11, 0x44C},
\r
636 {"NP1", 0x0D49, 11, 0x44C},
\r
637 {"NP2", 0x0D4A, 11, 0x44C},
\r
638 {"NP3", 0x0D4B, 11, 0x44C},
\r
639 {"NCUT", 0x0D4C, 32, 0xFFFFFFFF},
\r
640 // Filter and Preprocessor
\r
641 {"TPPT0", 0x3000, 7, 0x01},
\r
642 {"TPFS", 0x3001, 7, 0x05},
\r
643 {"TPFE", 0x3002, 7, 0x14},
\r
644 {"TPPGR", 0x3003, 7, 0x15},
\r
645 {"TPPAE", 0x3004, 7, 0x1E},
\r
646 {"TPQS0", 0x3005, 7, 0x00},
\r
647 {"TPQE0", 0x3006, 7, 0x0A},
\r
648 {"TPQS1", 0x3007, 7, 0x0B},
\r
649 {"TPQE1", 0x3008, 7, 0x14},
\r
650 {"EBD", 0x3009, 3, 0x0},
\r
651 {"EBAQA", 0x300A, 7, 0x00},
\r
652 {"EBSIA", 0x300B, 7, 0x20},
\r
653 {"EBSF", 0x300C, 1, 0x1},
\r
654 {"EBSIM", 0x300D, 1, 0x1},
\r
655 {"EBPP", 0x300E, 1, 0x1},
\r
656 {"EBPC", 0x300F, 1, 0x1},
\r
658 {"EBIS", 0x3014, 10, 0x005},
\r
659 {"EBIT", 0x3015, 12, 0x028},
\r
660 {"EBIL", 0x3016, 8, 0xF0},
\r
661 {"EBIN", 0x3017, 1, 0x1},
\r
662 {"FLBY", 0x3018, 1, 0x0},
\r
663 {"FPBY", 0x3019, 1, 0x0},
\r
664 {"FGBY", 0x301A, 1, 0x0},
\r
665 {"FTBY", 0x301B, 1, 0x0},
\r
666 {"FCBY", 0x301C, 1, 0x0},
\r
667 {"FPTC", 0x3020, 2, 0x3},
\r
668 {"FPNP", 0x3021, 9, 0x078},
\r
669 {"FPCL", 0x3022, 1, 0x1},
\r
670 {"FGTA", 0x3028, 12, 0x014},
\r
671 {"FGTB", 0x3029, 12, 0x80C},
\r
672 {"FGCL", 0x302A, 1, 0x1},
\r
673 {"FTAL", 0x3030, 10, 0x0F6},
\r
674 {"FTLL", 0x3031, 9, 0x11D},
\r
675 {"FTLS", 0x3032, 9, 0x0D3},
\r
676 {"FCW1", 0x3038, 8, 0x1E},
\r
677 {"FCW2", 0x3039, 8, 0xD4},
\r
678 {"FCW3", 0x303A, 8, 0xE6},
\r
679 {"FCW4", 0x303B, 8, 0x4A},
\r
680 {"FCW5", 0x303C, 8, 0xEF},
\r
681 {"TPFP", 0x3040, 9, 0x037},
\r
682 {"TPHT", 0x3041, 14, 0x00A0},
\r
684 {"TPVT", 0x3042, 6, 0x00},
\r
685 {"TPVBY", 0x3043, 1, 0x0},
\r
686 {"TPCT", 0x3044, 5, 0x08},
\r
687 {"TPCL", 0x3045, 5, 0x01},
\r
688 {"TPCBY", 0x3046, 1, 0x1},
\r
689 {"TPD", 0x3047, 4, 0xF},
\r
690 {"TPCI0", 0x3048, 5, 0x00},
\r
691 {"TPCI1", 0x3049, 5, 0x00},
\r
692 {"TPCI2", 0x304A, 5, 0x00},
\r
693 {"TPCI3", 0x304B, 5, 0x00},
\r
695 {"ADCMSK", 0x3050, 21, 0x1FFFFF},
\r
696 {"ADCINB", 0x3051, 2, 0x2},
\r
697 {"ADCDAC", 0x3052, 5, 0x10},
\r
698 {"ADCPAR", 0x3053, 18, 0x195EF},
\r
699 {"ADCTST", 0x3054, 2, 0x0},
\r
700 {"SADCAZ", 0x3055, 1, 0x1},
\r
702 {"FGF0", 0x3080, 9, 0x000},
\r
703 {"FGF1", 0x3081, 9, 0x000},
\r
704 {"FGF2", 0x3082, 9, 0x000},
\r
705 {"FGF3", 0x3083, 9, 0x000},
\r
706 {"FGF4", 0x3084, 9, 0x000},
\r
707 {"FGF5", 0x3085, 9, 0x000},
\r
708 {"FGF6", 0x3086, 9, 0x000},
\r
709 {"FGF7", 0x3087, 9, 0x000},
\r
710 {"FGF8", 0x3088, 9, 0x000},
\r
711 {"FGF9", 0x3089, 9, 0x000},
\r
712 {"FGF10", 0x308A, 9, 0x000},
\r
713 {"FGF11", 0x308B, 9, 0x000},
\r
714 {"FGF12", 0x308C, 9, 0x000},
\r
715 {"FGF13", 0x308D, 9, 0x000},
\r
716 {"FGF14", 0x308E, 9, 0x000},
\r
717 {"FGF15", 0x308F, 9, 0x000},
\r
718 {"FGF16", 0x3090, 9, 0x000},
\r
719 {"FGF17", 0x3091, 9, 0x000},
\r
720 {"FGF18", 0x3092, 9, 0x000},
\r
721 {"FGF19", 0x3093, 9, 0x000},
\r
722 {"FGF20", 0x3094, 9, 0x000},
\r
724 {"FGA0", 0x30A0, 6, 0x00},
\r
725 {"FGA1", 0x30A1, 6, 0x00},
\r
726 {"FGA2", 0x30A2, 6, 0x00},
\r
727 {"FGA3", 0x30A3, 6, 0x00},
\r
728 {"FGA4", 0x30A4, 6, 0x00},
\r
729 {"FGA5", 0x30A5, 6, 0x00},
\r
730 {"FGA6", 0x30A6, 6, 0x00},
\r
731 {"FGA7", 0x30A7, 6, 0x00},
\r
732 {"FGA8", 0x30A8, 6, 0x00},
\r
733 {"FGA9", 0x30A9, 6, 0x00},
\r
734 {"FGA10", 0x30AA, 6, 0x00},
\r
735 {"FGA11", 0x30AB, 6, 0x00},
\r
736 {"FGA12", 0x30AC, 6, 0x00},
\r
737 {"FGA13", 0x30AD, 6, 0x00},
\r
738 {"FGA14", 0x30AE, 6, 0x00},
\r
739 {"FGA15", 0x30AF, 6, 0x00},
\r
740 {"FGA16", 0x30B0, 6, 0x00},
\r
741 {"FGA17", 0x30B1, 6, 0x00},
\r
742 {"FGA18", 0x30B2, 6, 0x00},
\r
743 {"FGA19", 0x30B3, 6, 0x00},
\r
744 {"FGA20", 0x30B4, 6, 0x00},
\r
745 // non-linearity table, 64 x 6 bits
\r
746 {"FLL00", 0x3100, 6, 0x00},
\r
747 {"FLL01", 0x3101, 6, 0x00},
\r
748 {"FLL02", 0x3102, 6, 0x00},
\r
749 {"FLL03", 0x3103, 6, 0x00},
\r
750 {"FLL04", 0x3104, 6, 0x00},
\r
751 {"FLL05", 0x3105, 6, 0x00},
\r
752 {"FLL06", 0x3106, 6, 0x00},
\r
753 {"FLL07", 0x3107, 6, 0x00},
\r
754 {"FLL08", 0x3108, 6, 0x00},
\r
755 {"FLL09", 0x3109, 6, 0x00},
\r
756 {"FLL0A", 0x310A, 6, 0x00},
\r
757 {"FLL0B", 0x310B, 6, 0x00},
\r
758 {"FLL0C", 0x310C, 6, 0x00},
\r
759 {"FLL0D", 0x310D, 6, 0x00},
\r
760 {"FLL0E", 0x310E, 6, 0x00},
\r
761 {"FLL0F", 0x310F, 6, 0x00},
\r
762 {"FLL10", 0x3110, 6, 0x00},
\r
763 {"FLL11", 0x3111, 6, 0x00},
\r
764 {"FLL12", 0x3112, 6, 0x00},
\r
765 {"FLL13", 0x3113, 6, 0x00},
\r
766 {"FLL14", 0x3114, 6, 0x00},
\r
767 {"FLL15", 0x3115, 6, 0x00},
\r
768 {"FLL16", 0x3116, 6, 0x00},
\r
769 {"FLL17", 0x3117, 6, 0x00},
\r
770 {"FLL18", 0x3118, 6, 0x00},
\r
771 {"FLL19", 0x3119, 6, 0x00},
\r
772 {"FLL1A", 0x311A, 6, 0x00},
\r
773 {"FLL1B", 0x311B, 6, 0x00},
\r
774 {"FLL1C", 0x311C, 6, 0x00},
\r
775 {"FLL1D", 0x311D, 6, 0x00},
\r
776 {"FLL1E", 0x311E, 6, 0x00},
\r
777 {"FLL1F", 0x311F, 6, 0x00},
\r
778 {"FLL20", 0x3120, 6, 0x00},
\r
779 {"FLL21", 0x3121, 6, 0x00},
\r
780 {"FLL22", 0x3122, 6, 0x00},
\r
781 {"FLL23", 0x3123, 6, 0x00},
\r
782 {"FLL24", 0x3124, 6, 0x00},
\r
783 {"FLL25", 0x3125, 6, 0x00},
\r
784 {"FLL26", 0x3126, 6, 0x00},
\r
785 {"FLL27", 0x3127, 6, 0x00},
\r
786 {"FLL28", 0x3128, 6, 0x00},
\r
787 {"FLL29", 0x3129, 6, 0x00},
\r
788 {"FLL2A", 0x312A, 6, 0x00},
\r
789 {"FLL2B", 0x312B, 6, 0x00},
\r
790 {"FLL2C", 0x312C, 6, 0x00},
\r
791 {"FLL2D", 0x312D, 6, 0x00},
\r
792 {"FLL2E", 0x312E, 6, 0x00},
\r
793 {"FLL2F", 0x312F, 6, 0x00},
\r
794 {"FLL30", 0x3130, 6, 0x00},
\r
795 {"FLL31", 0x3131, 6, 0x00},
\r
796 {"FLL32", 0x3132, 6, 0x00},
\r
797 {"FLL33", 0x3133, 6, 0x00},
\r
798 {"FLL34", 0x3134, 6, 0x00},
\r
799 {"FLL35", 0x3135, 6, 0x00},
\r
800 {"FLL36", 0x3136, 6, 0x00},
\r
801 {"FLL37", 0x3137, 6, 0x00},
\r
802 {"FLL38", 0x3138, 6, 0x00},
\r
803 {"FLL39", 0x3139, 6, 0x00},
\r
804 {"FLL3A", 0x313A, 6, 0x00},
\r
805 {"FLL3B", 0x313B, 6, 0x00},
\r
806 {"FLL3C", 0x313C, 6, 0x00},
\r
807 {"FLL3D", 0x313D, 6, 0x00},
\r
808 {"FLL3E", 0x313E, 6, 0x00},
\r
809 {"FLL3F", 0x313F, 6, 0x00},
\r
810 // end of non-lin table
\r
811 {"PASADEL", 0x3158, 8, 0xFF},
\r
812 {"PASAPHA", 0x3159, 6, 0x3F},
\r
813 {"PASAPRA", 0x315A, 6, 0x0F},
\r
814 {"PASADAC", 0x315B, 8, 0x80},
\r
815 {"PASACHM", 0x315C, 19, 0x7FFFF},
\r
816 {"PASASTL", 0x315D, 8, 0xFF},
\r
817 {"PASAPR1", 0x315E, 1, 0x0},
\r
818 {"PASAPR0", 0x315F, 1, 0x0},
\r
819 {"SADCTRG", 0x3161, 1, 0x0},
\r
820 {"SADCRUN", 0x3162, 1, 0x0},
\r
821 {"SADCPWR", 0x3163, 3, 0x7},
\r
822 {"L0TSIM", 0x3165, 14, 0x0050},
\r
823 {"SADCEC", 0x3166, 7, 0x00},
\r
824 {"SADCMC", 0x3170, 8, 0xC0},
\r
825 {"SADCOC", 0x3171, 8, 0x19},
\r
826 {"SADCGTB", 0x3172, 32, 0x37737700},
\r
827 {"SEBDEN", 0x3178, 3, 0x0},
\r
828 {"SEBDOU", 0x3179, 3, 0x0},
\r
829 // pos table, 128 x 5 bits
\r
830 {"TPL00", 0x3180, 5, 0x00},
\r
831 {"TPL01", 0x3181, 5, 0x00},
\r
832 {"TPL02", 0x3182, 5, 0x00},
\r
833 {"TPL03", 0x3183, 5, 0x00},
\r
834 {"TPL04", 0x3184, 5, 0x00},
\r
835 {"TPL05", 0x3185, 5, 0x00},
\r
836 {"TPL06", 0x3186, 5, 0x00},
\r
837 {"TPL07", 0x3187, 5, 0x00},
\r
838 {"TPL08", 0x3188, 5, 0x00},
\r
839 {"TPL09", 0x3189, 5, 0x00},
\r
840 {"TPL0A", 0x318A, 5, 0x00},
\r
841 {"TPL0B", 0x318B, 5, 0x00},
\r
842 {"TPL0C", 0x318C, 5, 0x00},
\r
843 {"TPL0D", 0x318D, 5, 0x00},
\r
844 {"TPL0E", 0x318E, 5, 0x00},
\r
845 {"TPL0F", 0x318F, 5, 0x00},
\r
846 {"TPL10", 0x3190, 5, 0x00},
\r
847 {"TPL11", 0x3191, 5, 0x00},
\r
848 {"TPL12", 0x3192, 5, 0x00},
\r
849 {"TPL13", 0x3193, 5, 0x00},
\r
850 {"TPL14", 0x3194, 5, 0x00},
\r
851 {"TPL15", 0x3195, 5, 0x00},
\r
852 {"TPL16", 0x3196, 5, 0x00},
\r
853 {"TPL17", 0x3197, 5, 0x00},
\r
854 {"TPL18", 0x3198, 5, 0x00},
\r
855 {"TPL19", 0x3199, 5, 0x00},
\r
856 {"TPL1A", 0x319A, 5, 0x00},
\r
857 {"TPL1B", 0x319B, 5, 0x00},
\r
858 {"TPL1C", 0x319C, 5, 0x00},
\r
859 {"TPL1D", 0x319D, 5, 0x00},
\r
860 {"TPL1E", 0x319E, 5, 0x00},
\r
861 {"TPL1F", 0x319F, 5, 0x00},
\r
862 {"TPL20", 0x31A0, 5, 0x00},
\r
863 {"TPL21", 0x31A1, 5, 0x00},
\r
864 {"TPL22", 0x31A2, 5, 0x00},
\r
865 {"TPL23", 0x31A3, 5, 0x00},
\r
866 {"TPL24", 0x31A4, 5, 0x00},
\r
867 {"TPL25", 0x31A5, 5, 0x00},
\r
868 {"TPL26", 0x31A6, 5, 0x00},
\r
869 {"TPL27", 0x31A7, 5, 0x00},
\r
870 {"TPL28", 0x31A8, 5, 0x00},
\r
871 {"TPL29", 0x31A9, 5, 0x00},
\r
872 {"TPL2A", 0x31AA, 5, 0x00},
\r
873 {"TPL2B", 0x31AB, 5, 0x00},
\r
874 {"TPL2C", 0x31AC, 5, 0x00},
\r
875 {"TPL2D", 0x31AD, 5, 0x00},
\r
876 {"TPL2E", 0x31AE, 5, 0x00},
\r
877 {"TPL2F", 0x31AF, 5, 0x00},
\r
878 {"TPL30", 0x31B0, 5, 0x00},
\r
879 {"TPL31", 0x31B1, 5, 0x00},
\r
880 {"TPL32", 0x31B2, 5, 0x00},
\r
881 {"TPL33", 0x31B3, 5, 0x00},
\r
882 {"TPL34", 0x31B4, 5, 0x00},
\r
883 {"TPL35", 0x31B5, 5, 0x00},
\r
884 {"TPL36", 0x31B6, 5, 0x00},
\r
885 {"TPL37", 0x31B7, 5, 0x00},
\r
886 {"TPL38", 0x31B8, 5, 0x00},
\r
887 {"TPL39", 0x31B9, 5, 0x00},
\r
888 {"TPL3A", 0x31BA, 5, 0x00},
\r
889 {"TPL3B", 0x31BB, 5, 0x00},
\r
890 {"TPL3C", 0x31BC, 5, 0x00},
\r
891 {"TPL3D", 0x31BD, 5, 0x00},
\r
892 {"TPL3E", 0x31BE, 5, 0x00},
\r
893 {"TPL3F", 0x31BF, 5, 0x00},
\r
894 {"TPL40", 0x31C0, 5, 0x00},
\r
895 {"TPL41", 0x31C1, 5, 0x00},
\r
896 {"TPL42", 0x31C2, 5, 0x00},
\r
897 {"TPL43", 0x31C3, 5, 0x00},
\r
898 {"TPL44", 0x31C4, 5, 0x00},
\r
899 {"TPL45", 0x31C5, 5, 0x00},
\r
900 {"TPL46", 0x31C6, 5, 0x00},
\r
901 {"TPL47", 0x31C7, 5, 0x00},
\r
902 {"TPL48", 0x31C8, 5, 0x00},
\r
903 {"TPL49", 0x31C9, 5, 0x00},
\r
904 {"TPL4A", 0x31CA, 5, 0x00},
\r
905 {"TPL4B", 0x31CB, 5, 0x00},
\r
906 {"TPL4C", 0x31CC, 5, 0x00},
\r
907 {"TPL4D", 0x31CD, 5, 0x00},
\r
908 {"TPL4E", 0x31CE, 5, 0x00},
\r
909 {"TPL4F", 0x31CF, 5, 0x00},
\r
910 {"TPL50", 0x31D0, 5, 0x00},
\r
911 {"TPL51", 0x31D1, 5, 0x00},
\r
912 {"TPL52", 0x31D2, 5, 0x00},
\r
913 {"TPL53", 0x31D3, 5, 0x00},
\r
914 {"TPL54", 0x31D4, 5, 0x00},
\r
915 {"TPL55", 0x31D5, 5, 0x00},
\r
916 {"TPL56", 0x31D6, 5, 0x00},
\r
917 {"TPL57", 0x31D7, 5, 0x00},
\r
918 {"TPL58", 0x31D8, 5, 0x00},
\r
919 {"TPL59", 0x31D9, 5, 0x00},
\r
920 {"TPL5A", 0x31DA, 5, 0x00},
\r
921 {"TPL5B", 0x31DB, 5, 0x00},
\r
922 {"TPL5C", 0x31DC, 5, 0x00},
\r
923 {"TPL5D", 0x31DD, 5, 0x00},
\r
924 {"TPL5E", 0x31DE, 5, 0x00},
\r
925 {"TPL5F", 0x31DF, 5, 0x00},
\r
926 {"TPL60", 0x31E0, 5, 0x00},
\r
927 {"TPL61", 0x31E1, 5, 0x00},
\r
928 {"TPL62", 0x31E2, 5, 0x00},
\r
929 {"TPL63", 0x31E3, 5, 0x00},
\r
930 {"TPL64", 0x31E4, 5, 0x00},
\r
931 {"TPL65", 0x31E5, 5, 0x00},
\r
932 {"TPL66", 0x31E6, 5, 0x00},
\r
933 {"TPL67", 0x31E7, 5, 0x00},
\r
934 {"TPL68", 0x31E8, 5, 0x00},
\r
935 {"TPL69", 0x31E9, 5, 0x00},
\r
936 {"TPL6A", 0x31EA, 5, 0x00},
\r
937 {"TPL6B", 0x31EB, 5, 0x00},
\r
938 {"TPL6C", 0x31EC, 5, 0x00},
\r
939 {"TPL6D", 0x31ED, 5, 0x00},
\r
940 {"TPL6E", 0x31EE, 5, 0x00},
\r
941 {"TPL6F", 0x31EF, 5, 0x00},
\r
942 {"TPL70", 0x31F0, 5, 0x00},
\r
943 {"TPL71", 0x31F1, 5, 0x00},
\r
944 {"TPL72", 0x31F2, 5, 0x00},
\r
945 {"TPL73", 0x31F3, 5, 0x00},
\r
946 {"TPL74", 0x31F4, 5, 0x00},
\r
947 {"TPL75", 0x31F5, 5, 0x00},
\r
948 {"TPL76", 0x31F6, 5, 0x00},
\r
949 {"TPL77", 0x31F7, 5, 0x00},
\r
950 {"TPL78", 0x31F8, 5, 0x00},
\r
951 {"TPL79", 0x31F9, 5, 0x00},
\r
952 {"TPL7A", 0x31FA, 5, 0x00},
\r
953 {"TPL7B", 0x31FB, 5, 0x00},
\r
954 {"TPL7C", 0x31FC, 5, 0x00},
\r
955 {"TPL7D", 0x31FD, 5, 0x00},
\r
956 {"TPL7E", 0x31FE, 5, 0x00},
\r
957 {"TPL7F", 0x31FF, 5, 0x00},
\r
958 // end of pos table
\r
959 {"MEMRW", 0xD000, 7, 0x79},
\r
960 {"MEMCOR", 0xD001, 9, 0x000},
\r
961 {"DMDELA", 0xD002, 4, 0x8},
\r
962 {"DMDELS", 0xD003, 4, 0x8}
\r
965 const CmdRegs kCmdReg[NCMD] = {
\r
967 {"SMCMD" , 0x0A04},
\r
968 {"SMOFFON" , 0x0A05},
\r
970 {"SMOFF" , 0x0A07},
\r
971 {"CPU0SS" , 0x0A21},
\r
972 {"CPU1SS" , 0x0A23},
\r
973 {"CPU2SS" , 0x0A25},
\r
974 {"CPU3SS" , 0x0A27},
\r
975 {"NICLKSS" , 0x0A29},
\r
976 {"FILCLKSS", 0x0A2B},
\r
977 {"PRECLKSS", 0x0A2D},
\r
978 {"ADCENSS" , 0x0A2F},
\r
979 {"NIODESS" , 0x0A31},
\r
980 {"NIOCESS" , 0x0A33},
\r
981 {"NIIDESS" , 0x0A35},
\r
982 {"NIICESS" , 0x0A37}
\r
985 const CmdRegs kRoReg[NRO] = {
\r
987 {"NCTRL" , 0x0DC0},
\r
990 // event buffer parity violation counters
\r
996 {"SADCC0" , 0x3168},
\r
997 {"SADCC1" , 0x3169},
\r
998 {"SADCC2" , 0x316A},
\r
999 {"SADCC3" , 0x316B},
\r
1000 {"SADCC4" , 0x316C},
\r
1001 {"SADCC5" , 0x316D},
\r
1002 {"SADCC6" , 0x316E},
\r
1003 {"SADCC7" , 0x316F},
\r
1004 // hamming counters
\r
1005 {"HCNTI0" , 0xD010},
\r
1006 {"HCNTI1" , 0xD011},
\r
1007 {"HCNTI2" , 0xD012},
\r
1008 {"HCNTI3" , 0xD013},
\r
1009 {"HCNTD0" , 0xD014},
\r
1010 {"HCNTD1" , 0xD015},
\r
1011 {"HCNTD2" , 0xD016},
\r
1012 {"HCNTD3" , 0xD017},
\r
1014 {"CHIPID" , 0x3160},
\r
1016 {"SEBDIN" , 0x317A}
\r
1020 for (Int_t i = 0; i < NREGS; i++) {
\r
1021 fTrapReg[i] = kTrapReg[i];
\r
1023 for (Int_t i = 0; i < NCMD; i++) {
\r
1024 fCmdReg[i] = kCmdReg[i];
\r
1026 for (Int_t i = 0; i < NRO; i++) {
\r
1027 fRoReg[i] = kRoReg[i];
\r