TRD/AliTRDtrapConfig.cxx

   1 /**************************************************************************
   2  * Copyright(c) 1998-1999, ALICE Experiment at CERN, All rights reserved. *
   3  *                                                                        *
   4  * Author: The ALICE Off-line Project.                                    *
   5  * Contributors are mentioned in the code where appropriate.              *
   6  *                                                                        *
   7  * Permission to use, copy, modify and distribute this software and its   *
   8  * documentation strictly for non-commercial purposes is hereby granted   *
   9  * without fee, provided that the above copyright notice appears in all   *
  10  * copies and that both the copyright notice and this permission notice   *
  11  * appear in the supporting documentation. The authors make no claims     *
  12  * about the suitability of this software for any purpose. It is          *
  13  * provided "as is" without express or implied warranty.                  *
  14  **************************************************************************/
  15
  16 ////////////////////////////////////////////////////////////////////////////
  17 //                                                                        //
  18 //  TRAP config                                                           //
  19 //                                                                        //
  20 //  Author: J. Klein (Jochen.Klein@cern.ch)                               //
  21 //                                                                        //
  22 ////////////////////////////////////////////////////////////////////////////
  23
  24 #include "AliLog.h"
  25
  26 #include "AliTRDgeometry.h"
  27 #include "AliTRDfeeParam.h"
  28 #include "AliTRDtrapConfig.h"
  29 #include "AliTRDtrapConfigHandler.h"
  30
  31 #include <fstream>
  32 #include <iostream>
  33 #include <iomanip>
  34
  35 ClassImp(AliTRDtrapConfig)
  36
  37 AliTRDtrapConfig* AliTRDtrapConfig::fgInstance = 0x0;
  38 const Int_t AliTRDtrapConfig::fgkMaxMcm = AliTRDfeeParam::GetNmcmRob() + 2;
  39 const Int_t AliTRDtrapConfig::fgkDmemStartAddress = 0xc000;
  40
  41 AliTRDtrapConfig::AliTRDtrapConfig() :
  42   TObject(), fScaleQ0(0), fScaleQ1(0)
  43 {
  44   // default constructor, initializing array of TRAP registers
  45
  46   //                              Name          Address  Nbits   Reset Value
  47   fRegs[kSML0]    =   SimpleReg_t("SML0",        0x0A00, 15,     0x4050     );  // Global state machine
  48   fRegs[kSML1]    =   SimpleReg_t("SML1",        0x0A01, 15,     0x4200     );
  49   fRegs[kSML2]    =   SimpleReg_t("SML2",        0x0A02, 15,     0x4384     );
  50   fRegs[kSMMODE]  =   SimpleReg_t("SMMODE",      0x0A03, 16,     0xF0E2     );
  51   fRegs[kNITM0]   =   SimpleReg_t("NITM0",       0x0A08, 14,     0x3FFF     );
  52   fRegs[kNITM1]   =   SimpleReg_t("NITM1",       0x0A09, 14,     0x3FFF     );
  53   fRegs[kNITM2]   =   SimpleReg_t("NITM2",       0x0A0A, 14,     0x3FFF     );
  54   fRegs[kNIP4D]   =   SimpleReg_t("NIP4D",       0x0A0B, 7,      0x7F       );
  55   fRegs[kCPU0CLK] =   SimpleReg_t("CPU0CLK",     0x0A20, 5,      0x07       );
  56   fRegs[kCPU1CLK] =   SimpleReg_t("CPU1CLK",     0x0A22, 5,      0x07       );
  57   fRegs[kCPU2CLK] =   SimpleReg_t("CPU2CLK",     0x0A24, 5,      0x07       );
  58   fRegs[kCPU3CLK] =   SimpleReg_t("CPU3CLK",     0x0A26, 5,      0x07       );
  59   fRegs[kNICLK]   =   SimpleReg_t("NICLK",       0x0A28, 5,      0x07       );
  60   fRegs[kFILCLK]  =   SimpleReg_t("FILCLK",      0x0A2A, 5,      0x07       );
  61   fRegs[kPRECLK]  =   SimpleReg_t("PRECLK",      0x0A2C, 5,      0x07       );
  62   fRegs[kADCEN]   =   SimpleReg_t("ADCEN",       0x0A2E, 5,      0x07       );
  63   fRegs[kNIODE]   =   SimpleReg_t("NIODE",       0x0A30, 5,      0x07       );
  64   fRegs[kNIOCE]   =   SimpleReg_t("NIOCE",       0x0A32, 6,      0x21       );  // bit 5 is status bit (read-only)!
  65   fRegs[kNIIDE]   =   SimpleReg_t("NIIDE",       0x0A34, 5,      0x07       );
  66   fRegs[kNIICE]   =   SimpleReg_t("NIICE",       0x0A36, 5,      0x07       );
  67   fRegs[kARBTIM]  =   SimpleReg_t("ARBTIM",      0x0A3F, 4,      0x0        );  // Arbiter
  68   fRegs[kIA0IRQ0] =   SimpleReg_t("IA0IRQ0",     0x0B00, 12,     0x000      );  // IVT of CPU0
  69   fRegs[kIA0IRQ1] =   SimpleReg_t("IA0IRQ1",     0x0B01, 12,     0x000      );
  70   fRegs[kIA0IRQ2] =   SimpleReg_t("IA0IRQ2",     0x0B02, 12,     0x000      );
  71   fRegs[kIA0IRQ3] =   SimpleReg_t("IA0IRQ3",     0x0B03, 12,     0x000      );
  72   fRegs[kIA0IRQ4] =   SimpleReg_t("IA0IRQ4",     0x0B04, 12,     0x000      );
  73   fRegs[kIA0IRQ5] =   SimpleReg_t("IA0IRQ5",     0x0B05, 12,     0x000      );
  74   fRegs[kIA0IRQ6] =   SimpleReg_t("IA0IRQ6",     0x0B06, 12,     0x000      );
  75   fRegs[kIA0IRQ7] =   SimpleReg_t("IA0IRQ7",     0x0B07, 12,     0x000      );
  76   fRegs[kIA0IRQ8] =   SimpleReg_t("IA0IRQ8",     0x0B08, 12,     0x000      );
  77   fRegs[kIA0IRQ9] =   SimpleReg_t("IA0IRQ9",     0x0B09, 12,     0x000      );
  78   fRegs[kIA0IRQA] =   SimpleReg_t("IA0IRQA",     0x0B0A, 12,     0x000      );
  79   fRegs[kIA0IRQB] =   SimpleReg_t("IA0IRQB",     0x0B0B, 12,     0x000      );
  80   fRegs[kIA0IRQC] =   SimpleReg_t("IA0IRQC",     0x0B0C, 12,     0x000      );
  81   fRegs[kIRQSW0]  =   SimpleReg_t("IRQSW0",      0x0B0D, 13,     0x1FFF     );
  82   fRegs[kIRQHW0]  =   SimpleReg_t("IRQHW0",      0x0B0E, 13,     0x0000     );
  83   fRegs[kIRQHL0]  =   SimpleReg_t("IRQHL0",      0x0B0F, 13,     0x0000     );
  84   fRegs[kIA1IRQ0] =   SimpleReg_t("IA1IRQ0",     0x0B20, 12,     0x000      );  // IVT of CPU1
  85   fRegs[kIA1IRQ1] =   SimpleReg_t("IA1IRQ1",     0x0B21, 12,     0x000      );
  86   fRegs[kIA1IRQ2] =   SimpleReg_t("IA1IRQ2",     0x0B22, 12,     0x000      );
  87   fRegs[kIA1IRQ3] =   SimpleReg_t("IA1IRQ3",     0x0B23, 12,     0x000      );
  88   fRegs[kIA1IRQ4] =   SimpleReg_t("IA1IRQ4",     0x0B24, 12,     0x000      );
  89   fRegs[kIA1IRQ5] =   SimpleReg_t("IA1IRQ5",     0x0B25, 12,     0x000      );
  90   fRegs[kIA1IRQ6] =   SimpleReg_t("IA1IRQ6",     0x0B26, 12,     0x000      );
  91   fRegs[kIA1IRQ7] =   SimpleReg_t("IA1IRQ7",     0x0B27, 12,     0x000      );
  92   fRegs[kIA1IRQ8] =   SimpleReg_t("IA1IRQ8",     0x0B28, 12,     0x000      );
  93   fRegs[kIA1IRQ9] =   SimpleReg_t("IA1IRQ9",     0x0B29, 12,     0x000      );
  94   fRegs[kIA1IRQA] =   SimpleReg_t("IA1IRQA",     0x0B2A, 12,     0x000      );
  95   fRegs[kIA1IRQB] =   SimpleReg_t("IA1IRQB",     0x0B2B, 12,     0x000      );
  96   fRegs[kIA1IRQC] =   SimpleReg_t("IA1IRQC",     0x0B2C, 12,     0x000      );
  97   fRegs[kIRQSW1]  =   SimpleReg_t("IRQSW1",      0x0B2D, 13,     0x1FFF     );
  98   fRegs[kIRQHW1]  =   SimpleReg_t("IRQHW1",      0x0B2E, 13,     0x0000     );
  99   fRegs[kIRQHL1]  =   SimpleReg_t("IRQHL1",      0x0B2F, 13,     0x0000     );
 100   fRegs[kIA2IRQ0] =   SimpleReg_t("IA2IRQ0",     0x0B40, 12,     0x000      );  // IVT of CPU2
 101   fRegs[kIA2IRQ1] =   SimpleReg_t("IA2IRQ1",     0x0B41, 12,     0x000      );
 102   fRegs[kIA2IRQ2] =   SimpleReg_t("IA2IRQ2",     0x0B42, 12,     0x000      );
 103   fRegs[kIA2IRQ3] =   SimpleReg_t("IA2IRQ3",     0x0B43, 12,     0x000      );
 104   fRegs[kIA2IRQ4] =   SimpleReg_t("IA2IRQ4",     0x0B44, 12,     0x000      );
 105   fRegs[kIA2IRQ5] =   SimpleReg_t("IA2IRQ5",     0x0B45, 12,     0x000      );
 106   fRegs[kIA2IRQ6] =   SimpleReg_t("IA2IRQ6",     0x0B46, 12,     0x000      );
 107   fRegs[kIA2IRQ7] =   SimpleReg_t("IA2IRQ7",     0x0B47, 12,     0x000      );
 108   fRegs[kIA2IRQ8] =   SimpleReg_t("IA2IRQ8",     0x0B48, 12,     0x000      );
 109   fRegs[kIA2IRQ9] =   SimpleReg_t("IA2IRQ9",     0x0B49, 12,     0x000      );
 110   fRegs[kIA2IRQA] =   SimpleReg_t("IA2IRQA",     0x0B4A, 12,     0x000      );
 111   fRegs[kIA2IRQB] =   SimpleReg_t("IA2IRQB",     0x0B4B, 12,     0x000      );
 112   fRegs[kIA2IRQC] =   SimpleReg_t("IA2IRQC",     0x0B4C, 12,     0x000      );
 113   fRegs[kIRQSW2]  =   SimpleReg_t("IRQSW2",      0x0B4D, 13,     0x1FFF     );
 114   fRegs[kIRQHW2]  =   SimpleReg_t("IRQHW2",      0x0B4E, 13,     0x0000     );
 115   fRegs[kIRQHL2]  =   SimpleReg_t("IRQHL2",      0x0B4F, 13,     0x0000     );
 116   fRegs[kIA3IRQ0] =   SimpleReg_t("IA3IRQ0",     0x0B60, 12,     0x000      );  // IVT of CPU3
 117   fRegs[kIA3IRQ1] =   SimpleReg_t("IA3IRQ1",     0x0B61, 12,     0x000      );
 118   fRegs[kIA3IRQ2] =   SimpleReg_t("IA3IRQ2",     0x0B62, 12,     0x000      );
 119   fRegs[kIA3IRQ3] =   SimpleReg_t("IA3IRQ3",     0x0B63, 12,     0x000      );
 120   fRegs[kIA3IRQ4] =   SimpleReg_t("IA3IRQ4",     0x0B64, 12,     0x000      );
 121   fRegs[kIA3IRQ5] =   SimpleReg_t("IA3IRQ5",     0x0B65, 12,     0x000      );
 122   fRegs[kIA3IRQ6] =   SimpleReg_t("IA3IRQ6",     0x0B66, 12,     0x000      );
 123   fRegs[kIA3IRQ7] =   SimpleReg_t("IA3IRQ7",     0x0B67, 12,     0x000      );
 124   fRegs[kIA3IRQ8] =   SimpleReg_t("IA3IRQ8",     0x0B68, 12,     0x000      );
 125   fRegs[kIA3IRQ9] =   SimpleReg_t("IA3IRQ9",     0x0B69, 12,     0x000      );
 126   fRegs[kIA3IRQA] =   SimpleReg_t("IA3IRQA",     0x0B6A, 12,     0x000      );
 127   fRegs[kIA3IRQB] =   SimpleReg_t("IA3IRQB",     0x0B6B, 12,     0x000      );
 128   fRegs[kIA3IRQC] =   SimpleReg_t("IA3IRQC",     0x0B6C, 12,     0x000      );
 129   fRegs[kIRQSW3]  =   SimpleReg_t("IRQSW3",      0x0B6D, 13,     0x1FFF     );
 130   fRegs[kIRQHW3]  =   SimpleReg_t("IRQHW3",      0x0B6E, 13,     0x0000     );
 131   fRegs[kIRQHL3]  =   SimpleReg_t("IRQHL3",      0x0B6F, 13,     0x0000     );
 132   fRegs[kCTGDINI] =   SimpleReg_t("CTGDINI",     0x0B80, 32,     0x00000000 );  // Global Counter/Timer
 133   fRegs[kCTGCTRL] =   SimpleReg_t("CTGCTRL",     0x0B81, 12,     0xE3F      );
 134   fRegs[kC08CPU0] =   SimpleReg_t("C08CPU0",     0x0C00, 32,     0x00000000 );  // CPU constants
 135   fRegs[kC09CPU0] =   SimpleReg_t("C09CPU0",     0x0C01, 32,     0x00000000 );
 136   fRegs[kC10CPU0] =   SimpleReg_t("C10CPU0",     0x0C02, 32,     0x00000000 );
 137   fRegs[kC11CPU0] =   SimpleReg_t("C11CPU0",     0x0C03, 32,     0x00000000 );
 138   fRegs[kC12CPUA] =   SimpleReg_t("C12CPUA",     0x0C04, 32,     0x00000000 );
 139   fRegs[kC13CPUA] =   SimpleReg_t("C13CPUA",     0x0C05, 32,     0x00000000 );
 140   fRegs[kC14CPUA] =   SimpleReg_t("C14CPUA",     0x0C06, 32,     0x00000000 );
 141   fRegs[kC15CPUA] =   SimpleReg_t("C15CPUA",     0x0C07, 32,     0x00000000 );
 142   fRegs[kC08CPU1] =   SimpleReg_t("C08CPU1",     0x0C08, 32,     0x00000000 );
 143   fRegs[kC09CPU1] =   SimpleReg_t("C09CPU1",     0x0C09, 32,     0x00000000 );
 144   fRegs[kC10CPU1] =   SimpleReg_t("C10CPU1",     0x0C0A, 32,     0x00000000 );
 145   fRegs[kC11CPU1] =   SimpleReg_t("C11CPU1",     0x0C0B, 32,     0x00000000 );
 146   fRegs[kC08CPU2] =   SimpleReg_t("C08CPU2",     0x0C10, 32,     0x00000000 );
 147   fRegs[kC09CPU2] =   SimpleReg_t("C09CPU2",     0x0C11, 32,     0x00000000 );
 148   fRegs[kC10CPU2] =   SimpleReg_t("C10CPU2",     0x0C12, 32,     0x00000000 );
 149   fRegs[kC11CPU2] =   SimpleReg_t("C11CPU2",     0x0C13, 32,     0x00000000 );
 150   fRegs[kC08CPU3] =   SimpleReg_t("C08CPU3",     0x0C18, 32,     0x00000000 );
 151   fRegs[kC09CPU3] =   SimpleReg_t("C09CPU3",     0x0C19, 32,     0x00000000 );
 152   fRegs[kC10CPU3] =   SimpleReg_t("C10CPU3",     0x0C1A, 32,     0x00000000 );
 153   fRegs[kC11CPU3] =   SimpleReg_t("C11CPU3",     0x0C1B, 32,     0x00000000 );
 154   fRegs[kNMOD]    =   SimpleReg_t("NMOD",        0x0D40, 6,      0x08       );  // NI interface
 155   fRegs[kNDLY]    =   SimpleReg_t("NDLY",        0x0D41, 30,     0x24924924 );
 156   fRegs[kNED]     =   SimpleReg_t("NED",         0x0D42, 16,     0xA240     );
 157   fRegs[kNTRO]    =   SimpleReg_t("NTRO",        0x0D43, 18,     0x3FFFC    );
 158   fRegs[kNRRO]    =   SimpleReg_t("NRRO",        0x0D44, 18,     0x3FFFC    );
 159   fRegs[kNES]     =   SimpleReg_t("NES",         0x0D45, 32,     0x00000000 );
 160   fRegs[kNTP]     =   SimpleReg_t("NTP",         0x0D46, 32,     0x0000FFFF );
 161   fRegs[kNBND]    =   SimpleReg_t("NBND",        0x0D47, 16,     0x6020     );
 162   fRegs[kNP0]     =   SimpleReg_t("NP0",         0x0D48, 11,     0x44C      );
 163   fRegs[kNP1]     =   SimpleReg_t("NP1",         0x0D49, 11,     0x44C      );
 164   fRegs[kNP2]     =   SimpleReg_t("NP2",         0x0D4A, 11,     0x44C      );
 165   fRegs[kNP3]     =   SimpleReg_t("NP3",         0x0D4B, 11,     0x44C      );
 166   fRegs[kNCUT]    =   SimpleReg_t("NCUT",        0x0D4C, 32,     0xFFFFFFFF );
 167   fRegs[kTPPT0]   =   SimpleReg_t("TPPT0",       0x3000, 7,      0x01       );  // Filter and Preprocessor
 168   fRegs[kTPFS]    =   SimpleReg_t("TPFS",        0x3001, 7,      0x05       );
 169   fRegs[kTPFE]    =   SimpleReg_t("TPFE",        0x3002, 7,      0x14       );
 170   fRegs[kTPPGR]   =   SimpleReg_t("TPPGR",       0x3003, 7,      0x15       );
 171   fRegs[kTPPAE]   =   SimpleReg_t("TPPAE",       0x3004, 7,      0x1E       );
 172   fRegs[kTPQS0]   =   SimpleReg_t("TPQS0",       0x3005, 7,      0x00       );
 173   fRegs[kTPQE0]   =   SimpleReg_t("TPQE0",       0x3006, 7,      0x0A       );
 174   fRegs[kTPQS1]   =   SimpleReg_t("TPQS1",       0x3007, 7,      0x0B       );
 175   fRegs[kTPQE1]   =   SimpleReg_t("TPQE1",       0x3008, 7,      0x14       );
 176   fRegs[kEBD]     =   SimpleReg_t("EBD",         0x3009, 3,      0x0        );
 177   fRegs[kEBAQA]   =   SimpleReg_t("EBAQA",       0x300A, 7,      0x00       );
 178   fRegs[kEBSIA]   =   SimpleReg_t("EBSIA",       0x300B, 7,      0x20       );
 179   fRegs[kEBSF]    =   SimpleReg_t("EBSF",        0x300C, 1,      0x1        );
 180   fRegs[kEBSIM]   =   SimpleReg_t("EBSIM",       0x300D, 1,      0x1        );
 181   fRegs[kEBPP]    =   SimpleReg_t("EBPP",        0x300E, 1,      0x1        );
 182   fRegs[kEBPC]    =   SimpleReg_t("EBPC",        0x300F, 1,      0x1        );
 183   fRegs[kEBIS]    =   SimpleReg_t("EBIS",        0x3014, 10,     0x005      );
 184   fRegs[kEBIT]    =   SimpleReg_t("EBIT",        0x3015, 12,     0x028      );
 185   fRegs[kEBIL]    =   SimpleReg_t("EBIL",        0x3016, 8,      0xF0       );
 186   fRegs[kEBIN]    =   SimpleReg_t("EBIN",        0x3017, 1,      0x1        );
 187   fRegs[kFLBY]    =   SimpleReg_t("FLBY",        0x3018, 1,      0x0        );
 188   fRegs[kFPBY]    =   SimpleReg_t("FPBY",        0x3019, 1,      0x0        );
 189   fRegs[kFGBY]    =   SimpleReg_t("FGBY",        0x301A, 1,      0x0        );
 190   fRegs[kFTBY]    =   SimpleReg_t("FTBY",        0x301B, 1,      0x0        );
 191   fRegs[kFCBY]    =   SimpleReg_t("FCBY",        0x301C, 1,      0x0        );
 192   fRegs[kFPTC]    =   SimpleReg_t("FPTC",        0x3020, 2,      0x3        );
 193   fRegs[kFPNP]    =   SimpleReg_t("FPNP",        0x3021, 9,      0x078      );
 194   fRegs[kFPCL]    =   SimpleReg_t("FPCL",        0x3022, 1,      0x1        );
 195   fRegs[kFGTA]    =   SimpleReg_t("FGTA",        0x3028, 12,     0x014      );
 196   fRegs[kFGTB]    =   SimpleReg_t("FGTB",        0x3029, 12,     0x80C      );
 197   fRegs[kFGCL]    =   SimpleReg_t("FGCL",        0x302A, 1,      0x1        );
 198   fRegs[kFTAL]    =   SimpleReg_t("FTAL",        0x3030, 10,     0x0F6      );
 199   fRegs[kFTLL]    =   SimpleReg_t("FTLL",        0x3031, 9,      0x11D      );
 200   fRegs[kFTLS]    =   SimpleReg_t("FTLS",        0x3032, 9,      0x0D3      );
 201   fRegs[kFCW1]    =   SimpleReg_t("FCW1",        0x3038, 8,      0x1E       );
 202   fRegs[kFCW2]    =   SimpleReg_t("FCW2",        0x3039, 8,      0xD4       );
 203   fRegs[kFCW3]    =   SimpleReg_t("FCW3",        0x303A, 8,      0xE6       );
 204   fRegs[kFCW4]    =   SimpleReg_t("FCW4",        0x303B, 8,      0x4A       );
 205   fRegs[kFCW5]    =   SimpleReg_t("FCW5",        0x303C, 8,      0xEF       );
 206   fRegs[kTPFP]    =   SimpleReg_t("TPFP",        0x3040, 9,      0x037      );
 207   fRegs[kTPHT]    =   SimpleReg_t("TPHT",        0x3041, 14,     0x00A0     );
 208   fRegs[kTPVT]    =   SimpleReg_t("TPVT",        0x3042, 6,      0x00       );
 209   fRegs[kTPVBY]   =   SimpleReg_t("TPVBY",       0x3043, 1,      0x0        );
 210   fRegs[kTPCT]    =   SimpleReg_t("TPCT",        0x3044, 5,      0x08       );
 211   fRegs[kTPCL]    =   SimpleReg_t("TPCL",        0x3045, 5,      0x01       );
 212   fRegs[kTPCBY]   =   SimpleReg_t("TPCBY",       0x3046, 1,      0x1        );
 213   fRegs[kTPD]     =   SimpleReg_t("TPD",         0x3047, 4,      0xF        );
 214   fRegs[kTPCI0]   =   SimpleReg_t("TPCI0",       0x3048, 5,      0x00       );
 215   fRegs[kTPCI1]   =   SimpleReg_t("TPCI1",       0x3049, 5,      0x00       );
 216   fRegs[kTPCI2]   =   SimpleReg_t("TPCI2",       0x304A, 5,      0x00       );
 217   fRegs[kTPCI3]   =   SimpleReg_t("TPCI3",       0x304B, 5,      0x00       );
 218   fRegs[kADCMSK]  =   SimpleReg_t("ADCMSK",      0x3050, 21,     0x1FFFFF   );
 219   fRegs[kADCINB]  =   SimpleReg_t("ADCINB",      0x3051, 2,      0x2        );
 220   fRegs[kADCDAC]  =   SimpleReg_t("ADCDAC",      0x3052, 5,      0x10       );
 221   fRegs[kADCPAR]  =   SimpleReg_t("ADCPAR",      0x3053, 18,     0x195EF    );
 222   fRegs[kADCTST]  =   SimpleReg_t("ADCTST",      0x3054, 2,      0x0        );
 223   fRegs[kSADCAZ]  =   SimpleReg_t("SADCAZ",      0x3055, 1,      0x1        );
 224   fRegs[kFGF0]    =   SimpleReg_t("FGF0",        0x3080, 9,      0x000      );
 225   fRegs[kFGF1]    =   SimpleReg_t("FGF1",        0x3081, 9,      0x000      );
 226   fRegs[kFGF2]    =   SimpleReg_t("FGF2",        0x3082, 9,      0x000      );
 227   fRegs[kFGF3]    =   SimpleReg_t("FGF3",        0x3083, 9,      0x000      );
 228   fRegs[kFGF4]    =   SimpleReg_t("FGF4",        0x3084, 9,      0x000      );
 229   fRegs[kFGF5]    =   SimpleReg_t("FGF5",        0x3085, 9,      0x000      );
 230   fRegs[kFGF6]    =   SimpleReg_t("FGF6",        0x3086, 9,      0x000      );
 231   fRegs[kFGF7]    =   SimpleReg_t("FGF7",        0x3087, 9,      0x000      );
 232   fRegs[kFGF8]    =   SimpleReg_t("FGF8",        0x3088, 9,      0x000      );
 233   fRegs[kFGF9]    =   SimpleReg_t("FGF9",        0x3089, 9,      0x000      );
 234   fRegs[kFGF10]   =   SimpleReg_t("FGF10",       0x308A, 9,      0x000      );
 235   fRegs[kFGF11]   =   SimpleReg_t("FGF11",       0x308B, 9,      0x000      );
 236   fRegs[kFGF12]   =   SimpleReg_t("FGF12",       0x308C, 9,      0x000      );
 237   fRegs[kFGF13]   =   SimpleReg_t("FGF13",       0x308D, 9,      0x000      );
 238   fRegs[kFGF14]   =   SimpleReg_t("FGF14",       0x308E, 9,      0x000      );
 239   fRegs[kFGF15]   =   SimpleReg_t("FGF15",       0x308F, 9,      0x000      );
 240   fRegs[kFGF16]   =   SimpleReg_t("FGF16",       0x3090, 9,      0x000      );
 241   fRegs[kFGF17]   =   SimpleReg_t("FGF17",       0x3091, 9,      0x000      );
 242   fRegs[kFGF18]   =   SimpleReg_t("FGF18",       0x3092, 9,      0x000      );
 243   fRegs[kFGF19]   =   SimpleReg_t("FGF19",       0x3093, 9,      0x000      );
 244   fRegs[kFGF20]   =   SimpleReg_t("FGF20",       0x3094, 9,      0x000      );
 245   fRegs[kFGA0]    =   SimpleReg_t("FGA0",        0x30A0, 6,      0x00       );
 246   fRegs[kFGA1]    =   SimpleReg_t("FGA1",        0x30A1, 6,      0x00       );
 247   fRegs[kFGA2]    =   SimpleReg_t("FGA2",        0x30A2, 6,      0x00       );
 248   fRegs[kFGA3]    =   SimpleReg_t("FGA3",        0x30A3, 6,      0x00       );
 249   fRegs[kFGA4]    =   SimpleReg_t("FGA4",        0x30A4, 6,      0x00       );
 250   fRegs[kFGA5]    =   SimpleReg_t("FGA5",        0x30A5, 6,      0x00       );
 251   fRegs[kFGA6]    =   SimpleReg_t("FGA6",        0x30A6, 6,      0x00       );
 252   fRegs[kFGA7]    =   SimpleReg_t("FGA7",        0x30A7, 6,      0x00       );
 253   fRegs[kFGA8]    =   SimpleReg_t("FGA8",        0x30A8, 6,      0x00       );
 254   fRegs[kFGA9]    =   SimpleReg_t("FGA9",        0x30A9, 6,      0x00       );
 255   fRegs[kFGA10]   =   SimpleReg_t("FGA10",       0x30AA, 6,      0x00       );
 256   fRegs[kFGA11]   =   SimpleReg_t("FGA11",       0x30AB, 6,      0x00       );
 257   fRegs[kFGA12]   =   SimpleReg_t("FGA12",       0x30AC, 6,      0x00       );
 258   fRegs[kFGA13]   =   SimpleReg_t("FGA13",       0x30AD, 6,      0x00       );
 259   fRegs[kFGA14]   =   SimpleReg_t("FGA14",       0x30AE, 6,      0x00       );
 260   fRegs[kFGA15]   =   SimpleReg_t("FGA15",       0x30AF, 6,      0x00       );
 261   fRegs[kFGA16]   =   SimpleReg_t("FGA16",       0x30B0, 6,      0x00       );
 262   fRegs[kFGA17]   =   SimpleReg_t("FGA17",       0x30B1, 6,      0x00       );
 263   fRegs[kFGA18]   =   SimpleReg_t("FGA18",       0x30B2, 6,      0x00       );
 264   fRegs[kFGA19]   =   SimpleReg_t("FGA19",       0x30B3, 6,      0x00       );
 265   fRegs[kFGA20]   =   SimpleReg_t("FGA20",       0x30B4, 6,      0x00       );
 266   fRegs[kFLL00]   =   SimpleReg_t("FLL00",       0x3100, 6,      0x00       );  // non-linearity table, 64 x 6 bits
 267   fRegs[kFLL01]   =   SimpleReg_t("FLL01",       0x3101, 6,      0x00       );
 268   fRegs[kFLL02]   =   SimpleReg_t("FLL02",       0x3102, 6,      0x00       );
 269   fRegs[kFLL03]   =   SimpleReg_t("FLL03",       0x3103, 6,      0x00       );
 270   fRegs[kFLL04]   =   SimpleReg_t("FLL04",       0x3104, 6,      0x00       );
 271   fRegs[kFLL05]   =   SimpleReg_t("FLL05",       0x3105, 6,      0x00       );
 272   fRegs[kFLL06]   =   SimpleReg_t("FLL06",       0x3106, 6,      0x00       );
 273   fRegs[kFLL07]   =   SimpleReg_t("FLL07",       0x3107, 6,      0x00       );
 274   fRegs[kFLL08]   =   SimpleReg_t("FLL08",       0x3108, 6,      0x00       );
 275   fRegs[kFLL09]   =   SimpleReg_t("FLL09",       0x3109, 6,      0x00       );
 276   fRegs[kFLL0A]   =   SimpleReg_t("FLL0A",       0x310A, 6,      0x00       );
 277   fRegs[kFLL0B]   =   SimpleReg_t("FLL0B",       0x310B, 6,      0x00       );
 278   fRegs[kFLL0C]   =   SimpleReg_t("FLL0C",       0x310C, 6,      0x00       );
 279   fRegs[kFLL0D]   =   SimpleReg_t("FLL0D",       0x310D, 6,      0x00       );
 280   fRegs[kFLL0E]   =   SimpleReg_t("FLL0E",       0x310E, 6,      0x00       );
 281   fRegs[kFLL0F]   =   SimpleReg_t("FLL0F",       0x310F, 6,      0x00       );
 282   fRegs[kFLL10]   =   SimpleReg_t("FLL10",       0x3110, 6,      0x00       );
 283   fRegs[kFLL11]   =   SimpleReg_t("FLL11",       0x3111, 6,      0x00       );
 284   fRegs[kFLL12]   =   SimpleReg_t("FLL12",       0x3112, 6,      0x00       );
 285   fRegs[kFLL13]   =   SimpleReg_t("FLL13",       0x3113, 6,      0x00       );
 286   fRegs[kFLL14]   =   SimpleReg_t("FLL14",       0x3114, 6,      0x00       );
 287   fRegs[kFLL15]   =   SimpleReg_t("FLL15",       0x3115, 6,      0x00       );
 288   fRegs[kFLL16]   =   SimpleReg_t("FLL16",       0x3116, 6,      0x00       );
 289   fRegs[kFLL17]   =   SimpleReg_t("FLL17",       0x3117, 6,      0x00       );
 290   fRegs[kFLL18]   =   SimpleReg_t("FLL18",       0x3118, 6,      0x00       );
 291   fRegs[kFLL19]   =   SimpleReg_t("FLL19",       0x3119, 6,      0x00       );
 292   fRegs[kFLL1A]   =   SimpleReg_t("FLL1A",       0x311A, 6,      0x00       );
 293   fRegs[kFLL1B]   =   SimpleReg_t("FLL1B",       0x311B, 6,      0x00       );
 294   fRegs[kFLL1C]   =   SimpleReg_t("FLL1C",       0x311C, 6,      0x00       );
 295   fRegs[kFLL1D]   =   SimpleReg_t("FLL1D",       0x311D, 6,      0x00       );
 296   fRegs[kFLL1E]   =   SimpleReg_t("FLL1E",       0x311E, 6,      0x00       );
 297   fRegs[kFLL1F]   =   SimpleReg_t("FLL1F",       0x311F, 6,      0x00       );
 298   fRegs[kFLL20]   =   SimpleReg_t("FLL20",       0x3120, 6,      0x00       );
 299   fRegs[kFLL21]   =   SimpleReg_t("FLL21",       0x3121, 6,      0x00       );
 300   fRegs[kFLL22]   =   SimpleReg_t("FLL22",       0x3122, 6,      0x00       );
 301   fRegs[kFLL23]   =   SimpleReg_t("FLL23",       0x3123, 6,      0x00       );
 302   fRegs[kFLL24]   =   SimpleReg_t("FLL24",       0x3124, 6,      0x00       );
 303   fRegs[kFLL25]   =   SimpleReg_t("FLL25",       0x3125, 6,      0x00       );
 304   fRegs[kFLL26]   =   SimpleReg_t("FLL26",       0x3126, 6,      0x00       );
 305   fRegs[kFLL27]   =   SimpleReg_t("FLL27",       0x3127, 6,      0x00       );
 306   fRegs[kFLL28]   =   SimpleReg_t("FLL28",       0x3128, 6,      0x00       );
 307   fRegs[kFLL29]   =   SimpleReg_t("FLL29",       0x3129, 6,      0x00       );
 308   fRegs[kFLL2A]   =   SimpleReg_t("FLL2A",       0x312A, 6,      0x00       );
 309   fRegs[kFLL2B]   =   SimpleReg_t("FLL2B",       0x312B, 6,      0x00       );
 310   fRegs[kFLL2C]   =   SimpleReg_t("FLL2C",       0x312C, 6,      0x00       );
 311   fRegs[kFLL2D]   =   SimpleReg_t("FLL2D",       0x312D, 6,      0x00       );
 312   fRegs[kFLL2E]   =   SimpleReg_t("FLL2E",       0x312E, 6,      0x00       );
 313   fRegs[kFLL2F]   =   SimpleReg_t("FLL2F",       0x312F, 6,      0x00       );
 314   fRegs[kFLL30]   =   SimpleReg_t("FLL30",       0x3130, 6,      0x00       );
 315   fRegs[kFLL31]   =   SimpleReg_t("FLL31",       0x3131, 6,      0x00       );
 316   fRegs[kFLL32]   =   SimpleReg_t("FLL32",       0x3132, 6,      0x00       );
 317   fRegs[kFLL33]   =   SimpleReg_t("FLL33",       0x3133, 6,      0x00       );
 318   fRegs[kFLL34]   =   SimpleReg_t("FLL34",       0x3134, 6,      0x00       );
 319   fRegs[kFLL35]   =   SimpleReg_t("FLL35",       0x3135, 6,      0x00       );
 320   fRegs[kFLL36]   =   SimpleReg_t("FLL36",       0x3136, 6,      0x00       );
 321   fRegs[kFLL37]   =   SimpleReg_t("FLL37",       0x3137, 6,      0x00       );
 322   fRegs[kFLL38]   =   SimpleReg_t("FLL38",       0x3138, 6,      0x00       );
 323   fRegs[kFLL39]   =   SimpleReg_t("FLL39",       0x3139, 6,      0x00       );
 324   fRegs[kFLL3A]   =   SimpleReg_t("FLL3A",       0x313A, 6,      0x00       );
 325   fRegs[kFLL3B]   =   SimpleReg_t("FLL3B",       0x313B, 6,      0x00       );
 326   fRegs[kFLL3C]   =   SimpleReg_t("FLL3C",       0x313C, 6,      0x00       );
 327   fRegs[kFLL3D]   =   SimpleReg_t("FLL3D",       0x313D, 6,      0x00       );
 328   fRegs[kFLL3E]   =   SimpleReg_t("FLL3E",       0x313E, 6,      0x00       );
 329   fRegs[kFLL3F]   =   SimpleReg_t("FLL3F",       0x313F, 6,      0x00       );
 330   fRegs[kPASADEL] =   SimpleReg_t("PASADEL",     0x3158, 8,      0xFF       );  // end of non-lin table
 331   fRegs[kPASAPHA] =   SimpleReg_t("PASAPHA",     0x3159, 6,      0x3F       );
 332   fRegs[kPASAPRA] =   SimpleReg_t("PASAPRA",     0x315A, 6,      0x0F       );
 333   fRegs[kPASADAC] =   SimpleReg_t("PASADAC",     0x315B, 8,      0x80       );
 334   fRegs[kPASACHM] =   SimpleReg_t("PASACHM",     0x315C, 19,     0x7FFFF    );
 335   fRegs[kPASASTL] =   SimpleReg_t("PASASTL",     0x315D, 8,      0xFF       );
 336   fRegs[kPASAPR1] =   SimpleReg_t("PASAPR1",     0x315E, 1,      0x0        );
 337   fRegs[kPASAPR0] =   SimpleReg_t("PASAPR0",     0x315F, 1,      0x0        );
 338   fRegs[kSADCTRG] =   SimpleReg_t("SADCTRG",     0x3161, 1,      0x0        );
 339   fRegs[kSADCRUN] =   SimpleReg_t("SADCRUN",     0x3162, 1,      0x0        );
 340   fRegs[kSADCPWR] =   SimpleReg_t("SADCPWR",     0x3163, 3,      0x7        );
 341   fRegs[kL0TSIM]  =   SimpleReg_t("L0TSIM",      0x3165, 14,     0x0050     );
 342   fRegs[kSADCEC]  =   SimpleReg_t("SADCEC",      0x3166, 7,      0x00       );
 343   fRegs[kSADCMC]  =   SimpleReg_t("SADCMC",      0x3170, 8,      0xC0       );
 344   fRegs[kSADCOC]  =   SimpleReg_t("SADCOC",      0x3171, 8,      0x19       );
 345   fRegs[kSADCGTB] =   SimpleReg_t("SADCGTB",     0x3172, 32,     0x37737700 );
 346   fRegs[kSEBDEN]  =   SimpleReg_t("SEBDEN",      0x3178, 3,      0x0        );
 347   fRegs[kSEBDOU]  =   SimpleReg_t("SEBDOU",      0x3179, 3,      0x0        );
 348   fRegs[kTPL00]   =   SimpleReg_t("TPL00",       0x3180, 5,      0x00       );  // pos table, 128 x 5 bits
 349   fRegs[kTPL01]   =   SimpleReg_t("TPL01",       0x3181, 5,      0x00       );
 350   fRegs[kTPL02]   =   SimpleReg_t("TPL02",       0x3182, 5,      0x00       );
 351   fRegs[kTPL03]   =   SimpleReg_t("TPL03",       0x3183, 5,      0x00       );
 352   fRegs[kTPL04]   =   SimpleReg_t("TPL04",       0x3184, 5,      0x00       );
 353   fRegs[kTPL05]   =   SimpleReg_t("TPL05",       0x3185, 5,      0x00       );
 354   fRegs[kTPL06]   =   SimpleReg_t("TPL06",       0x3186, 5,      0x00       );
 355   fRegs[kTPL07]   =   SimpleReg_t("TPL07",       0x3187, 5,      0x00       );
 356   fRegs[kTPL08]   =   SimpleReg_t("TPL08",       0x3188, 5,      0x00       );
 357   fRegs[kTPL09]   =   SimpleReg_t("TPL09",       0x3189, 5,      0x00       );
 358   fRegs[kTPL0A]   =   SimpleReg_t("TPL0A",       0x318A, 5,      0x00       );
 359   fRegs[kTPL0B]   =   SimpleReg_t("TPL0B",       0x318B, 5,      0x00       );
 360   fRegs[kTPL0C]   =   SimpleReg_t("TPL0C",       0x318C, 5,      0x00       );
 361   fRegs[kTPL0D]   =   SimpleReg_t("TPL0D",       0x318D, 5,      0x00       );
 362   fRegs[kTPL0E]   =   SimpleReg_t("TPL0E",       0x318E, 5,      0x00       );
 363   fRegs[kTPL0F]   =   SimpleReg_t("TPL0F",       0x318F, 5,      0x00       );
 364   fRegs[kTPL10]   =   SimpleReg_t("TPL10",       0x3190, 5,      0x00       );
 365   fRegs[kTPL11]   =   SimpleReg_t("TPL11",       0x3191, 5,      0x00       );
 366   fRegs[kTPL12]   =   SimpleReg_t("TPL12",       0x3192, 5,      0x00       );
 367   fRegs[kTPL13]   =   SimpleReg_t("TPL13",       0x3193, 5,      0x00       );
 368   fRegs[kTPL14]   =   SimpleReg_t("TPL14",       0x3194, 5,      0x00       );
 369   fRegs[kTPL15]   =   SimpleReg_t("TPL15",       0x3195, 5,      0x00       );
 370   fRegs[kTPL16]   =   SimpleReg_t("TPL16",       0x3196, 5,      0x00       );
 371   fRegs[kTPL17]   =   SimpleReg_t("TPL17",       0x3197, 5,      0x00       );
 372   fRegs[kTPL18]   =   SimpleReg_t("TPL18",       0x3198, 5,      0x00       );
 373   fRegs[kTPL19]   =   SimpleReg_t("TPL19",       0x3199, 5,      0x00       );
 374   fRegs[kTPL1A]   =   SimpleReg_t("TPL1A",       0x319A, 5,      0x00       );
 375   fRegs[kTPL1B]   =   SimpleReg_t("TPL1B",       0x319B, 5,      0x00       );
 376   fRegs[kTPL1C]   =   SimpleReg_t("TPL1C",       0x319C, 5,      0x00       );
 377   fRegs[kTPL1D]   =   SimpleReg_t("TPL1D",       0x319D, 5,      0x00       );
 378   fRegs[kTPL1E]   =   SimpleReg_t("TPL1E",       0x319E, 5,      0x00       );
 379   fRegs[kTPL1F]   =   SimpleReg_t("TPL1F",       0x319F, 5,      0x00       );
 380   fRegs[kTPL20]   =   SimpleReg_t("TPL20",       0x31A0, 5,      0x00       );
 381   fRegs[kTPL21]   =   SimpleReg_t("TPL21",       0x31A1, 5,      0x00       );
 382   fRegs[kTPL22]   =   SimpleReg_t("TPL22",       0x31A2, 5,      0x00       );
 383   fRegs[kTPL23]   =   SimpleReg_t("TPL23",       0x31A3, 5,      0x00       );
 384   fRegs[kTPL24]   =   SimpleReg_t("TPL24",       0x31A4, 5,      0x00       );
 385   fRegs[kTPL25]   =   SimpleReg_t("TPL25",       0x31A5, 5,      0x00       );
 386   fRegs[kTPL26]   =   SimpleReg_t("TPL26",       0x31A6, 5,      0x00       );
 387   fRegs[kTPL27]   =   SimpleReg_t("TPL27",       0x31A7, 5,      0x00       );
 388   fRegs[kTPL28]   =   SimpleReg_t("TPL28",       0x31A8, 5,      0x00       );
 389   fRegs[kTPL29]   =   SimpleReg_t("TPL29",       0x31A9, 5,      0x00       );
 390   fRegs[kTPL2A]   =   SimpleReg_t("TPL2A",       0x31AA, 5,      0x00       );
 391   fRegs[kTPL2B]   =   SimpleReg_t("TPL2B",       0x31AB, 5,      0x00       );
 392   fRegs[kTPL2C]   =   SimpleReg_t("TPL2C",       0x31AC, 5,      0x00       );
 393   fRegs[kTPL2D]   =   SimpleReg_t("TPL2D",       0x31AD, 5,      0x00       );
 394   fRegs[kTPL2E]   =   SimpleReg_t("TPL2E",       0x31AE, 5,      0x00       );
 395   fRegs[kTPL2F]   =   SimpleReg_t("TPL2F",       0x31AF, 5,      0x00       );
 396   fRegs[kTPL30]   =   SimpleReg_t("TPL30",       0x31B0, 5,      0x00       );
 397   fRegs[kTPL31]   =   SimpleReg_t("TPL31",       0x31B1, 5,      0x00       );
 398   fRegs[kTPL32]   =   SimpleReg_t("TPL32",       0x31B2, 5,      0x00       );
 399   fRegs[kTPL33]   =   SimpleReg_t("TPL33",       0x31B3, 5,      0x00       );
 400   fRegs[kTPL34]   =   SimpleReg_t("TPL34",       0x31B4, 5,      0x00       );
 401   fRegs[kTPL35]   =   SimpleReg_t("TPL35",       0x31B5, 5,      0x00       );
 402   fRegs[kTPL36]   =   SimpleReg_t("TPL36",       0x31B6, 5,      0x00       );
 403   fRegs[kTPL37]   =   SimpleReg_t("TPL37",       0x31B7, 5,      0x00       );
 404   fRegs[kTPL38]   =   SimpleReg_t("TPL38",       0x31B8, 5,      0x00       );
 405   fRegs[kTPL39]   =   SimpleReg_t("TPL39",       0x31B9, 5,      0x00       );
 406   fRegs[kTPL3A]   =   SimpleReg_t("TPL3A",       0x31BA, 5,      0x00       );
 407   fRegs[kTPL3B]   =   SimpleReg_t("TPL3B",       0x31BB, 5,      0x00       );
 408   fRegs[kTPL3C]   =   SimpleReg_t("TPL3C",       0x31BC, 5,      0x00       );
 409   fRegs[kTPL3D]   =   SimpleReg_t("TPL3D",       0x31BD, 5,      0x00       );
 410   fRegs[kTPL3E]   =   SimpleReg_t("TPL3E",       0x31BE, 5,      0x00       );
 411   fRegs[kTPL3F]   =   SimpleReg_t("TPL3F",       0x31BF, 5,      0x00       );
 412   fRegs[kTPL40]   =   SimpleReg_t("TPL40",       0x31C0, 5,      0x00       );
 413   fRegs[kTPL41]   =   SimpleReg_t("TPL41",       0x31C1, 5,      0x00       );
 414   fRegs[kTPL42]   =   SimpleReg_t("TPL42",       0x31C2, 5,      0x00       );
 415   fRegs[kTPL43]   =   SimpleReg_t("TPL43",       0x31C3, 5,      0x00       );
 416   fRegs[kTPL44]   =   SimpleReg_t("TPL44",       0x31C4, 5,      0x00       );
 417   fRegs[kTPL45]   =   SimpleReg_t("TPL45",       0x31C5, 5,      0x00       );
 418   fRegs[kTPL46]   =   SimpleReg_t("TPL46",       0x31C6, 5,      0x00       );
 419   fRegs[kTPL47]   =   SimpleReg_t("TPL47",       0x31C7, 5,      0x00       );
 420   fRegs[kTPL48]   =   SimpleReg_t("TPL48",       0x31C8, 5,      0x00       );
 421   fRegs[kTPL49]   =   SimpleReg_t("TPL49",       0x31C9, 5,      0x00       );
 422   fRegs[kTPL4A]   =   SimpleReg_t("TPL4A",       0x31CA, 5,      0x00       );
 423   fRegs[kTPL4B]   =   SimpleReg_t("TPL4B",       0x31CB, 5,      0x00       );
 424   fRegs[kTPL4C]   =   SimpleReg_t("TPL4C",       0x31CC, 5,      0x00       );
 425   fRegs[kTPL4D]   =   SimpleReg_t("TPL4D",       0x31CD, 5,      0x00       );
 426   fRegs[kTPL4E]   =   SimpleReg_t("TPL4E",       0x31CE, 5,      0x00       );
 427   fRegs[kTPL4F]   =   SimpleReg_t("TPL4F",       0x31CF, 5,      0x00       );
 428   fRegs[kTPL50]   =   SimpleReg_t("TPL50",       0x31D0, 5,      0x00       );
 429   fRegs[kTPL51]   =   SimpleReg_t("TPL51",       0x31D1, 5,      0x00       );
 430   fRegs[kTPL52]   =   SimpleReg_t("TPL52",       0x31D2, 5,      0x00       );
 431   fRegs[kTPL53]   =   SimpleReg_t("TPL53",       0x31D3, 5,      0x00       );
 432   fRegs[kTPL54]   =   SimpleReg_t("TPL54",       0x31D4, 5,      0x00       );
 433   fRegs[kTPL55]   =   SimpleReg_t("TPL55",       0x31D5, 5,      0x00       );
 434   fRegs[kTPL56]   =   SimpleReg_t("TPL56",       0x31D6, 5,      0x00       );
 435   fRegs[kTPL57]   =   SimpleReg_t("TPL57",       0x31D7, 5,      0x00       );
 436   fRegs[kTPL58]   =   SimpleReg_t("TPL58",       0x31D8, 5,      0x00       );
 437   fRegs[kTPL59]   =   SimpleReg_t("TPL59",       0x31D9, 5,      0x00       );
 438   fRegs[kTPL5A]   =   SimpleReg_t("TPL5A",       0x31DA, 5,      0x00       );
 439   fRegs[kTPL5B]   =   SimpleReg_t("TPL5B",       0x31DB, 5,      0x00       );
 440   fRegs[kTPL5C]   =   SimpleReg_t("TPL5C",       0x31DC, 5,      0x00       );
 441   fRegs[kTPL5D]   =   SimpleReg_t("TPL5D",       0x31DD, 5,      0x00       );
 442   fRegs[kTPL5E]   =   SimpleReg_t("TPL5E",       0x31DE, 5,      0x00       );
 443   fRegs[kTPL5F]   =   SimpleReg_t("TPL5F",       0x31DF, 5,      0x00       );
 444   fRegs[kTPL60]   =   SimpleReg_t("TPL60",       0x31E0, 5,      0x00       );
 445   fRegs[kTPL61]   =   SimpleReg_t("TPL61",       0x31E1, 5,      0x00       );
 446   fRegs[kTPL62]   =   SimpleReg_t("TPL62",       0x31E2, 5,      0x00       );
 447   fRegs[kTPL63]   =   SimpleReg_t("TPL63",       0x31E3, 5,      0x00       );
 448   fRegs[kTPL64]   =   SimpleReg_t("TPL64",       0x31E4, 5,      0x00       );
 449   fRegs[kTPL65]   =   SimpleReg_t("TPL65",       0x31E5, 5,      0x00       );
 450   fRegs[kTPL66]   =   SimpleReg_t("TPL66",       0x31E6, 5,      0x00       );
 451   fRegs[kTPL67]   =   SimpleReg_t("TPL67",       0x31E7, 5,      0x00       );
 452   fRegs[kTPL68]   =   SimpleReg_t("TPL68",       0x31E8, 5,      0x00       );
 453   fRegs[kTPL69]   =   SimpleReg_t("TPL69",       0x31E9, 5,      0x00       );
 454   fRegs[kTPL6A]   =   SimpleReg_t("TPL6A",       0x31EA, 5,      0x00       );
 455   fRegs[kTPL6B]   =   SimpleReg_t("TPL6B",       0x31EB, 5,      0x00       );
 456   fRegs[kTPL6C]   =   SimpleReg_t("TPL6C",       0x31EC, 5,      0x00       );
 457   fRegs[kTPL6D]   =   SimpleReg_t("TPL6D",       0x31ED, 5,      0x00       );
 458   fRegs[kTPL6E]   =   SimpleReg_t("TPL6E",       0x31EE, 5,      0x00       );
 459   fRegs[kTPL6F]   =   SimpleReg_t("TPL6F",       0x31EF, 5,      0x00       );
 460   fRegs[kTPL70]   =   SimpleReg_t("TPL70",       0x31F0, 5,      0x00       );
 461   fRegs[kTPL71]   =   SimpleReg_t("TPL71",       0x31F1, 5,      0x00       );
 462   fRegs[kTPL72]   =   SimpleReg_t("TPL72",       0x31F2, 5,      0x00       );
 463   fRegs[kTPL73]   =   SimpleReg_t("TPL73",       0x31F3, 5,      0x00       );
 464   fRegs[kTPL74]   =   SimpleReg_t("TPL74",       0x31F4, 5,      0x00       );
 465   fRegs[kTPL75]   =   SimpleReg_t("TPL75",       0x31F5, 5,      0x00       );
 466   fRegs[kTPL76]   =   SimpleReg_t("TPL76",       0x31F6, 5,      0x00       );
 467   fRegs[kTPL77]   =   SimpleReg_t("TPL77",       0x31F7, 5,      0x00       );
 468   fRegs[kTPL78]   =   SimpleReg_t("TPL78",       0x31F8, 5,      0x00       );
 469   fRegs[kTPL79]   =   SimpleReg_t("TPL79",       0x31F9, 5,      0x00       );
 470   fRegs[kTPL7A]   =   SimpleReg_t("TPL7A",       0x31FA, 5,      0x00       );
 471   fRegs[kTPL7B]   =   SimpleReg_t("TPL7B",       0x31FB, 5,      0x00       );
 472   fRegs[kTPL7C]   =   SimpleReg_t("TPL7C",       0x31FC, 5,      0x00       );
 473   fRegs[kTPL7D]   =   SimpleReg_t("TPL7D",       0x31FD, 5,      0x00       );
 474   fRegs[kTPL7E]   =   SimpleReg_t("TPL7E",       0x31FE, 5,      0x00       );
 475   fRegs[kTPL7F]   =   SimpleReg_t("TPL7F",       0x31FF, 5,      0x00       );
 476   fRegs[kMEMRW]   =   SimpleReg_t("MEMRW",       0xD000, 7,      0x79       );  // end of pos table
 477   fRegs[kMEMCOR]  =   SimpleReg_t("MEMCOR",      0xD001, 9,      0x000      );
 478   fRegs[kDMDELA]  =   SimpleReg_t("DMDELA",      0xD002, 4,      0x8        );
 479   fRegs[kDMDELS]  =   SimpleReg_t("DMDELS",      0xD003, 4,      0x8        );
 480
 481
 482
 483   for(Int_t iAddr = 0; iAddr < fgkDmemWords; iAddr++) {
 484
 485      if(iAddr == fgkDmemAddrDeflCorr - fgkDmemStartAddress) {
 486         fDmem[iAddr] = new UInt_t[fgkDmemSizeSmIndividual];
 487         fDmemDepth[iAddr] = fgkDmemSizeSmIndividual;
 488      }
 489
 490      else if(iAddr == fgkDmemAddrNdrift - fgkDmemStartAddress) {
 491         fDmem[iAddr] = new UInt_t[fgkDmemSizeSmRocIndividual];
 492         fDmemDepth[iAddr] = fgkDmemSizeSmRocIndividual;
 493      }
 494
 495      else if(iAddr >= fgkDmemAddrDeflCutStart-fgkDmemStartAddress && iAddr <= fgkDmemAddrDeflCutEnd-fgkDmemStartAddress) {
 496         fDmem[iAddr]  = new UInt_t[fgkDmemSizeSmIndividual];
 497         fDmemDepth[iAddr] = fgkDmemSizeSmIndividual;
 498      }
 499
 500      else if(iAddr >= fgkDmemAddrTrackletStart-fgkDmemStartAddress && iAddr <= fgkDmemAddrTrackletEnd-fgkDmemStartAddress) {
 501         fDmem[iAddr]  = new UInt_t[fgkDmemSizeTotalIndividual];
 502         fDmemDepth[iAddr] = fgkDmemSizeTotalIndividual;
 503      }
 504
 505      else if(iAddr >= fgkDmemAddrLUTStart-fgkDmemStartAddress && iAddr <= fgkDmemAddrLUTEnd-fgkDmemStartAddress) {
 506         fDmem[iAddr]  = new UInt_t;   // same value for all MCMs
 507         fDmemDepth[iAddr] = fgkDmemSizeUniform;
 508     }
 509
 510      else if(iAddr == fgkDmemAddrLUTcor0-fgkDmemStartAddress) {
 511         fDmem[iAddr]  = new UInt_t[fgkDmemSizeSmIndividual];
 512         fDmemDepth[iAddr]  = fgkDmemSizeSmIndividual;
 513      }
 514
 515      else if(iAddr == fgkDmemAddrLUTcor1-fgkDmemStartAddress) {
 516         fDmem[iAddr]  = new UInt_t[fgkDmemSizeSmIndividual];
 517         fDmemDepth[iAddr]  = fgkDmemSizeSmIndividual;
 518      }
 519
 520      else if(iAddr == fgkDmemAddrLUTnbins-fgkDmemStartAddress) {
 521         fDmem[iAddr]  = new UInt_t;   // same value for all MCMs
 522         fDmemDepth[iAddr] = fgkDmemSizeUniform;
 523      }
 524
 525      else if(iAddr == fgkDmemAddrLUTLength-fgkDmemStartAddress) {
 526         fDmem[iAddr]  = new UInt_t;   // same value for all MCMs
 527         fDmemDepth[iAddr] = fgkDmemSizeUniform;
 528      }
 529
 530      else {
 531         fDmem[iAddr] = NULL;
 532         fDmemDepth[iAddr] = fgkDmemSizeEmpty;
 533      }
 534
 535   }
 536
 537   InitRegs();
 538   ResetDmem();
 539 }
 540
 541
 542 AliTRDtrapConfig* AliTRDtrapConfig::Instance()
 543 {
 544   // return a pointer to an instance of this class
 545
 546   if (!fgInstance) {
 547     fgInstance = new AliTRDtrapConfig();
 548     AliTRDtrapConfigHandler cfgHandler;
 549     cfgHandler.LoadConfig();
 550   }
 551
 552   return fgInstance;
 553 }
 554
 555
 556 AliTRDtrapConfig::~AliTRDtrapConfig()
 557 {
 558   for(Int_t iAddr = 0; iAddr < fgkDmemWords; iAddr++) {
 559      if(iAddr == fgkDmemAddrDeflCorr - fgkDmemStartAddress)
 560         delete [] fDmem[iAddr];
 561
 562      else if(iAddr == fgkDmemAddrNdrift - fgkDmemStartAddress)
 563         delete [] fDmem[iAddr];
 564
 565      else if(iAddr >= fgkDmemAddrDeflCutStart-fgkDmemStartAddress && iAddr <= fgkDmemAddrDeflCutEnd-fgkDmemStartAddress)
 566         delete [] fDmem[iAddr];
 567
 568      else if(iAddr >= fgkDmemAddrTrackletStart-fgkDmemStartAddress && iAddr <= fgkDmemAddrTrackletEnd-fgkDmemStartAddress)
 569         delete [] fDmem[iAddr];
 570
 571      else if(iAddr >= fgkDmemAddrLUTStart-fgkDmemStartAddress && iAddr <= fgkDmemAddrLUTEnd-fgkDmemStartAddress)
 572         delete fDmem[iAddr];
 573
 574      else if(iAddr == fgkDmemAddrLUTcor0-fgkDmemStartAddress)
 575         delete [] fDmem[iAddr];
 576
 577      else if(iAddr == fgkDmemAddrLUTcor1-fgkDmemStartAddress)
 578         delete [] fDmem[iAddr];
 579
 580      else if(iAddr == fgkDmemAddrLUTnbins-fgkDmemStartAddress)
 581         delete fDmem[iAddr];
 582
 583      else if(iAddr == fgkDmemAddrLUTLength-fgkDmemStartAddress)
 584         delete fDmem[iAddr];
 585   }
 586 }
 587
 588
 589 void AliTRDtrapConfig::InitRegs()
 590 {
 591    // Reset the content of all TRAP registers to the reset values (see TRAP User Manual)
 592
 593    for (Int_t iReg = 0; iReg < kLastReg; iReg++) {
 594
 595      fRegisterValue[iReg].individualValue = 0x0;
 596
 597      fRegisterValue[iReg].globalValue = GetRegResetValue((TrapReg_t) iReg);
 598      fRegisterValue[iReg].state = RegValue_t::kGlobal;
 599    }
 600 }
 601
 602
 603 void AliTRDtrapConfig::ResetRegs()
 604 {
 605    // Reset the content of all TRAP registers to the reset values (see TRAP User Manual)
 606
 607    for (Int_t iReg = 0; iReg < kLastReg; iReg++) {
 608       if(fRegisterValue[iReg].state == RegValue_t::kIndividual) {
 609         if (fRegisterValue[iReg].individualValue) {
 610           delete [] fRegisterValue[iReg].individualValue;
 611           fRegisterValue[iReg].individualValue = 0x0;
 612         }
 613       }
 614
 615       fRegisterValue[iReg].globalValue = GetRegResetValue((TrapReg_t) iReg);
 616       fRegisterValue[iReg].state = RegValue_t::kGlobal;
 617       //    printf("%-8s: 0x%08x\n", GetRegName((TrapReg_t) iReg), fRegisterValue[iReg].globalValue);
 618    }
 619 }
 620
 621
 622 void AliTRDtrapConfig::ResetDmem()
 623 {
 624      for(Int_t iAddr = 0; iAddr < fgkDmemWords; iAddr++) {
 625         if(fDmemDepth[iAddr] == 0)
 626            continue;
 627         for(Int_t j=0; j < fDmemDepth[iAddr]; j++) {
 628            fDmem[iAddr][j]=0;
 629         }
 630      }
 631 }
 632
 633
 634 Int_t AliTRDtrapConfig::GetTrapReg(TrapReg_t reg, Int_t det, Int_t rob, Int_t mcm) const
 635 {
 636   // get the value of an individual TRAP register
 637   // if it is individual for TRAPs a valid TRAP has to be specified
 638
 639   if ((reg < 0) || (reg >= kLastReg)) {
 640     AliError("Non-existing register requested");
 641     return 0;
 642   }
 643   else {
 644     if (fRegisterValue[reg].state == RegValue_t::kGlobal) {
 645       return fRegisterValue[reg].globalValue;
 646     }
 647     else if (fRegisterValue[reg].state == RegValue_t::kIndividual) {
 648        if((det >= 0 && det < AliTRDgeometry::Ndet()) &&
 649           (rob >= 0 && rob < AliTRDfeeParam::GetNrobC1()) &&
 650           (mcm >= 0 && mcm < fgkMaxMcm)) {
 651          return fRegisterValue[reg].individualValue[det*AliTRDfeeParam::GetNrobC1()*fgkMaxMcm + rob*fgkMaxMcm + mcm];
 652        }
 653        else {
 654          AliError("Invalid MCM specified or register is individual");
 655          return 0;
 656        }
 657     }
 658     else {  // should never be reached
 659       AliError("MCM register status neither kGlobal nor kIndividual");
 660       return 0;
 661     }
 662   }
 663 }
 664
 665
 666 Bool_t AliTRDtrapConfig::SetTrapReg(TrapReg_t reg, Int_t value)
 667 {
 668   // set a global value for the given TRAP register,
 669   // i.e. the same value for all TRAPs
 670
 671    if (fRegisterValue[reg].state == RegValue_t::kGlobal) {
 672       fRegisterValue[reg].globalValue = value;
 673       return kTRUE;
 674    }
 675    else {
 676       AliError("Register has individual values");
 677    }
 678    return kFALSE;
 679 }
 680
 681
 682 Bool_t AliTRDtrapConfig::SetTrapReg(TrapReg_t reg, Int_t value, Int_t det)
 683 {
 684   // set a global value for the given TRAP register,
 685   // i.e. the same value for all TRAPs
 686
 687    if (fRegisterValue[reg].state == RegValue_t::kGlobal) {
 688       fRegisterValue[reg].globalValue = value;
 689       return kTRUE;
 690    }
 691    else if (fRegisterValue[reg].state == RegValue_t::kIndividual) {
 692       // if the register is in idividual mode but a broadcast is requested, the selected register is
 693       // set to value for all MCMs on the chamber
 694
 695       if( (det>=0 && det<AliTRDgeometry::Ndet())) {
 696          for(Int_t rob=0; rob<AliTRDfeeParam::GetNrobC1(); rob++) {
 697             for(Int_t mcm=0; mcm<fgkMaxMcm; mcm++)
 698                fRegisterValue[reg].individualValue[det*AliTRDfeeParam::GetNrobC1()*fgkMaxMcm + rob*fgkMaxMcm + mcm] = value;
 699          }
 700       }
 701       else {
 702          AliError(Form("Invalid detector number: %i\n", det));
 703          return kFALSE;
 704       }
 705    }
 706    else {  // should never be reached
 707       AliError("MCM register status neither kGlobal nor kIndividual");
 708       return kFALSE;
 709    }
 710
 711    return kFALSE;
 712 }
 713
 714
 715 Bool_t AliTRDtrapConfig::SetTrapReg(TrapReg_t reg, Int_t value, Int_t det, Int_t rob, Int_t mcm)
 716 {
 717   // set the value for the given TRAP register of an individual MCM
 718
 719   //std::cout << "-- reg: 0x" << std::hex << fRegs[reg].addr <<
 720   //std::dec << ", data " << value << ", det " << det << ", rob " << rob << ", mcm " << mcm << std::endl;
 721
 722    if( (det >= 0 && det < AliTRDgeometry::Ndet()) &&
 723        (rob >= 0 && rob < AliTRDfeeParam::GetNrobC1()) &&
 724        (mcm >= 0 && mcm < fgkMaxMcm) ) {
 725      if (fRegisterValue[reg].state == RegValue_t::kGlobal) {
 726         Int_t defaultValue = fRegisterValue[reg].globalValue;
 727
 728         fRegisterValue[reg].state = RegValue_t::kIndividual;
 729         fRegisterValue[reg].individualValue = new Int_t[AliTRDgeometry::Ndet()*AliTRDfeeParam::GetNrobC1()*fgkMaxMcm];
 730
 731         for(Int_t i = 0; i < AliTRDgeometry::Ndet()*AliTRDfeeParam::GetNrobC1()*fgkMaxMcm; i++)
 732            fRegisterValue[reg].individualValue[i] = defaultValue; // set the requested register of all MCMs to the value previously stored
 733
 734         fRegisterValue[reg].individualValue[det*AliTRDfeeParam::GetNrobC1()*fgkMaxMcm + rob*fgkMaxMcm + mcm] = value;
 735      }
 736      else if (fRegisterValue[reg].state == RegValue_t::kIndividual) {
 737         fRegisterValue[reg].individualValue[det*AliTRDfeeParam::GetNrobC1()*fgkMaxMcm + rob*fgkMaxMcm + mcm] = value;
 738      }
 739      else {  // should never be reached
 740         AliError("MCM register status neither kGlobal nor kIndividual");
 741         return kFALSE;
 742      }
 743   }
 744    else {
 745       AliError(Form("Invalid value for det, ROB or MCM selected: %i, %i, %i", det, rob, mcm));
 746      return kFALSE;
 747    }
 748
 749   return kTRUE;
 750 }
 751
 752
 753 UInt_t AliTRDtrapConfig::Peek(Int_t addr, Int_t det, Int_t rob, Int_t mcm) const
 754 {
 755   // reading from given address
 756
 757   if ( (addr >= fgkDmemStartAddress) &&
 758        (addr < (fgkDmemStartAddress + fgkDmemWords)) ) {
 759     return GetDmemUnsigned(addr, det, rob, mcm);
 760   }
 761   else {
 762     TrapReg_t mcmReg = GetRegByAddress(addr);
 763     if ( mcmReg >= 0 && mcmReg < kLastReg) {
 764       return (UInt_t) GetTrapReg(mcmReg, det, rob, mcm);
 765     }
 766   }
 767
 768   return 0;
 769 }
 770
 771
 772 Bool_t AliTRDtrapConfig::Poke(Int_t addr, UInt_t value, Int_t det, Int_t rob, Int_t mcm)
 773 {
 774   // writing to given address
 775
 776   if ( (addr >= fgkDmemStartAddress) &&
 777        (addr < (fgkDmemStartAddress + fgkDmemWords)) ) {
 778     AliDebug(2, Form("DMEM 0x%08x : %i", addr, value));
 779     SetDmem(addr, value, det, rob, mcm);
 780     return kTRUE;
 781   }
 782   else {
 783     TrapReg_t mcmReg = GetRegByAddress(addr);
 784     if ( mcmReg >= 0 && mcmReg < kLastReg) {
 785       AliDebug(2, Form("Register: %s : %i\n", GetRegName(mcmReg), value));
 786       SetTrapReg(mcmReg, (UInt_t) value, det, rob, mcm);
 787       return kTRUE;
 788     }
 789   }
 790
 791   return kFALSE;
 792 }
 793
 794
 795 Bool_t AliTRDtrapConfig::SetDmem(Int_t addr, UInt_t value)
 796 {
 797   // Set the content of the given DMEM address
 798
 799    addr = addr - fgkDmemStartAddress;
 800
 801    if(addr < 0 || addr >=  fgkDmemWords) {
 802       AliError(Form("No DMEM address: 0x%08x", addr+fgkDmemStartAddress));
 803       return kFALSE;
 804    }
 805
 806    switch(fDmemDepth[addr]) {
 807    case fgkDmemSizeEmpty:
 808       AliDebug(4, Form("DMEM address %i not active", addr));
 809       return kFALSE;
 810       break;
 811    case fgkDmemSizeUniform:
 812       if(fDmem[addr][0]!=0)
 813          AliDebug(5, Form("Warning: Setting new value to DMEM 0x%08x", addr+fgkDmemStartAddress));
 814
 815       fDmem[addr][0] = value;
 816       break;
 817    case fgkDmemSizeSmIndividual:
 818       for(Int_t i=0; i<fgkDmemSizeSmIndividual; i++) {
 819          if(fDmem[addr][i]!=0)
 820             AliDebug(5, Form("Warning: Setting new value to DMEM 0x%08x", addr+fgkDmemStartAddress));
 821
 822          fDmem[addr][i]=value;
 823       }
 824       break;
 825    case fgkDmemSizeTotalIndividual:
 826       for(Int_t i=0; i<fgkDmemSizeTotalIndividual; i++) {
 827          if(fDmem[addr][i]!=0)
 828             AliDebug(5, Form("Warning: Setting new value to DMEM 0x%08x", addr+fgkDmemStartAddress));
 829
 830          fDmem[addr][i]=value;
 831       }
 832       break;
 833    case fgkDmemSizeSmRocIndividual:
 834       for(Int_t i=0; i<fgkDmemSizeSmRocIndividual; i++) {
 835          if(fDmem[addr][i]!=0)
 836             AliDebug(5, Form("Warning: Setting new value to DMEM 0x%08x", addr+fgkDmemStartAddress));
 837
 838          fDmem[addr][i]=value;
 839       }
 840       break;
 841    default:
 842       AliError(Form("Invalid selection type"));
 843       break;
 844    }
 845
 846    return kTRUE;
 847 }
 848
 849
 850 Bool_t AliTRDtrapConfig::SetDmem(Int_t addr, UInt_t value, Int_t det, Int_t rob, Int_t mcm)
 851 {
 852   // Set the content of the given DMEM address
 853
 854    addr = addr - fgkDmemStartAddress;
 855    Int_t roc = det%30;
 856    Int_t loc;
 857
 858    if(addr < 0 || addr >=  fgkDmemWords) {
 859       AliError(Form("No DMEM address: 0x%08x", addr+fgkDmemStartAddress));
 860       return kFALSE;
 861    }
 862
 863    Int_t detFactor=8*16;
 864    Int_t robFactor=16;
 865
 866    switch(fDmemDepth[addr]) {
 867    case fgkDmemSizeEmpty:
 868       AliDebug(4, Form("DMEM address 0x%08x not active", addr+fgkDmemStartAddress));
 869       return kFALSE;
 870       break;
 871    case fgkDmemSizeUniform:
 872       if(fDmem[addr][0]!=0)
 873          AliDebug(5, Form("Warning: Setting new value to DMEM 0x%08x", addr+fgkDmemStartAddress));
 874
 875       fDmem[addr][0] = value;
 876       break;
 877    case fgkDmemSizeSmIndividual:
 878       loc = detFactor*roc + robFactor*rob + mcm;
 879       if(loc < fgkDmemSizeSmIndividual) {
 880          if(fDmem[addr][loc]!=0)
 881             AliDebug(5, Form("Warning: Setting new value to DMEM 0x%08x", addr+fgkDmemStartAddress));
 882
 883          fDmem[addr][loc] = value;
 884       }
 885       else {
 886          AliError(Form("DMEM sub-address %i out of scope", loc));
 887          return kFALSE;
 888       }
 889       break;
 890    case fgkDmemSizeTotalIndividual:
 891       loc = detFactor*det + robFactor*rob + mcm;
 892       if(loc < fgkDmemSizeTotalIndividual) {
 893          if(fDmem[addr][loc]!=0)
 894             AliDebug(5, Form("Warning: Setting new value to DMEM 0x%08x", addr+fgkDmemStartAddress));
 895
 896          fDmem[addr][loc]=value;
 897       }
 898       else {
 899          AliError(Form("DMEM sub-address %i out of scope", loc));
 900          return kFALSE;
 901       }
 902       break;
 903    case fgkDmemSizeSmRocIndividual:
 904       if(det < fgkDmemSizeSmRocIndividual) {
 905          if(fDmem[addr][det]!=0)
 906             AliDebug(5, Form("Warning: Setting new value to DMEM 0x%08x", addr+fgkDmemStartAddress));
 907
 908          fDmem[addr][det]=value;
 909       }
 910       else {
 911          AliError(Form("DMEM sub-address %i out of scope", det));
 912          return kFALSE;
 913       }
 914
 915       break;
 916    default:
 917       AliError(Form("Invalid selection type"));
 918       return kFALSE;
 919       break;
 920    }
 921
 922    return kTRUE;
 923 }
 924
 925
 926 UInt_t AliTRDtrapConfig::GetDmemUnsigned(Int_t addr) const
 927 {
 928    addr = addr - fgkDmemStartAddress;
 929    if(addr < 0 || addr >=  fgkDmemWords) {
 930       AliError(Form("No DMEM address: 0x%08x", addr+fgkDmemStartAddress));
 931       return 0;
 932    }
 933
 934    if(fDmemDepth[addr] == fgkDmemSizeUniform)
 935       return fDmem[addr][0];
 936    else {
 937       AliError(Form("No global DMEM value at 0x%08x", addr+fgkDmemStartAddress));
 938       return 0;
 939    }
 940    return 0;
 941 }
 942
 943 UInt_t AliTRDtrapConfig::GetDmemUnsigned(Int_t addr, Int_t det, Int_t rob, Int_t mcm) const
 944 {
 945    addr = addr - fgkDmemStartAddress;
 946    Int_t roc = det%30;
 947    Int_t loc;
 948
 949    if(addr < 0 || addr >=  fgkDmemWords) {
 950       AliError(Form("No DMEM address: 0x%08x", addr+fgkDmemStartAddress));
 951       return 0;
 952    }
 953
 954    Int_t detFactor=8*16;
 955    Int_t robFactor=16;
 956
 957    switch(fDmemDepth[addr]) {
 958    case fgkDmemSizeEmpty:
 959       AliDebug(4, Form("DMEM address 0x%08x not active", addr+fgkDmemStartAddress));
 960       return 0;
 961       break;
 962    case fgkDmemSizeUniform:
 963       return fDmem[addr][0];
 964       break;
 965    case fgkDmemSizeSmIndividual:
 966       loc = detFactor*roc + robFactor*rob + mcm;
 967       if(loc < fgkDmemSizeSmIndividual) {
 968          return fDmem[addr][loc];
 969       }
 970       else {
 971          AliError(Form("DMEM sub-address %i out of scope", loc));
 972          return 0;
 973       }
 974       break;
 975    case fgkDmemSizeTotalIndividual:
 976       loc = detFactor*det + robFactor*rob + mcm;
 977       if(loc < fgkDmemSizeTotalIndividual) {
 978          return fDmem[addr][loc];
 979       }
 980       else {
 981          AliError(Form("DMEM sub-address %i out of scope", loc));
 982          return 0;
 983       }
 984       break;
 985    case fgkDmemSizeSmRocIndividual:
 986       if(det < fgkDmemSizeSmRocIndividual) {
 987          return fDmem[addr][det];
 988       }
 989       else {
 990          AliError(Form("DMEM sub-address %i out of scope", det));
 991          return 0;
 992       }
 993       break;
 994    default:
 995       AliError(Form("Invalid selection type"));
 996       return 0;
 997       break;
 998    }
 999
1000    return 0;
1001 }
1002
1003
1004 Bool_t AliTRDtrapConfig::ReadPackedConfig(Int_t hc, UInt_t *data, Int_t size)
1005 {
1006   // Read the packed configuration from the passed memory block
1007   //
1008   // To be used to retrieve the TRAP configuration from the
1009   // configuration as sent in the raw data.
1010
1011   AliDebug(1, "Reading packed configuration");
1012
1013   Int_t det = hc/2;
1014
1015   Int_t idx = 0;
1016   Int_t err = 0;
1017   Int_t step, bwidth, nwords, exitFlag, bitcnt;
1018
1019   UShort_t caddr;
1020   UInt_t dat, msk, header, dataHi;
1021
1022   while (idx < size && *data != 0x00000000) {
1023
1024     Int_t rob = (*data >> 28) & 0x7;
1025     Int_t mcm = (*data >> 24) & 0xf;
1026
1027     AliDebug(1, Form("Config of det. %3i MCM %i:%02i (0x%08x)", det, rob, mcm, *data));
1028     data++;
1029
1030     while (idx < size && *data != 0x00000000) {
1031
1032       header = *data;
1033       data++;
1034       idx++;
1035
1036       AliDebug(5, Form("read: 0x%08x", header));
1037
1038       if (header & 0x01) // single data
1039         {
1040           dat   = (header >>  2) & 0xFFFF;       // 16 bit data
1041           caddr = (header >> 18) & 0x3FFF;    // 14 bit address
1042
1043           if (caddr != 0x1FFF)  // temp!!! because the end marker was wrong
1044             {
1045               if (header & 0x02) // check if > 16 bits
1046                 {
1047                   dataHi = *data;
1048                   AliDebug(5, Form("read: 0x%08x", dataHi));
1049                   data++;
1050                   idx++;
1051                   err += ((dataHi ^ (dat | 1)) & 0xFFFF) != 0;
1052                   dat = (dataHi & 0xFFFF0000) | dat;
1053                 }
1054               AliDebug(5, Form("addr=0x%04x (%s) data=0x%08x\n", caddr, GetRegName(GetRegByAddress(caddr)), dat));
1055               if ( ! Poke(caddr, dat, det, rob, mcm) )
1056                 AliDebug(5, Form("(single-write): non-existing address 0x%04x containing 0x%08x\n", caddr, header));
1057               if (idx > size)
1058                 {
1059                   AliDebug(5, Form("(single-write): no more data, missing end marker\n"));
1060                   return -err;
1061                 }
1062             }
1063           else
1064             {
1065               AliDebug(5, Form("(single-write): address 0x%04x => old endmarker?\n", caddr));
1066               return err;
1067             }
1068         }
1069
1070       else               // block of data
1071         {
1072           step   =  (header >>  1) & 0x0003;
1073           bwidth = ((header >>  3) & 0x001F) + 1;
1074           nwords =  (header >>  8) & 0x00FF;
1075           caddr  =  (header >> 16) & 0xFFFF;
1076           exitFlag = (step == 0) || (step == 3) || (nwords == 0);
1077
1078           if (exitFlag)
1079             break;
1080
1081           switch (bwidth)
1082             {
1083             case    15:
1084             case    10:
1085             case     7:
1086             case     6:
1087             case     5:
1088               {
1089                 msk = (1 << bwidth) - 1;
1090                 bitcnt = 0;
1091                 while (nwords > 0)
1092                   {
1093                     nwords--;
1094                     bitcnt -= bwidth;
1095                     if (bitcnt < 0)
1096                       {
1097                         header = *data;
1098                         AliDebug(5, Form("read 0x%08x", header));
1099                         data++;
1100                         idx++;
1101                         err += (header & 1);
1102                         header = header >> 1;
1103                         bitcnt = 31 - bwidth;
1104                       }
1105                     AliDebug(5, Form("addr=0x%04x (%s) data=0x%08x\n", caddr, GetRegName(GetRegByAddress(caddr)), header & msk));
1106                     if ( ! Poke(caddr, header & msk, det, rob, mcm) )
1107                       AliDebug(5, Form("(single-write): non-existing address 0x%04x containing 0x%08x\n", caddr, header));
1108
1109                     caddr += step;
1110                     header = header >> bwidth;
1111                     if (idx >= size)
1112                       {
1113                         AliDebug(5, Form("(block-write): no end marker! %d words read\n", idx));
1114                         return -err;
1115                       }
1116                   }
1117                 break;
1118               } // end case 5-15
1119             case 31:
1120               {
1121                 while (nwords > 0)
1122                   {
1123                     header = *data;
1124                     AliDebug(5, Form("read 0x%08x", header));
1125                     data++;
1126                     idx++;
1127                     nwords--;
1128                     err += (header & 1);
1129
1130                     AliDebug(5, Form("addr=0x%04x (%s) data=0x%08x", caddr, GetRegName(GetRegByAddress(caddr)), header >> 1));
1131                     if ( ! Poke(caddr, header >> 1, det, rob, mcm) )
1132                       AliDebug(5, Form("(single-write): non-existing address 0x%04x containing 0x%08x\n", caddr, header));
1133
1134                     caddr += step;
1135                     if (idx >= size)
1136                       {
1137                         AliDebug(5, Form("no end marker! %d words read", idx));
1138                         return -err;
1139                       }
1140                   }
1141                 break;
1142               }
1143             default: return err;
1144             } // end switch
1145         } // end block case
1146     }
1147   } // end while
1148   AliDebug(5, Form("no end marker! %d words read", idx));
1149   return -err; // only if the max length of the block reached!
1150 }
1151
1152
1153 Bool_t AliTRDtrapConfig::PrintTrapReg(TrapReg_t reg, Int_t det, Int_t rob, Int_t mcm) const
1154 {
1155   // print the value stored in the given register
1156   // if it is individual a valid MCM has to be specified
1157
1158   if (fRegisterValue[reg].state == RegValue_t::kGlobal) {
1159     printf("%s (%i bits) at 0x%08x is 0x%08x and resets to: 0x%08x (currently global mode)\n",
1160            GetRegName((TrapReg_t) reg),
1161            GetRegNBits((TrapReg_t) reg),
1162            GetRegAddress((TrapReg_t) reg),
1163            fRegisterValue[reg].globalValue,
1164            GetRegResetValue((TrapReg_t) reg));
1165   }
1166   else if (fRegisterValue[reg].state == RegValue_t::kIndividual) {
1167     if((det >= 0 && det < AliTRDgeometry::Ndet()) &&
1168        (rob >= 0 && rob < AliTRDfeeParam::GetNrobC1()) &&
1169        (mcm >= 0 && mcm < fgkMaxMcm)) {
1170       printf("%s (%i bits) at 0x%08x is 0x%08x and resets to: 0x%08x (currently individual mode)\n",
1171              GetRegName((TrapReg_t) reg),
1172              GetRegNBits((TrapReg_t) reg),
1173              GetRegAddress((TrapReg_t) reg),
1174              fRegisterValue[reg].individualValue[det*AliTRDfeeParam::GetNrobC1()*fgkMaxMcm + rob*fgkMaxMcm + mcm],
1175              GetRegResetValue((TrapReg_t) reg));
1176     }
1177     else {
1178       AliError("Register value is MCM-specific: Invalid detector, ROB or MCM requested");
1179       return kFALSE;
1180     }
1181   }
1182   else {  // should never be reached
1183     AliError("MCM register status neither kGlobal nor kIndividual");
1184     return kFALSE;
1185   }
1186   return kTRUE;
1187 }
1188
1189
1190 Bool_t AliTRDtrapConfig::PrintTrapAddr(Int_t addr, Int_t det, Int_t rob, Int_t mcm) const
1191 {
1192   // print the value stored at the given address in the MCM chip
1193   TrapReg_t reg = GetRegByAddress(addr);
1194   if (reg >= 0 && reg < kLastReg) {
1195     return PrintTrapReg(reg, det, rob, mcm);
1196   }
1197   else {
1198     AliError(Form("There is no register at address 0x%08x in the simulator", addr));
1199     return kFALSE;
1200   }
1201 }
1202
1203
1204 Bool_t AliTRDtrapConfig::AddValues(UInt_t det, UInt_t cmd, UInt_t extali, Int_t addr, UInt_t data)
1205 {
1206    // transfer the informations provided by LoadConfig to the internal class variables
1207
1208   if(cmd != fgkScsnCmdWrite) {
1209     AliError(Form("Invalid command received: %i", cmd));
1210     return kFALSE;
1211   }
1212
1213   TrapReg_t mcmReg = GetRegByAddress(addr);
1214   Int_t rocType = AliTRDgeometry::GetStack(det) == 2 ? 0 : 1;
1215
1216   static const int mcmListSize=40;  // 40 is more or less arbitrary
1217   Int_t mcmList[mcmListSize];
1218
1219   // configuration registers
1220   if(mcmReg >= 0 && mcmReg < kLastReg) {
1221
1222     for(Int_t linkPair=0; linkPair<fgkMaxLinkPairs; linkPair++) {
1223       if(AliTRDfeeParam::ExtAliToAli(extali, linkPair, rocType, mcmList, mcmListSize)!=0) {
1224         Int_t i=0;
1225         while(mcmList[i] != -1 && i<mcmListSize) {
1226           if(mcmList[i]==127)
1227             SetTrapReg( (TrapReg_t) mcmReg, data, det);
1228           else
1229             SetTrapReg( (TrapReg_t) mcmReg, data, det, (mcmList[i]>>7), (mcmList[i]&0x7F));
1230           i++;
1231         }
1232       }
1233     }
1234     return kTRUE;
1235   }
1236   // DMEM
1237   else if ( (addr >= fgkDmemStartAddress) &&
1238             (addr < (fgkDmemStartAddress + fgkDmemWords))) {
1239     for(Int_t linkPair=0; linkPair<fgkMaxLinkPairs; linkPair++) {
1240       if(AliTRDfeeParam::ExtAliToAli(extali, linkPair, rocType, mcmList, mcmListSize)!=0) {
1241         Int_t i=0;
1242         while(mcmList[i] != -1 && i < mcmListSize) {
1243           if(mcmList[i] == 127)
1244              SetDmem(addr, data, det, 0, 127);
1245           else
1246              SetDmem(addr, data, det, mcmList[i] >> 7, mcmList[i] & 0x7f);
1247           i++;
1248         }
1249       }
1250     }
1251     return kTRUE;
1252   }
1253   else
1254     return kFALSE;
1255 }
1256
1257
1258 AliTRDtrapConfig::TrapReg_t AliTRDtrapConfig::GetRegByAddress(Int_t address) const
1259 {
1260   // get register by its address
1261   // used for reading of configuration data as sent to real FEE
1262
1263   TrapReg_t mcmReg = kLastReg;
1264   Int_t reg  = 0;
1265   do {
1266     if(fRegs[reg].fAddr == address)
1267       mcmReg = (TrapReg_t) reg;
1268     reg++;
1269   }  while (mcmReg == kLastReg && reg < kLastReg);
1270
1271   return mcmReg;
1272 }
1273
1274
1275 void AliTRDtrapConfig::PrintMemDatx(ostream &os, Int_t addr) const
1276 {
1277    PrintMemDatx(os, addr, 0, 0, 127);
1278 }
1279
1280 void AliTRDtrapConfig::PrintMemDatx(ostream &os, Int_t addr, Int_t det, Int_t rob, Int_t mcm) const
1281 {
1282    if(addr < fgkDmemStartAddress || addr >= fgkDmemStartAddress+fgkDmemWords) {
1283       AliError(Form("Invalid DMEM address 0x%08x!", addr));
1284       return;
1285    }
1286    PrintDatx(os, addr, GetDmemUnsigned(addr, det, rob, mcm), rob, mcm);
1287 }
1288
1289
1290 void AliTRDtrapConfig::PrintMemDatx(ostream &os, TrapReg_t reg) const
1291 {
1292    PrintMemDatx(os, reg, 0, 0, 127);
1293 }
1294
1295
1296 void AliTRDtrapConfig::PrintMemDatx(ostream &os, TrapReg_t reg, Int_t det, Int_t rob, Int_t mcm) const
1297 {
1298    if(reg>= kLastReg) {
1299       AliError(Form("Invalid register %i!", reg));
1300       return;
1301    }
1302    PrintDatx(os, GetRegAddress(reg), GetTrapReg(reg, det, rob, mcm), rob, mcm);
1303 }
1304
1305
1306 void AliTRDtrapConfig::PrintDatx(ostream &os, UInt_t addr, UInt_t data, Int_t rob, Int_t mcm) const
1307 {
1308    os << std::setw(5) << 10
1309       << std::setw(8) << addr
1310       << std::setw(12) << data;
1311    if(mcm==127)
1312       os << std::setw(8) << 127;
1313    else
1314       os << std::setw(8) << AliTRDfeeParam::AliToExtAli(rob, mcm);
1315
1316    os << std::endl;
1317 }