VZERO/AliVZEROLogicalSignal.cxx

   1 /**************************************************************************\r
   2  * Copyright(c) 1998-1999, ALICE Experiment at CERN, All rights reserved. *\r
   3  *                                                                        *\r
   4  * Author: The ALICE Off-line Project.                                    *\r
   5  * Contributors are mentioned in the code where appropriate.              *\r
   6  *                                                                        *\r
   7  * Permission to use, copy, modify and distribute this software and its   *\r
   8  * documentation strictly for non-commercial purposes is hereby granted   *\r
   9  * without fee, provided that the above copyright notice appears in all   *\r
  10  * copies and that both the copyright notice and this permission notice   *\r
  11  * appear in the supporting documentation. The authors make no claims     *\r
  12  * about the suitability of this software for any purpose. It is          *\r
  13  * provided "as is" without express or implied warranty.                  *\r
  14  **************************************************************************/\r
  15 \r
  16 // \r
  17 // Class AliVZEROLogicalSignal\r
  18 // ---------------------------\r
  19 // Describes a logical signal in the electronics. \r
  20 // Use it to generate observation windows\r
  21 // which are used by AliVZEROTriggerSimulator class\r
  22 // \r
  23 \r
  24 #include "AliLog.h"\r
  25 #include "AliVZEROLogicalSignal.h"\r
  26 \r
  27 ClassImp(AliVZEROLogicalSignal)\r
  28 \r
  29 //_____________________________________________________________________________\r
  30 AliVZEROLogicalSignal::AliVZEROLogicalSignal() : TObject(), fStart(0.), fStop(0.)\r
  31 {\r
  32         // Default constructor\r
  33 }\r
  34 //_____________________________________________________________________________\r
  35 AliVZEROLogicalSignal::AliVZEROLogicalSignal(Float_t start, Float_t stop) : TObject(), fStart(start), fStop(stop)\r
  36 {\r
  37         // Constructor using start and stop time\r
  38         if(fStart>fStop) AliError("Logical Signal has a Start time AFTER the Stop time");\r
  39         if(fStart==fStop) AliWarning("Logical Signal has a zero width");\r
  40 }\r
  41 //_____________________________________________________________________________\r
  42 AliVZEROLogicalSignal::AliVZEROLogicalSignal(UShort_t profilClock, UInt_t delay) : TObject(), fStart(0.), fStop(0.)\r
  43 {\r
  44         // Constructor using the profilClock and delay parameters comming from the FEE\r
  45         \r
  46         Bool_t word;\r
  47         Bool_t up=kFALSE;\r
  48         Bool_t down=kFALSE;\r
  49         \r
  50         for(int i=0 ; i<5 ; i++) {\r
  51                 word = (profilClock >> i) & 0x1;\r
  52                 if(word&&!up) {\r
  53                         fStart = 5. * i;\r
  54                         up = kTRUE;\r
  55                 }\r
  56                 if(!word&&up&&!down) {\r
  57                         fStop = 5. * i;\r
  58                         down = kTRUE;\r
  59                 }               \r
  60         }\r
  61         if(!down) fStop = 25.;\r
  62         \r
  63         fStart += delay*10.e-2; // Add 10 ps par register unit\r
  64         fStop  += delay*10.e-2; \r
  65 }\r
  66 //_____________________________________________________________________________\r
  67 AliVZEROLogicalSignal::AliVZEROLogicalSignal(const AliVZEROLogicalSignal &signal) : \r
  68         TObject(), fStart(signal.fStart), \r
  69         fStop(signal.fStop)\r
  70 {\r
  71         // Copy constructor\r
  72 }\r
  73 \r
  74 //_____________________________________________________________________________\r
  75 AliVZEROLogicalSignal::~AliVZEROLogicalSignal(){\r
  76         // Destructor\r
  77 }\r
  78 \r
  79 //_____________________________________________________________________________\r
  80 AliVZEROLogicalSignal& AliVZEROLogicalSignal::operator = \r
  81 (const AliVZEROLogicalSignal& signal)\r
  82 {\r
  83         // Operator =\r
  84         fStart = signal.fStart;\r
  85         fStop  = signal.fStop;\r
  86         return *this;\r
  87 }\r
  88 \r
  89 //_____________________________________________________________________________\r
  90 AliVZEROLogicalSignal AliVZEROLogicalSignal::operator|(const AliVZEROLogicalSignal& signal) const \r
  91 {\r
  92         // Perform the Logical OR of two signals: C = A or B\r
  93         if((fStart>signal.fStop) || (signal.fStart>fStop))\r
  94                 AliError(Form("Both signal do not superpose in time.\n  Start(A) = %f Stop(A) = %f\n   Start(B) = %f Stop(B) = %f",fStart, fStop, signal.fStart,signal.fStop));\r
  95         \r
  96         AliVZEROLogicalSignal result;\r
  97         if(fStart<signal.fStart) result.fStart = fStart;\r
  98         else result.fStart = signal.fStart;\r
  99         \r
 100         if(fStop>signal.fStop) result.fStop = fStop;\r
 101         else result.fStop = signal.fStop;\r
 102                 \r
 103         return result;\r
 104 }\r
 105 //_____________________________________________________________________________\r
 106 AliVZEROLogicalSignal AliVZEROLogicalSignal::operator&(const AliVZEROLogicalSignal& signal) const\r
 107 {\r
 108         // Perform the Logical AND of two signals: C = A and B\r
 109         if((fStart>signal.fStop) || (signal.fStart>fStop))\r
 110                 AliError(Form("Both signal do not superpose in time.\n  Start(A) = %f Stop(A) = %f\n   Start(B) = %f Stop(B) = %f",fStart, fStop, signal.fStart,signal.fStop));\r
 111         \r
 112         AliVZEROLogicalSignal result;\r
 113         if(fStart>signal.fStart) result.fStart = fStart;\r
 114         else result.fStart = signal.fStart;\r
 115         \r
 116         if(fStop<signal.fStop) result.fStop = fStop;\r
 117         else result.fStop = signal.fStop;\r
 118         \r
 119         return result;\r
 120 }\r
 121 \r
 122 //_____________________________________________________________________________\r
 123 Bool_t AliVZEROLogicalSignal::IsInCoincidence(Float_t time) const\r
 124 {\r
 125         // Check if a signal arriving at the time "time" is in coincidence with the logical signal\r
 126         Bool_t result = kFALSE;\r
 127         if((time>fStart) && (time<fStop)) result = kTRUE;\r
 128         return result;\r
 129 }\r
 130 \r