# # Pre-trigger run time parameter example file # which should be generated by PVSS tag editor panels # # Configuration infos TAG 120 REVISION 123 TIMESTAMP/CREATION YYYY-MM-DD hh:mm:ss TIMESTAMP/LASTUPDATE YYYY-MM-DD hh:mm:ss COMMENT example configuration (2010-03-31) changes according to PT meeting # TLMU input masks TLMU/IMASK/SEC00 1111_1111_1111_1111_1111_1111_1111_1111 TLMU/IMASK/SEC01 1111_1111_1111_1111_1111_1111_1111_1111 TLMU/IMASK/SEC02 1111_1111_1111_1111_1111_1111_1111_1111 TLMU/IMASK/SEC03 1111_1111_1111_1111_1111_1111_1111_1111 TLMU/IMASK/SEC04 1111_1111_1111_1111_1111_1111_1111_1111 TLMU/IMASK/SEC05 1111_1111_1111_1111_1111_1111_1111_1111 TLMU/IMASK/SEC06 1111_1111_1111_1111_1111_1111_1111_1111 TLMU/IMASK/SEC07 1111_1111_1111_1111_1111_1111_1111_1111 TLMU/IMASK/SEC08 1111_1111_1111_1111_1111_1111_1111_1111 TLMU/IMASK/SEC09 1111_1111_1111_1111_1111_1111_1111_1111 TLMU/IMASK/SEC10 1111_1111_1111_1111_1111_1111_1111_1111 TLMU/IMASK/SEC11 1111_1111_1111_1111_1111_1111_1111_1111 TLMU/IMASK/SEC12 1111_1111_1111_1111_1111_1111_1111_1111 TLMU/IMASK/SEC13 1111_1111_1111_1111_1111_1111_1111_1111 TLMU/IMASK/SEC14 1111_1111_1111_1111_1111_1111_1111_1111 TLMU/IMASK/SEC15 1111_1111_1111_1111_1111_1111_1111_1111 TLMU/IMASK/SEC17 1111_1111_1111_1111_1111_1111_1111_1111 # How long input if stretched. Value can be 0 to 3 TLMU/STRETCH 1 # Coincidence matrices set (there are three) (if not set, not activated) TLMU/CMATRIX0/SEC00 00_0000_0010_0000_0001 TLMU/CMATRIX0/SEC01 00_0000_0100_0000_0010 TLMU/CMATRIX0/SEC02 00_0000_1000_0000_0100 TLMU/CMATRIX0/SEC03 00_0001_0000_0000_1000 TLMU/CMATRIX0/SEC04 00_0010_0000_0001_0000 TLMU/CMATRIX0/SEC05 00_0100_0000_0010_0000 TLMU/CMATRIX0/SEC06 00_1000_0000_0100_0000 TLMU/CMATRIX0/SEC07 01_0000_0000_1000_0000 TLMU/CMATRIX0/SEC08 10_0000_0001_0000_0000 TLMU/CMATRIX1/SEC00 00_0000_0111_0000_0001 TLMU/CMATRIX1/SEC01 00_0000_1110_0000_0010 TLMU/CMATRIX1/SEC02 00_0001_1100_0000_0100 TLMU/CMATRIX1/SEC03 00_0011_1000_0000_1000 TLMU/CMATRIX1/SEC04 00_0111_0000_0001_0000 TLMU/CMATRIX1/SEC05 00_1110_0000_0010_0000 TLMU/CMATRIX1/SEC06 01_1100_0000_0100_0000 TLMU/CMATRIX1/SEC07 11_1000_0000_1000_0000 TLMU/CMATRIX1/SEC08 11_0000_0001_0000_0001 TLMU/CMATRIX1/SEC09 10_0000_0010_0000_0011 TLMU/CMATRIX1/SEC10 00_0000_0100_0000_0111 TLMU/CMATRIX1/SEC11 00_0000_1000_0000_1110 TLMU/CMATRIX1/SEC12 00_0001_0000_0001_1100 TLMU/CMATRIX1/SEC13 00_0010_0000_0011_1000 TLMU/CMATRIX1/SEC14 00_0100_0000_0111_0000 TLMU/CMATRIX1/SEC15 00_1000_0000_1110_0000 TLMU/CMATRIX1/SEC16 01_0000_0001_1100_0000 TLMU/CMATRIX1/SEC17 10_0000_0011_1000_0000 TLMU/CMATRIX2/SEC00 00_0000_1111_1000_0001 TLMU/CMATRIX2/SEC01 00_0001_1111_0000_0010 TLMU/CMATRIX2/SEC02 00_0011_1110_0000_0100 TLMU/CMATRIX2/SEC03 00_0111_1100_0000_1000 TLMU/CMATRIX2/SEC04 00_1111_1000_0001_0000 TLMU/CMATRIX2/SEC05 01_1111_0000_0010_0000 TLMU/CMATRIX2/SEC06 11_1110_0000_0100_0000 TLMU/CMATRIX2/SEC07 11_1100_0000_1000_0001 TLMU/CMATRIX2/SEC08 11_1000_0001_0000_0011 TLMU/CMATRIX2/SEC09 11_0000_0010_0000_0111 TLMU/CMATRIX2/SEC10 10_0000_0100_0000_1111 TLMU/CMATRIX2/SEC11 00_0000_1000_0001_1111 TLMU/CMATRIX2/SEC12 00_0001_0000_0011_1110 TLMU/CMATRIX2/SEC13 00_0010_0000_0111_1100 TLMU/CMATRIX2/SEC14 00_0100_0000_1111_1000 TLMU/CMATRIX2/SEC15 00_1000_0001_1111_0000 TLMU/CMATRIX2/SEC16 01_0000_0011_1110_0000 TLMU/CMATRIX2/SEC17 10_0000_0111_1100_0000 # Multiplicity counter setup (where to slice) . # there are 9 slices with lower and upper thresholds TLMU/MCNTR0/THR 5 20 TLMU/MCNTR1/THR 20 100 TLMU/MCNTR2/THR 100 200 TLMU/MCNTR3/THR 200 300 TLMU/MCNTR4/THR 300 400 TLMU/MCNTR5/THR 400 500 TLMU/MCNTR6/THR 500 520 TLMU/MCNTR7/THR 520 576 TLMU/MCNTR8/THR 1 576 # Assign signal to output. CM means CMATRIX and MC means Multiplicity counter # SEQ [0..4] means trigger sequencer. NONE will not assign anything # # channel 0 1 2 3 4 5 6 7 TLMU/OUTMUX CM1 MC2 MC3 MC4 MC5 MC6 MC7 MC8 # FEBs # basically thresholds and delay (T0 has 12 channels, and V0 has 8 channels) # V0 has 4 sections named V0, V1, V2, V3 # Delay is 0 to 31, with 1/4 BC precision (max delay is then 8 BCs) # The value can take here is from 0 to 255 for threshold and 0 to 31 for delay FEB/T0/A/THR 10 10 10 10 10 10 10 10 10 10 10 10 FEB/T0/A/DELAY 1 1 1 1 1 1 1 1 1 1 1 1 FEB/T0/C/THR 10 10 10 10 10 10 10 10 10 10 10 10 FEB/T0/C/DELAY 1 1 1 1 1 1 1 1 1 1 1 1 FEB/V0/A0/THR 10 10 10 10 10 10 10 10 FEB/V0/A1/THR 10 10 10 10 10 10 10 10 FEB/V0/A2/THR 10 10 10 10 10 10 10 10 FEB/V0/A3/THR 10 10 10 10 10 10 10 10 FEB/V0/A0/DELAY 1 1 1 1 1 1 1 1 FEB/V0/A1/DELAY 1 1 1 1 1 1 1 1 FEB/V0/A2/DELAY 1 1 1 1 1 1 1 1 FEB/V0/A3/DELAY 1 1 1 1 1 1 1 1 FEB/V0/C0/THR 10 10 10 10 10 10 10 10 FEB/V0/C1/THR 10 10 10 10 10 10 10 10 FEB/V0/C2/THR 10 10 10 10 10 10 10 10 FEB/V0/C3/THR 10 10 10 10 10 10 10 10 FEB/V0/C0/DELAY 1 1 1 1 1 1 1 1 FEB/V0/C1/DELAY 1 1 1 1 1 1 1 1 FEB/V0/C2/DELAY 1 1 1 1 1 1 1 1 FEB/V0/C3/DELAY 1 1 1 1 1 1 1 1 # Lookup table at FEB FEB/T0/A/LUT/0 M(1111_1111_1111)>0 # maybe also logical equations FEB/T0/A/LUT/1 M(1111_1111_1111)>4 FEB/V0/A0/LUT/0 M(1111_1111)>0 FEB/V0/A0/LUT/1 M(1111_1111)>2 FEB/V0/A1/LUT/0 M(1111_1111)>0 FEB/V0/A1/LUT/1 M(1111_1111)>2 FEB/V0/A2/LUT/0 M(1111_1111)>0 FEB/V0/A2/LUT/1 M(1111_1111)>2 FEB/V0/A3/LUT/0 M(1111_1111)>0 FEB/V0/A3/LUT/1 M(1111_1111)>2 FEB/T0/C/LUT/0 M(1111_1111_1111)>0 FEB/T0/C/LUT/1 M(1111_1111_1111)>4 FEB/V0/C0/LUT/0 M(1111_1111)>0 FEB/V0/C0/LUT/1 M(1111_1111)>2 FEB/V0/C1/LUT/0 M(1111_1111)>0 FEB/V0/C1/LUT/1 M(1111_1111)>2 FEB/V0/C2/LUT/0 M(1111_1111)>0 FEB/V0/C2/LUT/1 M(1111_1111)>2 FEB/V0/C3/LUT/0 M(1111_1111)>0 FEB/V0/C3/LUT/1 M(1111_1111)>2 # Lookup table at CB-AC CBA/LUT/0 T0_0 || ( V0-0_0 || V0-1_0 || V0-2_0 || V0-3_0 ) CBA/LUT/1 !T0_1 && !V0-0_1 && !V0-1_1 && !V0-2_1 && !V0-3_1 CBC/LUT/0 T0_0 || ( V0-0_0 || V0-1_0 || V0-2_0 || V0-3_0 ) CBC/LUT/1 !T0_1 && !V0-0_1 && !V0-1_1 && !V0-2_1 && !V0-3_1 # Lookup table at CB-B CBB/LUT/0 ( CB-A_1 && !CB-C_1 ) && TLMU_7 CBB/LUT/1 ( !CB-A_1 && CB-C_1 ) && TLMU_7 CBB/LUT/2 ( CB-A_1 && CB-C_1 ) && TLMU_7 # Timing parameter for trigger processor CBB/TRG/L0A 43 # comment CBB/TRG/L0S 47 CBB/TRG/L1A 308 CBB/TRG/L1S 311 CBB/TRG/DEAD/PT 200 CBB/TRG/DEAD/L0 350 CBB/TRG/DEAD/L1 500 CBB/TRG/DELAY/L0 46 CBB/TRG/CTRL/SM_TO_CTP YES CBB/TRG/CTRL/TRG_EMU YES CBB/TRG/CTRL/A/VALUE 0 CBB/TRG/CTRL/A/OVR NO CBB/TRG/CTRL/B/VALUE 0 CBB/TRG/CTRL/B/OVR NO CBB/TRG/A/DIS YES # do not change! CBB/TRG/TIN/0 0 # normal triggering (should be 0!) CBB/TRG/TIN/1 0 # normal triggering (should be 0!) CBB/PT/CBA/SAMPL 0 CBB/PT/CBC/SAMPL 0 CBB/PT/ALIGN/CB-A_0/STRETCH 0 CBB/PT/ALIGN/CB-A_0/DELAY 0 CBB/PT/ALIGN/CB-A_1/STRETCH 0 CBB/PT/ALIGN/CB-A_1/DELAY 0 CBB/PT/ALIGN/CB-C_0/STRETCH 0 CBB/PT/ALIGN/CB-C_0/DELAY 0 CBB/PT/ALIGN/CB-C_1/STRETCH 0 CBB/PT/ALIGN/CB-C_1/DELAY 0 CBB/PT/ALIGN/RND/STRETCH 0 CBB/PT/ALIGN/RND/DELAY 0 CBB/PT/ALIGN/BC/STRETCH 0 CBB/PT/ALIGN/BC/DELAY 0 CBB/PT/ALIGN/TLMU_0/STRETCH 0 CBB/PT/ALIGN/TLMU_0/DELAY 0 CBB/PT/ALIGN/TLMU_1/STRETCH 0 CBB/PT/ALIGN/TLMU_1/DELAY 0 CBB/PT/ALIGN/TLMU_2/STRETCH 0 CBB/PT/ALIGN/TLMU_2/DELAY 0 CBB/PT/ALIGN/TLMU_3/STRETCH 0 CBB/PT/ALIGN/TLMU_3/DELAY 0 CBB/PT/ALIGN/TLMU_4/STRETCH 0 CBB/PT/ACBB/LIGN/TLMU_4/DELAY 0 CBB/PT/ALIGN/TLMU_5/STRETCH 0 CBB/PT/ALIGN/TLMU_5/DELAY 0 CBB/PT/ALIGN/TLMU_6/STRETCH 0 CBB/PT/ALIGN/TLMU_6/DELAY 0 CBB/PT/ALIGN/TLMU_7/STRETCH 0 CBB/PT/ALIGN/TLMU_7/DELAY 0 CBB/PT/ALIGN/CB-B_0/STRETCH 0 CBB/PT/ALIGN/CB-B_0/DELAY 0 CBB/PT/ALIGN/CB-B_1/STRETCH 0 CBB/PT/ALIGN/CB-B_1/DELAY 0 CBB/BUSY/CTRL 0 CBB/RND/THR 150000 CBB/BC/RESET_VALUE 222 CBB/PT/MASK/CB-A_0 YES CBB/PT/MASK/CB-A_1 NO CBB/PT/MASK/CB-C_0 YES CBB/PT/MASK/CB-C_1 NO CBB/PT/MASK/RND NO CBB/PT/MASK/BC NO CBB/PT/MASK/TLMU_0 YES CBB/PT/MASK/TLMU_1 YES CBB/PT/MASK/TLMU_2 YES CBB/PT/MASK/TLMU_3 YES CBB/PT/MASK/TLMU_4 YES CBB/PT/MASK/TLMU_5 YES CBB/PT/MASK/TLMU_6 YES CBB/PT/MASK/TLMU_7 NO CBB/PT/MASK/CB-B_0 YES CBB/PT/MASK/CB-B_1 YES CBB/PT/MASK/CB-B_2 YES # EOF