-/**************************************************************************\r
- * Copyright(c) 1998-1999, ALICE Experiment at CERN, All rights reserved. *\r
- * *\r
- * Author: The ALICE Off-line Project. *\r
- * Contributors are mentioned in the code where appropriate. *\r
- * *\r
- * Permission to use, copy, modify and distribute this software and its *\r
- * documentation strictly for non-commercial purposes is hereby granted *\r
- * without fee, provided that the above copyright notice appears in all *\r
- * copies and that both the copyright notice and this permission notice *\r
- * appear in the supporting documentation. The authors make no claims *\r
- * about the suitability of this software for any purpose. It is *\r
- * provided "as is" without express or implied warranty. *\r
- **************************************************************************/\r
-\r
-// \r
-// Class AliVZEROLogicalSignal\r
-// ---------------------------\r
-// Describes a logical signal in the electronics. \r
-// Use it to generate observation windows\r
-// which are used by AliVZEROTriggerSimulator class\r
-// \r
-\r
-#include "AliLog.h"\r
-#include "AliVZEROLogicalSignal.h"\r
-\r
-ClassImp(AliVZEROLogicalSignal)\r
-\r
-//_____________________________________________________________________________\r
-AliVZEROLogicalSignal::AliVZEROLogicalSignal() : TObject(), fStart(0.), fStop(0.)\r
-{\r
- // Default constructor\r
-}\r
-//_____________________________________________________________________________\r
-AliVZEROLogicalSignal::AliVZEROLogicalSignal(Float_t start, Float_t stop) : TObject(), fStart(start), fStop(stop)\r
-{\r
- // Constructor using start and stop time\r
- if(fStart>fStop) AliError("Logical Signal has a Start time AFTER the Stop time");\r
- if(fStart==fStop) AliWarning("Logical Signal has a zero width");\r
-}\r
-//_____________________________________________________________________________\r
-AliVZEROLogicalSignal::AliVZEROLogicalSignal(UShort_t profilClock, UInt_t delay) : TObject(), fStart(0.), fStop(0.)\r
-{\r
- // Constructor using the profilClock and delay parameters comming from the FEE\r
- \r
- Bool_t word;\r
- Bool_t up=kFALSE;\r
- Bool_t down=kFALSE;\r
- \r
- for(int i=0 ; i<5 ; i++) {\r
- word = (profilClock >> i) & 0x1;\r
- if(word&&!up) {\r
- fStart = 5. * i;\r
- up = kTRUE;\r
- }\r
- if(!word&&up&&!down) {\r
- fStop = 5. * i;\r
- down = kTRUE;\r
- } \r
- }\r
- if(!down) fStop = 25.;\r
- \r
- fStart += delay*10.e-3; // Add 10 ps par register unit\r
- fStop += delay*10.e-3; \r
-}\r
-//_____________________________________________________________________________\r
-AliVZEROLogicalSignal::AliVZEROLogicalSignal(const AliVZEROLogicalSignal &signal) : \r
- TObject(), fStart(signal.fStart), \r
- fStop(signal.fStop)\r
-{\r
- // Copy constructor\r
-}\r
-\r
-//_____________________________________________________________________________\r
-AliVZEROLogicalSignal::~AliVZEROLogicalSignal(){\r
- // Destructor\r
-}\r
-\r
-//_____________________________________________________________________________\r
-AliVZEROLogicalSignal& AliVZEROLogicalSignal::operator = \r
-(const AliVZEROLogicalSignal& signal)\r
-{\r
- // Operator =\r
- fStart = signal.fStart;\r
- fStop = signal.fStop;\r
- return *this;\r
-}\r
-\r
-//_____________________________________________________________________________\r
-AliVZEROLogicalSignal AliVZEROLogicalSignal::operator|(const AliVZEROLogicalSignal& signal) const \r
-{\r
- // Perform the Logical OR of two signals: C = A or B\r
- if((fStart>signal.fStop) || (signal.fStart>fStop))\r
- AliError(Form("Both signal do not superpose in time.\n Start(A) = %f Stop(A) = %f\n Start(B) = %f Stop(B) = %f",fStart, fStop, signal.fStart,signal.fStop));\r
- \r
- AliVZEROLogicalSignal result;\r
- if(fStart<signal.fStart) result.fStart = fStart;\r
- else result.fStart = signal.fStart;\r
- \r
- if(fStop>signal.fStop) result.fStop = fStop;\r
- else result.fStop = signal.fStop;\r
- \r
- return result;\r
-}\r
-//_____________________________________________________________________________\r
-AliVZEROLogicalSignal AliVZEROLogicalSignal::operator&(const AliVZEROLogicalSignal& signal) const\r
-{\r
- // Perform the Logical AND of two signals: C = A and B\r
- if((fStart>signal.fStop) || (signal.fStart>fStop))\r
- AliError(Form("Both signal do not superpose in time.\n Start(A) = %f Stop(A) = %f\n Start(B) = %f Stop(B) = %f",fStart, fStop, signal.fStart,signal.fStop));\r
- \r
- AliVZEROLogicalSignal result;\r
- if(fStart>signal.fStart) result.fStart = fStart;\r
- else result.fStart = signal.fStart;\r
- \r
- if(fStop<signal.fStop) result.fStop = fStop;\r
- else result.fStop = signal.fStop;\r
- \r
- return result;\r
-}\r
-\r
-//_____________________________________________________________________________\r
-Bool_t AliVZEROLogicalSignal::IsInCoincidence(Float_t time) const\r
-{\r
- // Check if a signal arriving at the time "time" is in coincidence with the logical signal\r
- Bool_t result = kFALSE;\r
- if((time>fStart) && (time<fStop)) result = kTRUE;\r
- return result;\r
-}\r
-\r
+/**************************************************************************
+ * Copyright(c) 1998-1999, ALICE Experiment at CERN, All rights reserved. *
+ * *
+ * Author: The ALICE Off-line Project. *
+ * Contributors are mentioned in the code where appropriate. *
+ * *
+ * Permission to use, copy, modify and distribute this software and its *
+ * documentation strictly for non-commercial purposes is hereby granted *
+ * without fee, provided that the above copyright notice appears in all *
+ * copies and that both the copyright notice and this permission notice *
+ * appear in the supporting documentation. The authors make no claims *
+ * about the suitability of this software for any purpose. It is *
+ * provided "as is" without express or implied warranty. *
+ **************************************************************************/
+
+//
+// Class AliVZEROLogicalSignal
+// ---------------------------
+// Describes a logical signal in the electronics.
+// Use it to generate observation windows
+// which are used by AliVZEROTriggerSimulator class
+//
+
+#include "AliLog.h"
+#include "AliVZEROLogicalSignal.h"
+
+ClassImp(AliVZEROLogicalSignal)
+
+//_____________________________________________________________________________
+AliVZEROLogicalSignal::AliVZEROLogicalSignal() : TObject(), fStart(0.), fStop(0.)
+{
+ // Default constructor
+}
+//_____________________________________________________________________________
+AliVZEROLogicalSignal::AliVZEROLogicalSignal(UShort_t profilClock, UInt_t delay) : TObject(), fStart(0.), fStop(0.)
+{
+ // Constructor using the profilClock and delay parameters comming from the FEE
+
+ Bool_t word;
+ Bool_t up=kFALSE;
+ Bool_t down=kFALSE;
+
+ for(int i=0 ; i<5 ; i++) {
+ Int_t shift = (i<4) ? (3-i) : 4;
+ word = (profilClock >> shift) & 0x1;
+ if(word&&!up) {
+ fStart = 5. * (i + 1);
+ up = kTRUE;
+ }
+ if(!word&&up&&!down) {
+ fStop = 5. * (i + 1);
+ down = kTRUE;
+ }
+ }
+ if(!down) fStop = 30.;
+
+ fStart += delay*1e-2; // Add 10 ps par register unit
+ fStop += delay*1e-2;
+}
+//_____________________________________________________________________________
+AliVZEROLogicalSignal::AliVZEROLogicalSignal(const AliVZEROLogicalSignal &signal) :
+ TObject(), fStart(signal.fStart),
+ fStop(signal.fStop)
+{
+ // Copy constructor
+}
+
+//_____________________________________________________________________________
+AliVZEROLogicalSignal::~AliVZEROLogicalSignal(){
+ // Destructor
+}
+
+//_____________________________________________________________________________
+AliVZEROLogicalSignal& AliVZEROLogicalSignal::operator =
+(const AliVZEROLogicalSignal& signal)
+{
+ // Operator =
+ if(&signal == this) return *this;
+ fStart = signal.fStart;
+ fStop = signal.fStop;
+ return *this;
+}
+
+//_____________________________________________________________________________
+AliVZEROLogicalSignal AliVZEROLogicalSignal::operator|(const AliVZEROLogicalSignal& signal) const
+{
+ // Perform the Logical OR of two signals: C = A or B
+ if((fStart>signal.fStop) || (signal.fStart>fStop))
+ AliError(Form("Both signal do not superpose in time.\n Start(A) = %f Stop(A) = %f\n Start(B) = %f Stop(B) = %f",fStart, fStop, signal.fStart,signal.fStop));
+
+ AliVZEROLogicalSignal result;
+ if(fStart<signal.fStart) result.fStart = fStart;
+ else result.fStart = signal.fStart;
+
+ if(fStop>signal.fStop) result.fStop = fStop;
+ else result.fStop = signal.fStop;
+
+ return result;
+}
+//_____________________________________________________________________________
+AliVZEROLogicalSignal AliVZEROLogicalSignal::operator&(const AliVZEROLogicalSignal& signal) const
+{
+ // Perform the Logical AND of two signals: C = A and B
+ if((fStart>signal.fStop) || (signal.fStart>fStop))
+ AliError(Form("Both signal do not superpose in time.\n Start(A) = %f Stop(A) = %f\n Start(B) = %f Stop(B) = %f",fStart, fStop, signal.fStart,signal.fStop));
+
+ AliVZEROLogicalSignal result;
+ if(fStart>signal.fStart) result.fStart = fStart;
+ else result.fStart = signal.fStart;
+
+ if(fStop<signal.fStop) result.fStop = fStop;
+ else result.fStop = signal.fStop;
+
+ return result;
+}
+
+//_____________________________________________________________________________
+Bool_t AliVZEROLogicalSignal::IsInCoincidence(Float_t time) const
+{
+ // Check if a signal arriving at the time "time" is in coincidence with the logical signal
+ Bool_t result = kFALSE;
+ if((time>fStart) && (time<fStop)) result = kTRUE;
+ return result;
+}
+
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