1. Leading time was not decoded properly (there are coarse and fine gains in the...

1. Leading time was not decoded properly (there are coarse and fine gains in the HPTDC which I did not not about). 2. HPTDC were written in raw data from 7 to 0 within a ring whereas for everything else it was from 0 to 7.  This was Yannick's mistake  but he did not want to change the programming of his FPGAs so I had to change it in aliroot. 3. All the ADCs in Float_t instead of integers. (Brigitter). Changes in the ESD classes were agreed by Andreas, Rene confirmed that the schema evolution will handle them properly.