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Some hick-up with common blocks solved.
[u/mrichter/AliRoot.git] / TRD / AliTRDrawTPStream.cxx
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94ac01ef 1#/**************************************************************************\r\r
2* Copyright(c) 1998-1999, ALICE Experiment at CERN, All rights reserved. *\r\r
3* *\r\r
4* Author: The ALICE Off-line Project. *\r\r
5* Contributors are mentioned in the code where appropriate. *\r\r
6* *\r\r
7* Permission to use, copy, modify and distribute this software and its *\r\r
8* documentation strictly for non-commercial purposes is hereby granted *\r\r
9* without fee, provided that the above copyright notice appears in all *\r\r
10* copies and that both the copyright notice and this permission notice *\r\r
11* appear in the supporting documentation. The authors make no claims *\r\r
12* about the suitability of this software for any purpose. It is *\r\r
13* provided "as is" without express or implied warranty. *\r\r
14**************************************************************************/\r\r
15\r\r
16/* $Id: AliTRDrawTPStream.cxx 27797 2008-08-05 14:37:22Z cblume $ */\r\r
17\r\r
18///////////////////////////////////////////////////////////////////////////////////////\r\r
19// //\r\r
20// This class provides access to pattern generated TRD raw data including //\r\r
21// configuration data. //\r\r
22// //\r\r
23// It is based on Venelin Angelov's c++ code decoding standalone // \r\r
24// configuration data // \r\r
25// http://alice.physi.uni-heidelberg.de/svn/trd/wconfigurations/trunk/C/trap_cnf.cpp //\r\r
26// http://alice.physi.uni-heidelberg.de/svn/trd/wconfigurations/trunk/C/trap_cnf.h //\r\r
27// //\r\r
28// Author: MinJung Kweon(minjung@physi.uni-heidelberg.de) // \r\r
29// //\r\r
30///////////////////////////////////////////////////////////////////////////////////////\r\r
31\r\r
32//#include "AliLog.h"\r\r
33\r\r
34#include "AliTRDrawStream.h"\r\r
35#include "AliTRDrawTPStream.h"\r\r
36\r\r
37\r\r
38#define GET_VALUE_AT(w,m,s) (( (w) >> (s)) & (m) )\r\r
39#define MCM_HEADER_MASK_ERR(w) ( ((w) & (0xf)) == (0xc) ? 0 : 1) \r\r
40#define MCM_ROB_NUMBER(w) GET_VALUE_AT(w,0x7,28)\r\r
41#define MCM_MCM_NUMBER(w) GET_VALUE_AT(w,0x0f,24)\r\r
42#define MCM_EVENT_COUNTER(w) GET_VALUE_AT(w,0x00fffff,4)\r\r
43\r\r
44\r\r
45\r\r
46ClassImp(AliTRDrawTPStream)\r\r
47\r\r
48//---------------------------------------------------------------------\r\r
49AliTRDrawTPStream::AliTRDrawTPStream(Int_t rawVMajorOpt, UInt_t * pPos)\r\r
50 : AliTRDrawStreamBase()\r\r
51 , fTrapReg() \r\r
52 , fCmdReg() \r\r
53 , fRoReg() \r\r
54 , fCnfPro()\r\r
55 , fDmemValid()\r\r
56 , fRegs()\r\r
57 , fDmem()\r\r
58 , fDbank()\r\r
59 , fDbankPro()\r\r
60 , fpPos(pPos)\r\r
61 , fRawVMajorOpt(rawVMajorOpt) \r\r
62{\r\r
63 //\r\r
64 // default constructor\r\r
65 //\r\r
66\r\r
67 if (FillConfig() == kFALSE)\r\r
68 AliError("Reading reset value failed.");\r\r
69\r\r
70}\r\r
71\r\r
72//---------------------------------------------------------------------\r\r
73AliTRDrawTPStream::AliTRDrawTPStream(const AliTRDrawTPStream& /*st*/)\r\r
74 : AliTRDrawStreamBase()\r\r
75 , fTrapReg() \r\r
76 , fCmdReg() \r\r
77 , fRoReg() \r\r
78 , fCnfPro()\r\r
79 , fDmemValid()\r\r
80 , fRegs()\r\r
81 , fDmem()\r\r
82 , fDbank()\r\r
83 , fDbankPro()\r\r
84 , fpPos()\r\r
85 , fRawVMajorOpt() \r\r
86{\r\r
87 //\r\r
88 // copy constructor\r\r
89 //\r\r
90\r\r
91 AliError("Not implemeneted.");\r\r
92\r\r
93}\r\r
94\r\r
95//---------------------------------------------------------------------\r\r
96AliTRDrawTPStream &\r\r
97AliTRDrawTPStream::operator=(const AliTRDrawTPStream &)\r\r
98{\r\r
99 //\r\r
100 // we are not using this functionality\r\r
101 //\r\r
102 AliFatal("May not use.");\r\r
103 return *this;\r\r
104}\r\r
105\r\r
106//---------------------------------------------------------------------\r\r
107AliTRDrawTPStream::~AliTRDrawTPStream()\r\r
108{\r\r
109 //\r\r
110 // destructor\r\r
111 //\r\r
112}\r\r
113\r\r
114//---------------------------------------------------------------------\r\r
115Bool_t AliTRDrawTPStream::DecodeTPdata()\r\r
116{\r\r
117 //\r\r
118 // main function to decode test pattern data \r\r
119 // fRawVMajorOpt version control different type of test pattern data\r\r
120 //\r\r
121\r\r
122 if (fRawVMajorOpt == 7)\r\r
123 {\r\r
124 AliInfo("This is configuration data event read by first trigger.");\r\r
125 if(!AliTRDrawStream::fgEnableDecodeConfigData) return kTRUE;\r\r
126 if (DecodeConfigdata() == kFALSE) // configuration data \r\r
127 {\r\r
128 AliError("failed to to decode configuration data");\r\r
129 return kFALSE;\r\r
130 }\r\r
131 else \r\r
132 return kTRUE;\r\r
133 }\r\r
134 else\r\r
135 AliError("These are different type of test pattern data. You need other reader");\r\r
136\r\r
137 return kFALSE;\r\r
138}\r\r
139\r\r
140//---------------------------------------------------------------------\r\r
141Bool_t AliTRDrawTPStream::DecodeConfigdata()\r\r
142{\r\r
143 //\r\r
144 // main function to decode trap configuration data \r\r
145 //\r\r
146\r\r
147 UInt_t packedConf[256];\r\r
148 Int_t mcmPos, mcmsRead, lengthPacked;\r\r
149\r\r
150 mcmsRead = 0;\r\r
151 do\r\r
152 {\r\r
153 mcmPos = ReadPacked(fpPos, packedConf, &lengthPacked);\r\r
154 if (mcmPos >= 0)\r\r
155 {\r\r
156 PowerUp();\r\r
157 UnPackConfN(packedConf, lengthPacked);\r\r
158 DumpCnf(mcmPos);\r\r
159 mcmsRead++;\r\r
160 AliInfo(Form("%d MCMs read up to now, last was MCM%02d\n",mcmsRead, mcmPos));\r\r
161 }\r\r
162 } while ((mcmsRead < 84) && (mcmPos >= 0)); // [mj] have to think about # of mcmsRead\r\r
163 AliInfo("Done\n");\r\r
164\r\r
165 return kTRUE;\r\r
166}\r\r
167\r\r
168//---------------------------------------------------------------------\r\r
169Int_t AliTRDrawTPStream::ReadPacked(UInt_t *word, UInt_t *pData, Int_t * const nWords)\r\r
170{\r\r
171 //\r\r
172 // decode packed data words\r\r
173 //\r\r
174\r\r
175 UInt_t vword = *word;\r\r
176\r\r
177 Int_t iLength;\r\r
178 UInt_t err, robNum, mcmNum, chipId, noEndMarker;\r\r
179\r\r
180 iLength = 0;\r\r
181 err = 0;\r\r
182\r\r
183 // decode mcm header\r\r
184 if(MCM_HEADER_MASK_ERR(vword)) err++;\r\r
185\r\r
186 robNum = MCM_ROB_NUMBER(vword);\r\r
187 mcmNum = MCM_MCM_NUMBER(vword);\r\r
188 chipId = MCM_EVENT_COUNTER(vword);\r\r
189\r\r
190 if (err == 0) {\r\r
191 AliInfo(Form("MCM header ROB %d, MCM %02d, ChipId %d 0x%05x\n", robNum, mcmNum, chipId, chipId));\r\r
192 }\r\r
193 else \r\r
194 return -1;\r\r
195\r\r
196 // read MCM data and store into array\r\r
197 noEndMarker = 1;\r\r
198 do\r\r
199 {\r\r
200 word++;\r\r
201 vword = *word;\r\r
202\r\r
203 noEndMarker = ((vword != ENDM_CONF) && (vword != (ENDM_CONF | 1)) && (vword != 0x10001000));\r\r
204 *pData = vword;\r\r
205 pData++;\r\r
206 iLength++;\r\r
207 } while (noEndMarker && (iLength < 256));\r\r
208\r\r
209 word++; \r\r
210 fpPos = word;\r\r
211\r\r
212 *nWords = iLength;\r\r
213 if (iLength == 0) \r\r
214 return -1;\r\r
215 else\r\r
216 return mcmNum;\r\r
217}\r\r
218\r\r
219//---------------------------------------------------------------------\r\r
220void AliTRDrawTPStream::PowerUp() // power up\r\r
221{\r\r
222 //\r\r
223 // copy the reset values \r\r
224 //\r\r
225\r\r
226 for (Int_t i=0; i< NREGS; i++)\r\r
227 {\r\r
228 fRegs[i] = fTrapReg[i].fResVal;\r\r
229 fCnfPro[i] = 0;\r\r
230 }\r\r
231 // mark all DMEM cells as invalid\r\r
232 for (Int_t i=0; i< NDMEM; i++) fDmemValid[i] = 0;\r\r
233 // mark all DBANK cells as empty\r\r
234 for (Int_t i=0; i< NDBANK; i++) fDbankPro[i] = kDbankEmpty;\r\r
235}\r\r
236\r\r
237\r\r
238//---------------------------------------------------------------------\r\r
239Int_t AliTRDrawTPStream::UnPackConfN(const UInt_t *pData, Int_t maxLength)\r\r
240{\r\r
241 //\r\r
242 // unpack configuration\r\r
243 //\r\r
244\r\r
245 Int_t debug = 0; // the debug mode not completely ready\r\r
246 Int_t step, bwidth, nwords, idx, err, exitFlag, bitcnt, werr;\r\r
247 UInt_t caddr;\r\r
248 UInt_t dat, msk, header, dataHi;\r\r
249\r\r
250 idx = 0; // index in PackedConf\r\r
251 err = 0;\r\r
252 while (idx < maxLength)\r\r
253 {\r\r
254 header = *pData;\r\r
255 if (debug) printf("read 0x%08x ",header);\r\r
256 pData++;\r\r
257 idx++;\r\r
258 if (header & 0x01) // single data\r\r
259 {\r\r
260 dat = (header >> 2) & 0xFFFF; // 16 bit data\r\r
261 caddr = (header >> 18) & 0x3FFF; // 14 bit address\r\r
262 if (caddr != 0x1FFF) // temp!!! because the end marker was wrong\r\r
263 {\r\r
264 if (header & 0x02) // check if > 16 bits\r\r
265 {\r\r
266 dataHi = *pData;\r\r
267 if (debug) printf("read 0x%08x ",dataHi);\r\r
268 pData++;\r\r
269 idx++;\r\r
270 err += ((dataHi ^ (dat | 1)) & 0xFFFF) != 0;\r\r
271 dat = (dataHi & 0xFFFF0000) | dat;\r\r
272 }\r\r
273 if (debug) printf("addr=0x%04x (%s) data=0x%08x\n",caddr, Addr2Name(caddr), dat);\r\r
274 werr = SetU(caddr, dat);\r\r
275 if (werr < 0)\r\r
276 {\r\r
277 printf("(single-write): non-existing address 0x%04x containing 0x%08x\n", caddr, header);\r\r
278 }\r\r
279 if (idx > maxLength)\r\r
280 {\r\r
281 printf("(single-write): no more data, missing end marker\n");\r\r
282 return -err;\r\r
283 }\r\r
284 }\r\r
285 else\r\r
286 {\r\r
287 printf("(single-write): address 0x%04x => old endmarker?\n",caddr);\r\r
288 return err;\r\r
289 }\r\r
290 }\r\r
291 else // block of data\r\r
292 {\r\r
293 step = (header >> 1) & 0x0003;\r\r
294 bwidth = ((header >> 3) & 0x001F) + 1;\r\r
295 nwords = (header >> 8) & 0x00FF;\r\r
296 caddr = (header >> 16) & 0xFFFF;\r\r
297 exitFlag = (step == 0) || (step == 3) || (nwords == 0);\r\r
298 if (exitFlag) return err;\r\r
299 switch (bwidth)\r\r
300 {\r\r
301 case 15:\r\r
302 case 10:\r\r
303 case 7:\r\r
304 case 6:\r\r
305 case 5:\r\r
306 {\r\r
307 msk = (1 << bwidth) - 1;\r\r
308 bitcnt = 0;\r\r
309 while (nwords > 0)\r\r
310 {\r\r
311 nwords--;\r\r
312 bitcnt -= bwidth;\r\r
313 if (bitcnt < 0)\r\r
314 {\r\r
315 header = *pData;\r\r
316 if (debug) printf("read 0x%08x ",header);\r\r
317 pData++;\r\r
318 idx++;\r\r
319 err += (header & 1);\r\r
320 header = header >> 1;\r\r
321 bitcnt = 31 - bwidth;\r\r
322 }\r\r
323 if (debug) printf("addr=0x%04x (%s) data=0x%08x\n",caddr, Addr2Name(caddr), header & msk);\r\r
324 werr = SetU(caddr, header & msk);\r\r
325 if (werr < 0)\r\r
326 {\r\r
327 printf("(single-write): non-existing address 0x%04x containing 0x%08x\n", caddr, header);\r\r
328 }\r\r
329 caddr += step;\r\r
330 header = header >> bwidth;\r\r
331 if (idx >= maxLength)\r\r
332 {\r\r
333 printf("(block-write): no end marker! %d words read\n",idx);\r\r
334 return -err;\r\r
335 }\r\r
336 }\r\r
337 break;\r\r
338 } // end case 5-15\r\r
339 case 31:\r\r
340 {\r\r
341 while (nwords > 0)\r\r
342 {\r\r
343 header = *pData;\r\r
344 if (debug) printf("read 0x%08x ",header);\r\r
345 pData++;\r\r
346 idx++;\r\r
347 nwords--;\r\r
348 err += (header & 1);\r\r
349 if (debug) printf("addr=0x%04x (%s) data=0x%08x\n",caddr, Addr2Name(caddr), header >> 1);\r\r
350 werr = SetU(caddr, header >> 1);\r\r
351 if (werr < 0)\r\r
352 {\r\r
353 printf("(single-write): non-existing address 0x%04x containing 0x%08x\n", caddr, header);\r\r
354 }\r\r
355 caddr += step;\r\r
356 if (idx >= maxLength)\r\r
357 {\r\r
358 printf("no end marker! %d words read\n",idx);\r\r
359 return -err;\r\r
360 }\r\r
361 }\r\r
362 break;\r\r
363 }\r\r
364 default: return err;\r\r
365 } // end switch\r\r
366 } // end block case\r\r
367 } // end while\r\r
368 printf("no end marker! %d words read\n",idx);\r\r
369 return -err; // only if the max length of the block reached!\r\r
370}\r\r
371\r\r
372//---------------------------------------------------------------------\r\r
373void AliTRDrawTPStream::DumpCnf(Int_t slv)\r\r
374{\r\r
375 //\r\r
376 // dump configuration\r\r
377 //\r\r
378\r\r
379 UInt_t idx;\r\r
380 for (idx = 0; idx < NREGS; idx++) // config. reg\r\r
381 {\r\r
382 if (slv >= 0)\r\r
383 printf("%s\t0x%08x\t%3d %c\n", fTrapReg[idx].fkName, (Int_t) fRegs[idx], slv, CnfStat(fCnfPro[idx]));\r\r
384 else\r\r
385 printf("%s\t0x%08x %c\n", fTrapReg[idx].fkName, (Int_t) fRegs[idx], CnfStat(fCnfPro[idx]));\r\r
386 }\r\r
387}\r\r
388\r\r
389\r\r
390//---------------------------------------------------------------------\r\r
391const Char_t * AliTRDrawTPStream::Addr2Name(UInt_t addr) const\r\r
392{\r\r
393 //\r\r
394 // return name of a given address\r\r
395 //\r\r
396\r\r
397 Int_t idx;\r\r
398 idx = 0;\r\r
399 if ( ( ( (addr >> 4) & 0xFFE) == 0x0C0) && ( ( (addr >> 2) & 1) == 1) )\r\r
400 {\r\r
401 addr = addr & 0x0C07;\r\r
402 }\r\r
403 while ((idx < NREGS) && (fTrapReg[idx].fAddr != addr) ) idx++;\r\r
404 if (idx < NREGS)\r\r
405 return fTrapReg[idx].fkName;\r\r
406 idx = 0;\r\r
407 while ((idx < NCMD) && (fCmdReg[idx].fAddr != addr)) idx++;\r\r
408 if (idx < NCMD)\r\r
409 return fCmdReg[idx].fkName;\r\r
410 idx = 0;\r\r
411 while ((idx < NRO) && (fRoReg[idx].fAddr != addr)) idx++;\r\r
412 if (idx < NRO)\r\r
413 return fRoReg[idx].fkName;\r\r
414 else\r\r
415 return 0;\r\r
416}\r\r
417\r\r
418//---------------------------------------------------------------------\r\r
419Char_t AliTRDrawTPStream::CnfStat(UInt_t prop) const\r\r
420{\r\r
421 //\r\r
422 // return configuration status\r\r
423 //\r\r
424\r\r
425 if (prop == 0) return 'U';\r\r
426 else\r\r
427 if (prop == 1) return 'R';\r\r
428 else\r\r
429 if (prop == 2) return 'I';\r\r
430 else\r\r
431 return prop;\r\r
432}\r\r
433\r\r
434//---------------------------------------------------------------------\r\r
435Int_t AliTRDrawTPStream::SetU(UInt_t addr, UInt_t newVal)\r\r
436{\r\r
437 //\r\r
438 // set ?\r\r
439 //\r\r
440\r\r
441 Int_t i;\r\r
442 UInt_t maxVal = 0;\r\r
443\r\r
444 if (AddrIsDmem(addr))\r\r
445 {\r\r
446 fDmem[addr & 0x3FF] = newVal;\r\r
447 fDmemValid[addr & 0x3FF] = 1;\r\r
448 return 0;\r\r
449 }\r\r
450 else\r\r
451 if (AddrIsDbank(addr))\r\r
452 {\r\r
453 fDbank[addr & 0xFF] = newVal;\r\r
454 fDbankPro[addr & 0xFF] = kScsnDat;\r\r
455 return 0;\r\r
456 }\r\r
457 else\r\r
458 {\r\r
459 i = Addr2Idx(addr);\r\r
460 if (i < NREGS) // found\r\r
461 {\r\r
462 fCnfPro[i] = 2;\r\r
463 if (fTrapReg[i].fNbits < 32) // create the max value from the number of bits\r\r
464 {\r\r
465 maxVal = 1;\r\r
466 maxVal = (maxVal << fTrapReg[i].fNbits) - 1;\r\r
467 }\r\r
468 if ( (fTrapReg[i].fNbits == 32) || (newVal <= maxVal) ) // in range\r\r
469 {\r\r
470 fRegs[i] = newVal;\r\r
471 return 0;\r\r
472 }\r\r
473 else\r\r
474 { // out of range\r\r
475 fRegs[i] = newVal & maxVal;\r\r
476 printf("Out of range, writing 0x%08x to %d bits at addr = 0x%04x\n",newVal, fTrapReg[i].fNbits, addr);\r\r
477 return -2;\r\r
478 }\r\r
479 }\r\r
480 else // not found\r\r
481 {\r\r
482 printf("(SetU): No such address, writing 0x%08x to addr = 0x%04x\n",newVal, addr);\r\r
483 return -1; // no such address\r\r
484 }\r\r
485 }\r\r
486}\r\r
487\r\r
488//---------------------------------------------------------------------\r\r
489Int_t AliTRDrawTPStream::AddrIsDmem(UInt_t addr) const\r\r
490{\r\r
491 addr = (addr >> 10);\r\r
492 return (addr == 0x30);\r\r
493}\r\r
494\r\r
495//---------------------------------------------------------------------\r\r
496Int_t AliTRDrawTPStream::AddrIsDbank(UInt_t addr) const\r\r
497{\r\r
498 addr = (addr >> 8);\r\r
499 return (addr == 0xF0);\r\r
500}\r\r
501\r\r
502//---------------------------------------------------------------------\r\r
503UInt_t AliTRDrawTPStream::Addr2Idx(UInt_t addr) const\r\r
504{\r\r
505 //\r\r
506 // return index from a given address\r\r
507 //\r\r
508\r\r
509 Int_t idx;\r\r
510 idx = 0;\r\r
511 // check if global const\r\r
512 if ( ( ( (addr >> 4) & 0xFFE) == 0x0C0) && ( ( (addr >> 2) & 1) == 1) )\r\r
513 {\r\r
514 addr = addr & 0x0C07;\r\r
515 }\r\r
516 // searching\r\r
517 while ((idx < NREGS) && (fTrapReg[idx].fAddr != addr)) idx++;\r\r
518 // printf("Addr = 0x%04x; Idx = %d\n",addr, idx); // debugging\r\r
519 return idx;\r\r
520}\r\r
521\r\r
522//---------------------------------------------------------------------\r\r
523Bool_t AliTRDrawTPStream::FillConfig()\r\r
524{\r\r
525 //\r\r
526 // fill array with configuraiton information \r\r
527 //\r\r
528\r\r
529 const SimpleRegs kTrapReg[NREGS] = {\r\r
530 // Name Address Nbits Reset Value\r\r
531 // Global state machine\r\r
532 {"SML0", 0x0A00, 15, 0x4050},\r\r
533 {"SML1", 0x0A01, 15, 0x4200},\r\r
534 {"SML2", 0x0A02, 15, 0x4384},\r\r
535 {"SMMODE", 0x0A03, 16, 0xF0E2},\r\r
536 {"NITM0", 0x0A08, 14, 0x3FFF},\r\r
537 {"NITM1", 0x0A09, 14, 0x3FFF},\r\r
538 {"NITM2", 0x0A0A, 14, 0x3FFF},\r\r
539 {"NIP4D", 0x0A0B, 7, 0x7F},\r\r
540 {"CPU0CLK", 0x0A20, 5, 0x07},\r\r
541 {"CPU1CLK", 0x0A22, 5, 0x07},\r\r
542 {"CPU2CLK", 0x0A24, 5, 0x07},\r\r
543 {"CPU3CLK", 0x0A26, 5, 0x07},\r\r
544 {"NICLK", 0x0A28, 5, 0x07},\r\r
545 {"FILCLK", 0x0A2A, 5, 0x07},\r\r
546 {"PRECLK", 0x0A2C, 5, 0x07},\r\r
547 {"ADCEN", 0x0A2E, 5, 0x07},\r\r
548 {"NIODE", 0x0A30, 5, 0x07},\r\r
549 {"NIOCE", 0x0A32, 5, 0x21}, // bit 5 is status bit (read-only)!\r\r
550 {"NIIDE", 0x0A34, 5, 0x07},\r\r
551 {"NIICE", 0x0A36, 5, 0x07},\r\r
552 // Arbiter\r\r
553 {"ARBTIM", 0x0A3F, 4, 0x0},\r\r
554 // IVT of CPU0\r\r
555 {"IA0IRQ0", 0x0B00, 12, 0x000},\r\r
556 {"IA0IRQ1", 0x0B01, 12, 0x000},\r\r
557 {"IA0IRQ2", 0x0B02, 12, 0x000},\r\r
558 {"IA0IRQ3", 0x0B03, 12, 0x000},\r\r
559 {"IA0IRQ4", 0x0B04, 12, 0x000},\r\r
560 {"IA0IRQ5", 0x0B05, 12, 0x000},\r\r
561 {"IA0IRQ6", 0x0B06, 12, 0x000},\r\r
562 {"IA0IRQ7", 0x0B07, 12, 0x000},\r\r
563 {"IA0IRQ8", 0x0B08, 12, 0x000},\r\r
564 {"IA0IRQ9", 0x0B09, 12, 0x000},\r\r
565 {"IA0IRQA", 0x0B0A, 12, 0x000},\r\r
566 {"IA0IRQB", 0x0B0B, 12, 0x000},\r\r
567 {"IA0IRQC", 0x0B0C, 12, 0x000},\r\r
568 {"IRQSW0", 0x0B0D, 13, 0x1FFF},\r\r
569 {"IRQHW0", 0x0B0E, 13, 0x0000},\r\r
570 {"IRQHL0", 0x0B0F, 13, 0x0000},\r\r
571 // IVT of CPU1\r\r
572 {"IA1IRQ0", 0x0B20, 12, 0x000},\r\r
573 {"IA1IRQ1", 0x0B21, 12, 0x000},\r\r
574 {"IA1IRQ2", 0x0B22, 12, 0x000},\r\r
575 {"IA1IRQ3", 0x0B23, 12, 0x000},\r\r
576 {"IA1IRQ4", 0x0B24, 12, 0x000},\r\r
577 {"IA1IRQ5", 0x0B25, 12, 0x000},\r\r
578 {"IA1IRQ6", 0x0B26, 12, 0x000},\r\r
579 {"IA1IRQ7", 0x0B27, 12, 0x000},\r\r
580 {"IA1IRQ8", 0x0B28, 12, 0x000},\r\r
581 {"IA1IRQ9", 0x0B29, 12, 0x000},\r\r
582 {"IA1IRQA", 0x0B2A, 12, 0x000},\r\r
583 {"IA1IRQB", 0x0B2B, 12, 0x000},\r\r
584 {"IA1IRQC", 0x0B2C, 12, 0x000},\r\r
585 {"IRQSW1", 0x0B2D, 13, 0x1FFF},\r\r
586 {"IRQHW1", 0x0B2E, 13, 0x0000},\r\r
587 {"IRQHL1", 0x0B2F, 13, 0x0000},\r\r
588 // IVT of CPU2\r\r
589 {"IA2IRQ0", 0x0B40, 12, 0x000},\r\r
590 {"IA2IRQ1", 0x0B41, 12, 0x000},\r\r
591 {"IA2IRQ2", 0x0B42, 12, 0x000},\r\r
592 {"IA2IRQ3", 0x0B43, 12, 0x000},\r\r
593 {"IA2IRQ4", 0x0B44, 12, 0x000},\r\r
594 {"IA2IRQ5", 0x0B45, 12, 0x000},\r\r
595 {"IA2IRQ6", 0x0B46, 12, 0x000},\r\r
596 {"IA2IRQ7", 0x0B47, 12, 0x000},\r\r
597 {"IA2IRQ8", 0x0B48, 12, 0x000},\r\r
598 {"IA2IRQ9", 0x0B49, 12, 0x000},\r\r
599 {"IA2IRQA", 0x0B4A, 12, 0x000},\r\r
600 {"IA2IRQB", 0x0B4B, 12, 0x000},\r\r
601 {"IA2IRQC", 0x0B4C, 12, 0x000},\r\r
602 {"IRQSW2", 0x0B4D, 13, 0x1FFF},\r\r
603 {"IRQHW2", 0x0B4E, 13, 0x0000},\r\r
604 {"IRQHL2", 0x0B4F, 13, 0x0000},\r\r
605 // IVT of CPU3\r\r
606 {"IA3IRQ0", 0x0B60, 12, 0x000},\r\r
607 {"IA3IRQ1", 0x0B61, 12, 0x000},\r\r
608 {"IA3IRQ2", 0x0B62, 12, 0x000},\r\r
609 {"IA3IRQ3", 0x0B63, 12, 0x000},\r\r
610 {"IA3IRQ4", 0x0B64, 12, 0x000},\r\r
611 {"IA3IRQ5", 0x0B65, 12, 0x000},\r\r
612 {"IA3IRQ6", 0x0B66, 12, 0x000},\r\r
613 {"IA3IRQ7", 0x0B67, 12, 0x000},\r\r
614 {"IA3IRQ8", 0x0B68, 12, 0x000},\r\r
615 {"IA3IRQ9", 0x0B69, 12, 0x000},\r\r
616 {"IA3IRQA", 0x0B6A, 12, 0x000},\r\r
617 {"IA3IRQB", 0x0B6B, 12, 0x000},\r\r
618 {"IA3IRQC", 0x0B6C, 12, 0x000},\r\r
619 {"IRQSW3", 0x0B6D, 13, 0x1FFF},\r\r
620 {"IRQHW3", 0x0B6E, 13, 0x0000},\r\r
621 {"IRQHL3", 0x0B6F, 13, 0x0000},\r\r
622 // Global Counter/Timer\r\r
623 {"CTGDINI", 0x0B80, 32, 0x00000000},\r\r
624 {"CTGCTRL", 0x0B81, 12, 0xE3F},\r\r
625 // CPU constants\r\r
626 {"C08CPU0", 0x0C00, 32, 0x00000000},\r\r
627 {"C09CPU0", 0x0C01, 32, 0x00000000},\r\r
628 {"C10CPU0", 0x0C02, 32, 0x00000000},\r\r
629 {"C11CPU0", 0x0C03, 32, 0x00000000},\r\r
630 {"C12CPUA", 0x0C04, 32, 0x00000000},\r\r
631 {"C13CPUA", 0x0C05, 32, 0x00000000},\r\r
632 {"C14CPUA", 0x0C06, 32, 0x00000000},\r\r
633 {"C15CPUA", 0x0C07, 32, 0x00000000},\r\r
634 {"C08CPU1", 0x0C08, 32, 0x00000000},\r\r
635 {"C09CPU1", 0x0C09, 32, 0x00000000},\r\r
636 {"C10CPU1", 0x0C0A, 32, 0x00000000},\r\r
637 {"C11CPU1", 0x0C0B, 32, 0x00000000},\r\r
638 {"C08CPU2", 0x0C10, 32, 0x00000000},\r\r
639 {"C09CPU2", 0x0C11, 32, 0x00000000},\r\r
640 {"C10CPU2", 0x0C12, 32, 0x00000000},\r\r
641 {"C11CPU2", 0x0C13, 32, 0x00000000},\r\r
642 {"C08CPU3", 0x0C18, 32, 0x00000000},\r\r
643 {"C09CPU3", 0x0C19, 32, 0x00000000},\r\r
644 {"C10CPU3", 0x0C1A, 32, 0x00000000},\r\r
645 {"C11CPU3", 0x0C1B, 32, 0x00000000},\r\r
646 // NI interface\r\r
647 {"NMOD", 0x0D40, 6, 0x08},\r\r
648 {"NDLY", 0x0D41, 30, 0x24924924},\r\r
649 {"NED", 0x0D42, 16, 0xA240},\r\r
650 {"NTRO", 0x0D43, 18, 0x3FFFC},\r\r
651 {"NRRO", 0x0D44, 18, 0x3FFFC},\r\r
652\r\r
653 {"NES", 0x0D45, 32, 0x00000000},\r\r
654 {"NTP", 0x0D46, 32, 0x0000FFFF},\r\r
655 {"NBND", 0x0D47, 16, 0x6020},\r\r
656 {"NP0", 0x0D48, 11, 0x44C},\r\r
657 {"NP1", 0x0D49, 11, 0x44C},\r\r
658 {"NP2", 0x0D4A, 11, 0x44C},\r\r
659 {"NP3", 0x0D4B, 11, 0x44C},\r\r
660 {"NCUT", 0x0D4C, 32, 0xFFFFFFFF},\r\r
661 // Filter and Preprocessor\r\r
662 {"TPPT0", 0x3000, 7, 0x01},\r\r
663 {"TPFS", 0x3001, 7, 0x05},\r\r
664 {"TPFE", 0x3002, 7, 0x14},\r\r
665 {"TPPGR", 0x3003, 7, 0x15},\r\r
666 {"TPPAE", 0x3004, 7, 0x1E},\r\r
667 {"TPQS0", 0x3005, 7, 0x00},\r\r
668 {"TPQE0", 0x3006, 7, 0x0A},\r\r
669 {"TPQS1", 0x3007, 7, 0x0B},\r\r
670 {"TPQE1", 0x3008, 7, 0x14},\r\r
671 {"EBD", 0x3009, 3, 0x0},\r\r
672 {"EBAQA", 0x300A, 7, 0x00},\r\r
673 {"EBSIA", 0x300B, 7, 0x20},\r\r
674 {"EBSF", 0x300C, 1, 0x1},\r\r
675 {"EBSIM", 0x300D, 1, 0x1},\r\r
676 {"EBPP", 0x300E, 1, 0x1},\r\r
677 {"EBPC", 0x300F, 1, 0x1},\r\r
678\r\r
679 {"EBIS", 0x3014, 10, 0x005},\r\r
680 {"EBIT", 0x3015, 12, 0x028},\r\r
681 {"EBIL", 0x3016, 8, 0xF0},\r\r
682 {"EBIN", 0x3017, 1, 0x1},\r\r
683 {"FLBY", 0x3018, 1, 0x0},\r\r
684 {"FPBY", 0x3019, 1, 0x0},\r\r
685 {"FGBY", 0x301A, 1, 0x0},\r\r
686 {"FTBY", 0x301B, 1, 0x0},\r\r
687 {"FCBY", 0x301C, 1, 0x0},\r\r
688 {"FPTC", 0x3020, 2, 0x3},\r\r
689 {"FPNP", 0x3021, 9, 0x078},\r\r
690 {"FPCL", 0x3022, 1, 0x1},\r\r
691 {"FGTA", 0x3028, 12, 0x014},\r\r
692 {"FGTB", 0x3029, 12, 0x80C},\r\r
693 {"FGCL", 0x302A, 1, 0x1},\r\r
694 {"FTAL", 0x3030, 10, 0x0F6},\r\r
695 {"FTLL", 0x3031, 9, 0x11D},\r\r
696 {"FTLS", 0x3032, 9, 0x0D3},\r\r
697 {"FCW1", 0x3038, 8, 0x1E},\r\r
698 {"FCW2", 0x3039, 8, 0xD4},\r\r
699 {"FCW3", 0x303A, 8, 0xE6},\r\r
700 {"FCW4", 0x303B, 8, 0x4A},\r\r
701 {"FCW5", 0x303C, 8, 0xEF},\r\r
702 {"TPFP", 0x3040, 9, 0x037},\r\r
703 {"TPHT", 0x3041, 14, 0x00A0},\r\r
704\r\r
705 {"TPVT", 0x3042, 6, 0x00},\r\r
706 {"TPVBY", 0x3043, 1, 0x0},\r\r
707 {"TPCT", 0x3044, 5, 0x08},\r\r
708 {"TPCL", 0x3045, 5, 0x01},\r\r
709 {"TPCBY", 0x3046, 1, 0x1},\r\r
710 {"TPD", 0x3047, 4, 0xF},\r\r
711 {"TPCI0", 0x3048, 5, 0x00},\r\r
712 {"TPCI1", 0x3049, 5, 0x00},\r\r
713 {"TPCI2", 0x304A, 5, 0x00},\r\r
714 {"TPCI3", 0x304B, 5, 0x00},\r\r
715\r\r
716 {"ADCMSK", 0x3050, 21, 0x1FFFFF},\r\r
717 {"ADCINB", 0x3051, 2, 0x2},\r\r
718 {"ADCDAC", 0x3052, 5, 0x10},\r\r
719 {"ADCPAR", 0x3053, 18, 0x195EF},\r\r
720 {"ADCTST", 0x3054, 2, 0x0},\r\r
721 {"SADCAZ", 0x3055, 1, 0x1},\r\r
722\r\r
723 {"FGF0", 0x3080, 9, 0x000},\r\r
724 {"FGF1", 0x3081, 9, 0x000},\r\r
725 {"FGF2", 0x3082, 9, 0x000},\r\r
726 {"FGF3", 0x3083, 9, 0x000},\r\r
727 {"FGF4", 0x3084, 9, 0x000},\r\r
728 {"FGF5", 0x3085, 9, 0x000},\r\r
729 {"FGF6", 0x3086, 9, 0x000},\r\r
730 {"FGF7", 0x3087, 9, 0x000},\r\r
731 {"FGF8", 0x3088, 9, 0x000},\r\r
732 {"FGF9", 0x3089, 9, 0x000},\r\r
733 {"FGF10", 0x308A, 9, 0x000},\r\r
734 {"FGF11", 0x308B, 9, 0x000},\r\r
735 {"FGF12", 0x308C, 9, 0x000},\r\r
736 {"FGF13", 0x308D, 9, 0x000},\r\r
737 {"FGF14", 0x308E, 9, 0x000},\r\r
738 {"FGF15", 0x308F, 9, 0x000},\r\r
739 {"FGF16", 0x3090, 9, 0x000},\r\r
740 {"FGF17", 0x3091, 9, 0x000},\r\r
741 {"FGF18", 0x3092, 9, 0x000},\r\r
742 {"FGF19", 0x3093, 9, 0x000},\r\r
743 {"FGF20", 0x3094, 9, 0x000},\r\r
744\r\r
745 {"FGA0", 0x30A0, 6, 0x00},\r\r
746 {"FGA1", 0x30A1, 6, 0x00},\r\r
747 {"FGA2", 0x30A2, 6, 0x00},\r\r
748 {"FGA3", 0x30A3, 6, 0x00},\r\r
749 {"FGA4", 0x30A4, 6, 0x00},\r\r
750 {"FGA5", 0x30A5, 6, 0x00},\r\r
751 {"FGA6", 0x30A6, 6, 0x00},\r\r
752 {"FGA7", 0x30A7, 6, 0x00},\r\r
753 {"FGA8", 0x30A8, 6, 0x00},\r\r
754 {"FGA9", 0x30A9, 6, 0x00},\r\r
755 {"FGA10", 0x30AA, 6, 0x00},\r\r
756 {"FGA11", 0x30AB, 6, 0x00},\r\r
757 {"FGA12", 0x30AC, 6, 0x00},\r\r
758 {"FGA13", 0x30AD, 6, 0x00},\r\r
759 {"FGA14", 0x30AE, 6, 0x00},\r\r
760 {"FGA15", 0x30AF, 6, 0x00},\r\r
761 {"FGA16", 0x30B0, 6, 0x00},\r\r
762 {"FGA17", 0x30B1, 6, 0x00},\r\r
763 {"FGA18", 0x30B2, 6, 0x00},\r\r
764 {"FGA19", 0x30B3, 6, 0x00},\r\r
765 {"FGA20", 0x30B4, 6, 0x00},\r\r
766 // non-linearity table, 64 x 6 bits\r\r
767 {"FLL00", 0x3100, 6, 0x00},\r\r
768 {"FLL01", 0x3101, 6, 0x00},\r\r
769 {"FLL02", 0x3102, 6, 0x00},\r\r
770 {"FLL03", 0x3103, 6, 0x00},\r\r
771 {"FLL04", 0x3104, 6, 0x00},\r\r
772 {"FLL05", 0x3105, 6, 0x00},\r\r
773 {"FLL06", 0x3106, 6, 0x00},\r\r
774 {"FLL07", 0x3107, 6, 0x00},\r\r
775 {"FLL08", 0x3108, 6, 0x00},\r\r
776 {"FLL09", 0x3109, 6, 0x00},\r\r
777 {"FLL0A", 0x310A, 6, 0x00},\r\r
778 {"FLL0B", 0x310B, 6, 0x00},\r\r
779 {"FLL0C", 0x310C, 6, 0x00},\r\r
780 {"FLL0D", 0x310D, 6, 0x00},\r\r
781 {"FLL0E", 0x310E, 6, 0x00},\r\r
782 {"FLL0F", 0x310F, 6, 0x00},\r\r
783 {"FLL10", 0x3110, 6, 0x00},\r\r
784 {"FLL11", 0x3111, 6, 0x00},\r\r
785 {"FLL12", 0x3112, 6, 0x00},\r\r
786 {"FLL13", 0x3113, 6, 0x00},\r\r
787 {"FLL14", 0x3114, 6, 0x00},\r\r
788 {"FLL15", 0x3115, 6, 0x00},\r\r
789 {"FLL16", 0x3116, 6, 0x00},\r\r
790 {"FLL17", 0x3117, 6, 0x00},\r\r
791 {"FLL18", 0x3118, 6, 0x00},\r\r
792 {"FLL19", 0x3119, 6, 0x00},\r\r
793 {"FLL1A", 0x311A, 6, 0x00},\r\r
794 {"FLL1B", 0x311B, 6, 0x00},\r\r
795 {"FLL1C", 0x311C, 6, 0x00},\r\r
796 {"FLL1D", 0x311D, 6, 0x00},\r\r
797 {"FLL1E", 0x311E, 6, 0x00},\r\r
798 {"FLL1F", 0x311F, 6, 0x00},\r\r
799 {"FLL20", 0x3120, 6, 0x00},\r\r
800 {"FLL21", 0x3121, 6, 0x00},\r\r
801 {"FLL22", 0x3122, 6, 0x00},\r\r
802 {"FLL23", 0x3123, 6, 0x00},\r\r
803 {"FLL24", 0x3124, 6, 0x00},\r\r
804 {"FLL25", 0x3125, 6, 0x00},\r\r
805 {"FLL26", 0x3126, 6, 0x00},\r\r
806 {"FLL27", 0x3127, 6, 0x00},\r\r
807 {"FLL28", 0x3128, 6, 0x00},\r\r
808 {"FLL29", 0x3129, 6, 0x00},\r\r
809 {"FLL2A", 0x312A, 6, 0x00},\r\r
810 {"FLL2B", 0x312B, 6, 0x00},\r\r
811 {"FLL2C", 0x312C, 6, 0x00},\r\r
812 {"FLL2D", 0x312D, 6, 0x00},\r\r
813 {"FLL2E", 0x312E, 6, 0x00},\r\r
814 {"FLL2F", 0x312F, 6, 0x00},\r\r
815 {"FLL30", 0x3130, 6, 0x00},\r\r
816 {"FLL31", 0x3131, 6, 0x00},\r\r
817 {"FLL32", 0x3132, 6, 0x00},\r\r
818 {"FLL33", 0x3133, 6, 0x00},\r\r
819 {"FLL34", 0x3134, 6, 0x00},\r\r
820 {"FLL35", 0x3135, 6, 0x00},\r\r
821 {"FLL36", 0x3136, 6, 0x00},\r\r
822 {"FLL37", 0x3137, 6, 0x00},\r\r
823 {"FLL38", 0x3138, 6, 0x00},\r\r
824 {"FLL39", 0x3139, 6, 0x00},\r\r
825 {"FLL3A", 0x313A, 6, 0x00},\r\r
826 {"FLL3B", 0x313B, 6, 0x00},\r\r
827 {"FLL3C", 0x313C, 6, 0x00},\r\r
828 {"FLL3D", 0x313D, 6, 0x00},\r\r
829 {"FLL3E", 0x313E, 6, 0x00},\r\r
830 {"FLL3F", 0x313F, 6, 0x00},\r\r
831 // end of non-lin table\r\r
832 {"PASADEL", 0x3158, 8, 0xFF},\r\r
833 {"PASAPHA", 0x3159, 6, 0x3F},\r\r
834 {"PASAPRA", 0x315A, 6, 0x0F},\r\r
835 {"PASADAC", 0x315B, 8, 0x80},\r\r
836 {"PASACHM", 0x315C, 19, 0x7FFFF},\r\r
837 {"PASASTL", 0x315D, 8, 0xFF},\r\r
838 {"PASAPR1", 0x315E, 1, 0x0},\r\r
839 {"PASAPR0", 0x315F, 1, 0x0},\r\r
840 {"SADCTRG", 0x3161, 1, 0x0},\r\r
841 {"SADCRUN", 0x3162, 1, 0x0},\r\r
842 {"SADCPWR", 0x3163, 3, 0x7},\r\r
843 {"L0TSIM", 0x3165, 14, 0x0050},\r\r
844 {"SADCEC", 0x3166, 7, 0x00},\r\r
845 {"SADCMC", 0x3170, 8, 0xC0},\r\r
846 {"SADCOC", 0x3171, 8, 0x19},\r\r
847 {"SADCGTB", 0x3172, 32, 0x37737700},\r\r
848 {"SEBDEN", 0x3178, 3, 0x0},\r\r
849 {"SEBDOU", 0x3179, 3, 0x0},\r\r
850 // pos table, 128 x 5 bits\r\r
851 {"TPL00", 0x3180, 5, 0x00},\r\r
852 {"TPL01", 0x3181, 5, 0x00},\r\r
853 {"TPL02", 0x3182, 5, 0x00},\r\r
854 {"TPL03", 0x3183, 5, 0x00},\r\r
855 {"TPL04", 0x3184, 5, 0x00},\r\r
856 {"TPL05", 0x3185, 5, 0x00},\r\r
857 {"TPL06", 0x3186, 5, 0x00},\r\r
858 {"TPL07", 0x3187, 5, 0x00},\r\r
859 {"TPL08", 0x3188, 5, 0x00},\r\r
860 {"TPL09", 0x3189, 5, 0x00},\r\r
861 {"TPL0A", 0x318A, 5, 0x00},\r\r
862 {"TPL0B", 0x318B, 5, 0x00},\r\r
863 {"TPL0C", 0x318C, 5, 0x00},\r\r
864 {"TPL0D", 0x318D, 5, 0x00},\r\r
865 {"TPL0E", 0x318E, 5, 0x00},\r\r
866 {"TPL0F", 0x318F, 5, 0x00},\r\r
867 {"TPL10", 0x3190, 5, 0x00},\r\r
868 {"TPL11", 0x3191, 5, 0x00},\r\r
869 {"TPL12", 0x3192, 5, 0x00},\r\r
870 {"TPL13", 0x3193, 5, 0x00},\r\r
871 {"TPL14", 0x3194, 5, 0x00},\r\r
872 {"TPL15", 0x3195, 5, 0x00},\r\r
873 {"TPL16", 0x3196, 5, 0x00},\r\r
874 {"TPL17", 0x3197, 5, 0x00},\r\r
875 {"TPL18", 0x3198, 5, 0x00},\r\r
876 {"TPL19", 0x3199, 5, 0x00},\r\r
877 {"TPL1A", 0x319A, 5, 0x00},\r\r
878 {"TPL1B", 0x319B, 5, 0x00},\r\r
879 {"TPL1C", 0x319C, 5, 0x00},\r\r
880 {"TPL1D", 0x319D, 5, 0x00},\r\r
881 {"TPL1E", 0x319E, 5, 0x00},\r\r
882 {"TPL1F", 0x319F, 5, 0x00},\r\r
883 {"TPL20", 0x31A0, 5, 0x00},\r\r
884 {"TPL21", 0x31A1, 5, 0x00},\r\r
885 {"TPL22", 0x31A2, 5, 0x00},\r\r
886 {"TPL23", 0x31A3, 5, 0x00},\r\r
887 {"TPL24", 0x31A4, 5, 0x00},\r\r
888 {"TPL25", 0x31A5, 5, 0x00},\r\r
889 {"TPL26", 0x31A6, 5, 0x00},\r\r
890 {"TPL27", 0x31A7, 5, 0x00},\r\r
891 {"TPL28", 0x31A8, 5, 0x00},\r\r
892 {"TPL29", 0x31A9, 5, 0x00},\r\r
893 {"TPL2A", 0x31AA, 5, 0x00},\r\r
894 {"TPL2B", 0x31AB, 5, 0x00},\r\r
895 {"TPL2C", 0x31AC, 5, 0x00},\r\r
896 {"TPL2D", 0x31AD, 5, 0x00},\r\r
897 {"TPL2E", 0x31AE, 5, 0x00},\r\r
898 {"TPL2F", 0x31AF, 5, 0x00},\r\r
899 {"TPL30", 0x31B0, 5, 0x00},\r\r
900 {"TPL31", 0x31B1, 5, 0x00},\r\r
901 {"TPL32", 0x31B2, 5, 0x00},\r\r
902 {"TPL33", 0x31B3, 5, 0x00},\r\r
903 {"TPL34", 0x31B4, 5, 0x00},\r\r
904 {"TPL35", 0x31B5, 5, 0x00},\r\r
905 {"TPL36", 0x31B6, 5, 0x00},\r\r
906 {"TPL37", 0x31B7, 5, 0x00},\r\r
907 {"TPL38", 0x31B8, 5, 0x00},\r\r
908 {"TPL39", 0x31B9, 5, 0x00},\r\r
909 {"TPL3A", 0x31BA, 5, 0x00},\r\r
910 {"TPL3B", 0x31BB, 5, 0x00},\r\r
911 {"TPL3C", 0x31BC, 5, 0x00},\r\r
912 {"TPL3D", 0x31BD, 5, 0x00},\r\r
913 {"TPL3E", 0x31BE, 5, 0x00},\r\r
914 {"TPL3F", 0x31BF, 5, 0x00},\r\r
915 {"TPL40", 0x31C0, 5, 0x00},\r\r
916 {"TPL41", 0x31C1, 5, 0x00},\r\r
917 {"TPL42", 0x31C2, 5, 0x00},\r\r
918 {"TPL43", 0x31C3, 5, 0x00},\r\r
919 {"TPL44", 0x31C4, 5, 0x00},\r\r
920 {"TPL45", 0x31C5, 5, 0x00},\r\r
921 {"TPL46", 0x31C6, 5, 0x00},\r\r
922 {"TPL47", 0x31C7, 5, 0x00},\r\r
923 {"TPL48", 0x31C8, 5, 0x00},\r\r
924 {"TPL49", 0x31C9, 5, 0x00},\r\r
925 {"TPL4A", 0x31CA, 5, 0x00},\r\r
926 {"TPL4B", 0x31CB, 5, 0x00},\r\r
927 {"TPL4C", 0x31CC, 5, 0x00},\r\r
928 {"TPL4D", 0x31CD, 5, 0x00},\r\r
929 {"TPL4E", 0x31CE, 5, 0x00},\r\r
930 {"TPL4F", 0x31CF, 5, 0x00},\r\r
931 {"TPL50", 0x31D0, 5, 0x00},\r\r
932 {"TPL51", 0x31D1, 5, 0x00},\r\r
933 {"TPL52", 0x31D2, 5, 0x00},\r\r
934 {"TPL53", 0x31D3, 5, 0x00},\r\r
935 {"TPL54", 0x31D4, 5, 0x00},\r\r
936 {"TPL55", 0x31D5, 5, 0x00},\r\r
937 {"TPL56", 0x31D6, 5, 0x00},\r\r
938 {"TPL57", 0x31D7, 5, 0x00},\r\r
939 {"TPL58", 0x31D8, 5, 0x00},\r\r
940 {"TPL59", 0x31D9, 5, 0x00},\r\r
941 {"TPL5A", 0x31DA, 5, 0x00},\r\r
942 {"TPL5B", 0x31DB, 5, 0x00},\r\r
943 {"TPL5C", 0x31DC, 5, 0x00},\r\r
944 {"TPL5D", 0x31DD, 5, 0x00},\r\r
945 {"TPL5E", 0x31DE, 5, 0x00},\r\r
946 {"TPL5F", 0x31DF, 5, 0x00},\r\r
947 {"TPL60", 0x31E0, 5, 0x00},\r\r
948 {"TPL61", 0x31E1, 5, 0x00},\r\r
949 {"TPL62", 0x31E2, 5, 0x00},\r\r
950 {"TPL63", 0x31E3, 5, 0x00},\r\r
951 {"TPL64", 0x31E4, 5, 0x00},\r\r
952 {"TPL65", 0x31E5, 5, 0x00},\r\r
953 {"TPL66", 0x31E6, 5, 0x00},\r\r
954 {"TPL67", 0x31E7, 5, 0x00},\r\r
955 {"TPL68", 0x31E8, 5, 0x00},\r\r
956 {"TPL69", 0x31E9, 5, 0x00},\r\r
957 {"TPL6A", 0x31EA, 5, 0x00},\r\r
958 {"TPL6B", 0x31EB, 5, 0x00},\r\r
959 {"TPL6C", 0x31EC, 5, 0x00},\r\r
960 {"TPL6D", 0x31ED, 5, 0x00},\r\r
961 {"TPL6E", 0x31EE, 5, 0x00},\r\r
962 {"TPL6F", 0x31EF, 5, 0x00},\r\r
963 {"TPL70", 0x31F0, 5, 0x00},\r\r
964 {"TPL71", 0x31F1, 5, 0x00},\r\r
965 {"TPL72", 0x31F2, 5, 0x00},\r\r
966 {"TPL73", 0x31F3, 5, 0x00},\r\r
967 {"TPL74", 0x31F4, 5, 0x00},\r\r
968 {"TPL75", 0x31F5, 5, 0x00},\r\r
969 {"TPL76", 0x31F6, 5, 0x00},\r\r
970 {"TPL77", 0x31F7, 5, 0x00},\r\r
971 {"TPL78", 0x31F8, 5, 0x00},\r\r
972 {"TPL79", 0x31F9, 5, 0x00},\r\r
973 {"TPL7A", 0x31FA, 5, 0x00},\r\r
974 {"TPL7B", 0x31FB, 5, 0x00},\r\r
975 {"TPL7C", 0x31FC, 5, 0x00},\r\r
976 {"TPL7D", 0x31FD, 5, 0x00},\r\r
977 {"TPL7E", 0x31FE, 5, 0x00},\r\r
978 {"TPL7F", 0x31FF, 5, 0x00},\r\r
979 // end of pos table\r\r
980 {"MEMRW", 0xD000, 7, 0x79},\r\r
981 {"MEMCOR", 0xD001, 9, 0x000},\r\r
982 {"DMDELA", 0xD002, 4, 0x8},\r\r
983 {"DMDELS", 0xD003, 4, 0x8}\r\r
984 };\r\r
985\r\r
986 const CmdRegs kCmdReg[NCMD] = {\r\r
987 // Name Address\r\r
988 {"SMCMD" , 0x0A04},\r\r
989 {"SMOFFON" , 0x0A05},\r\r
990 {"SMON" , 0x0A06},\r\r
991 {"SMOFF" , 0x0A07},\r\r
992 {"CPU0SS" , 0x0A21},\r\r
993 {"CPU1SS" , 0x0A23},\r\r
994 {"CPU2SS" , 0x0A25},\r\r
995 {"CPU3SS" , 0x0A27},\r\r
996 {"NICLKSS" , 0x0A29},\r\r
997 {"FILCLKSS", 0x0A2B},\r\r
998 {"PRECLKSS", 0x0A2D},\r\r
999 {"ADCENSS" , 0x0A2F},\r\r
1000 {"NIODESS" , 0x0A31},\r\r
1001 {"NIOCESS" , 0x0A33},\r\r
1002 {"NIIDESS" , 0x0A35},\r\r
1003 {"NIICESS" , 0x0A37}\r\r
1004 };\r\r
1005\r\r
1006 const CmdRegs kRoReg[NRO] = {\r\r
1007 // NI\r\r
1008 {"NCTRL" , 0x0DC0},\r\r
1009 {"NFE" , 0x0DC1},\r\r
1010 {"NFSM" , 0x0DC2},\r\r
1011 // event buffer parity violation counters\r\r
1012 {"EBP0" , 0x3010},\r\r
1013 {"EBP1" , 0x3011},\r\r
1014 {"EBP2" , 0x3012},\r\r
1015 {"EBP3" , 0x3013},\r\r
1016 // slow ADC\r\r
1017 {"SADCC0" , 0x3168},\r\r
1018 {"SADCC1" , 0x3169},\r\r
1019 {"SADCC2" , 0x316A},\r\r
1020 {"SADCC3" , 0x316B},\r\r
1021 {"SADCC4" , 0x316C},\r\r
1022 {"SADCC5" , 0x316D},\r\r
1023 {"SADCC6" , 0x316E},\r\r
1024 {"SADCC7" , 0x316F},\r\r
1025 // hamming counters\r\r
1026 {"HCNTI0" , 0xD010},\r\r
1027 {"HCNTI1" , 0xD011},\r\r
1028 {"HCNTI2" , 0xD012},\r\r
1029 {"HCNTI3" , 0xD013},\r\r
1030 {"HCNTD0" , 0xD014},\r\r
1031 {"HCNTD1" , 0xD015},\r\r
1032 {"HCNTD2" , 0xD016},\r\r
1033 {"HCNTD3" , 0xD017},\r\r
1034\r\r
1035 {"CHIPID" , 0x3160},\r\r
1036\r\r
1037 {"SEBDIN" , 0x317A}\r\r
1038 };\r\r
1039\r\r
1040\r\r
1041 for (Int_t i = 0; i < NREGS; i++) {\r\r
1042 fTrapReg[i] = kTrapReg[i];\r\r
1043 }\r\r
1044 for (Int_t i = 0; i < NCMD; i++) {\r\r
1045 fCmdReg[i] = kCmdReg[i];\r\r
1046 }\r\r
1047 for (Int_t i = 0; i < NRO; i++) {\r\r
1048 fRoReg[i] = kRoReg[i];\r\r
1049 }\r\r
1050\r\r
1051 return kTRUE;\r\r
1052}\r\r