Added SPD outlier trigger bit

[u/mrichter/AliRoot.git] / ALIROOT / CMakebinaliroot.pkg

diff --git a/ALIROOT/CMakebinaliroot.pkg b/ALIROOT/CMakebinaliroot.pkg
index 555f0fe9f6e9642f0098fdcff00960167b8524ec..15eaee92fe4cd82678793d57c7a54cd6b8a2358f 100644 (file)
--- a/ALIROOT/CMakebinaliroot.pkg
+++ b/ALIROOT/CMakebinaliroot.pkg
@@ -34,7 +34,7 @@ set ( ELIBSDIR )
 set ( ELIBS  MUONevaluation    MUONmapping MUONshuttle MUONgraphics MUONsim MUONrec MUONgeometry MUONcalib MUONbase MUONraw MUONtrigger MUONcore TPCbase TPCsim TPCrec TPCutil  ITSbase ITSsim ITSrec PMDbase PMDsim PMDrec TRDbase TRDsim TRDrec FMDbase FMDsim FMDrec TOFbase TOFrec TOFsim PHOSUtils PHOSbase PHOSsim PHOSrec ADbase ADsim ADrec ACORDEbase ACORDEsim ACORDErec HMPIDbase HMPIDrec HMPIDsim ZDCbase ZDCsim ZDCrec VZERObase VZEROsim VZEROrec MFTbase MFTsim MFTrec EMCALUtils EMCALbase EMCALsim EMCALrec EMCALraw BCM STRUCT T0base T0sim T0rec FASTSIM microcern HLTbase HLTshuttle TRIGGERbase STEER STAT CDB AOD  STEERBase ESD ANALYSIS RAWDatasim RAWDatarec RAWDatabase)
 
 if(PYTHIA6)
-  list(APPEND ELIBS EVGEN)
+  list(APPEND ELIBS EVGEN HepMC HepMCParser)
 endif(PYTHIA6)
 
 if( ALICE_TARGET STREQUAL "macosx")
@@ -67,7 +67,7 @@ set (ARLIBS ${AFILES})
 list(APPEND SRCS ${GFILES})
 set ( SHLIBS  ${BINLIBDIRS} EVGEN -lEGPythia6 Pythia6 -lpythia6 AliPythia6 lhapdf THijing hijing THerwig herwig TPHIC FASTSIM microcern)
 
-set ( EINCLUDE STEER/STEER )
+set ( EINCLUDE STEER/STEER ${CMAKE_INCLUDE_EXPORT_DIRECTORY}/FromTemplate/)
 #
 # EOF
 #