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36dc3337 1/**************************************************************************
2 * Copyright(c) 1998-1999, ALICE Experiment at CERN, All rights reserved. *
3 * *
4 * Author: The ALICE Off-line Project. *
5 * Contributors are mentioned in the code where appropriate. *
6 * *
7 * Permission to use, copy, modify and distribute this software and its *
8 * documentation strictly for non-commercial purposes is hereby granted *
9 * without fee, provided that the above copyright notice appears in all *
10 * copies and that both the copyright notice and this permission notice *
11 * appear in the supporting documentation. The authors make no claims *
12 * about the suitability of this software for any purpose. It is *
13 * provided "as is" without express or implied warranty. *
14 **************************************************************************/
15
16////////////////////////////////////////////////////////////////////////////
17// //
18// TRAP config //
19// //
20// Author: J. Klein (Jochen.Klein@cern.ch) //
21// //
22////////////////////////////////////////////////////////////////////////////
23
ce4786b9 24#include "AliLog.h"
25
26#include "AliTRDgeometry.h"
27#include "AliTRDfeeParam.h"
28#include "AliTRDtrapConfig.h"
29
30#include <fstream>
31#include <iostream>
32#include <iomanip>
33
34ClassImp(AliTRDtrapConfig)
35
36AliTRDtrapConfig* AliTRDtrapConfig::fgInstance = 0x0;
37const Int_t AliTRDtrapConfig::fgkMaxMcm = AliTRDfeeParam::GetNmcmRob() + 2;
38const Int_t AliTRDtrapConfig::fgkDmemStartAddress = 0xc000;
39
40AliTRDtrapConfig::AliTRDtrapConfig() :
41 TObject()
42{
43 // default constructor, initializing array of TRAP registers
44
45 // Name Address Nbits Reset Value
46 fRegs[kSML0] = SimpleReg_t("SML0", 0x0A00, 15, 0x4050 ); // Global state machine
47 fRegs[kSML1] = SimpleReg_t("SML1", 0x0A01, 15, 0x4200 );
48 fRegs[kSML2] = SimpleReg_t("SML2", 0x0A02, 15, 0x4384 );
49 fRegs[kSMMODE] = SimpleReg_t("SMMODE", 0x0A03, 16, 0xF0E2 );
50 fRegs[kNITM0] = SimpleReg_t("NITM0", 0x0A08, 14, 0x3FFF );
51 fRegs[kNITM1] = SimpleReg_t("NITM1", 0x0A09, 14, 0x3FFF );
52 fRegs[kNITM2] = SimpleReg_t("NITM2", 0x0A0A, 14, 0x3FFF );
53 fRegs[kNIP4D] = SimpleReg_t("NIP4D", 0x0A0B, 7, 0x7F );
54 fRegs[kCPU0CLK] = SimpleReg_t("CPU0CLK", 0x0A20, 5, 0x07 );
55 fRegs[kCPU1CLK] = SimpleReg_t("CPU1CLK", 0x0A22, 5, 0x07 );
56 fRegs[kCPU2CLK] = SimpleReg_t("CPU2CLK", 0x0A24, 5, 0x07 );
57 fRegs[kCPU3CLK] = SimpleReg_t("CPU3CLK", 0x0A26, 5, 0x07 );
58 fRegs[kNICLK] = SimpleReg_t("NICLK", 0x0A28, 5, 0x07 );
59 fRegs[kFILCLK] = SimpleReg_t("FILCLK", 0x0A2A, 5, 0x07 );
60 fRegs[kPRECLK] = SimpleReg_t("PRECLK", 0x0A2C, 5, 0x07 );
61 fRegs[kADCEN] = SimpleReg_t("ADCEN", 0x0A2E, 5, 0x07 );
62 fRegs[kNIODE] = SimpleReg_t("NIODE", 0x0A30, 5, 0x07 );
63 fRegs[kNIOCE] = SimpleReg_t("NIOCE", 0x0A32, 6, 0x21 ); // bit 5 is status bit (read-only)!
64 fRegs[kNIIDE] = SimpleReg_t("NIIDE", 0x0A34, 5, 0x07 );
65 fRegs[kNIICE] = SimpleReg_t("NIICE", 0x0A36, 5, 0x07 );
66 fRegs[kARBTIM] = SimpleReg_t("ARBTIM", 0x0A3F, 4, 0x0 ); // Arbiter
67 fRegs[kIA0IRQ0] = SimpleReg_t("IA0IRQ0", 0x0B00, 12, 0x000 ); // IVT of CPU0
68 fRegs[kIA0IRQ1] = SimpleReg_t("IA0IRQ1", 0x0B01, 12, 0x000 );
69 fRegs[kIA0IRQ2] = SimpleReg_t("IA0IRQ2", 0x0B02, 12, 0x000 );
70 fRegs[kIA0IRQ3] = SimpleReg_t("IA0IRQ3", 0x0B03, 12, 0x000 );
71 fRegs[kIA0IRQ4] = SimpleReg_t("IA0IRQ4", 0x0B04, 12, 0x000 );
72 fRegs[kIA0IRQ5] = SimpleReg_t("IA0IRQ5", 0x0B05, 12, 0x000 );
73 fRegs[kIA0IRQ6] = SimpleReg_t("IA0IRQ6", 0x0B06, 12, 0x000 );
74 fRegs[kIA0IRQ7] = SimpleReg_t("IA0IRQ7", 0x0B07, 12, 0x000 );
75 fRegs[kIA0IRQ8] = SimpleReg_t("IA0IRQ8", 0x0B08, 12, 0x000 );
76 fRegs[kIA0IRQ9] = SimpleReg_t("IA0IRQ9", 0x0B09, 12, 0x000 );
77 fRegs[kIA0IRQA] = SimpleReg_t("IA0IRQA", 0x0B0A, 12, 0x000 );
78 fRegs[kIA0IRQB] = SimpleReg_t("IA0IRQB", 0x0B0B, 12, 0x000 );
79 fRegs[kIA0IRQC] = SimpleReg_t("IA0IRQC", 0x0B0C, 12, 0x000 );
80 fRegs[kIRQSW0] = SimpleReg_t("IRQSW0", 0x0B0D, 13, 0x1FFF );
81 fRegs[kIRQHW0] = SimpleReg_t("IRQHW0", 0x0B0E, 13, 0x0000 );
82 fRegs[kIRQHL0] = SimpleReg_t("IRQHL0", 0x0B0F, 13, 0x0000 );
83 fRegs[kIA1IRQ0] = SimpleReg_t("IA1IRQ0", 0x0B20, 12, 0x000 ); // IVT of CPU1
84 fRegs[kIA1IRQ1] = SimpleReg_t("IA1IRQ1", 0x0B21, 12, 0x000 );
85 fRegs[kIA1IRQ2] = SimpleReg_t("IA1IRQ2", 0x0B22, 12, 0x000 );
86 fRegs[kIA1IRQ3] = SimpleReg_t("IA1IRQ3", 0x0B23, 12, 0x000 );
87 fRegs[kIA1IRQ4] = SimpleReg_t("IA1IRQ4", 0x0B24, 12, 0x000 );
88 fRegs[kIA1IRQ5] = SimpleReg_t("IA1IRQ5", 0x0B25, 12, 0x000 );
89 fRegs[kIA1IRQ6] = SimpleReg_t("IA1IRQ6", 0x0B26, 12, 0x000 );
90 fRegs[kIA1IRQ7] = SimpleReg_t("IA1IRQ7", 0x0B27, 12, 0x000 );
91 fRegs[kIA1IRQ8] = SimpleReg_t("IA1IRQ8", 0x0B28, 12, 0x000 );
92 fRegs[kIA1IRQ9] = SimpleReg_t("IA1IRQ9", 0x0B29, 12, 0x000 );
93 fRegs[kIA1IRQA] = SimpleReg_t("IA1IRQA", 0x0B2A, 12, 0x000 );
94 fRegs[kIA1IRQB] = SimpleReg_t("IA1IRQB", 0x0B2B, 12, 0x000 );
95 fRegs[kIA1IRQC] = SimpleReg_t("IA1IRQC", 0x0B2C, 12, 0x000 );
96 fRegs[kIRQSW1] = SimpleReg_t("IRQSW1", 0x0B2D, 13, 0x1FFF );
97 fRegs[kIRQHW1] = SimpleReg_t("IRQHW1", 0x0B2E, 13, 0x0000 );
98 fRegs[kIRQHL1] = SimpleReg_t("IRQHL1", 0x0B2F, 13, 0x0000 );
99 fRegs[kIA2IRQ0] = SimpleReg_t("IA2IRQ0", 0x0B40, 12, 0x000 ); // IVT of CPU2
100 fRegs[kIA2IRQ1] = SimpleReg_t("IA2IRQ1", 0x0B41, 12, 0x000 );
101 fRegs[kIA2IRQ2] = SimpleReg_t("IA2IRQ2", 0x0B42, 12, 0x000 );
102 fRegs[kIA2IRQ3] = SimpleReg_t("IA2IRQ3", 0x0B43, 12, 0x000 );
103 fRegs[kIA2IRQ4] = SimpleReg_t("IA2IRQ4", 0x0B44, 12, 0x000 );
104 fRegs[kIA2IRQ5] = SimpleReg_t("IA2IRQ5", 0x0B45, 12, 0x000 );
105 fRegs[kIA2IRQ6] = SimpleReg_t("IA2IRQ6", 0x0B46, 12, 0x000 );
106 fRegs[kIA2IRQ7] = SimpleReg_t("IA2IRQ7", 0x0B47, 12, 0x000 );
107 fRegs[kIA2IRQ8] = SimpleReg_t("IA2IRQ8", 0x0B48, 12, 0x000 );
108 fRegs[kIA2IRQ9] = SimpleReg_t("IA2IRQ9", 0x0B49, 12, 0x000 );
109 fRegs[kIA2IRQA] = SimpleReg_t("IA2IRQA", 0x0B4A, 12, 0x000 );
110 fRegs[kIA2IRQB] = SimpleReg_t("IA2IRQB", 0x0B4B, 12, 0x000 );
111 fRegs[kIA2IRQC] = SimpleReg_t("IA2IRQC", 0x0B4C, 12, 0x000 );
112 fRegs[kIRQSW2] = SimpleReg_t("IRQSW2", 0x0B4D, 13, 0x1FFF );
113 fRegs[kIRQHW2] = SimpleReg_t("IRQHW2", 0x0B4E, 13, 0x0000 );
114 fRegs[kIRQHL2] = SimpleReg_t("IRQHL2", 0x0B4F, 13, 0x0000 );
115 fRegs[kIA3IRQ0] = SimpleReg_t("IA3IRQ0", 0x0B60, 12, 0x000 ); // IVT of CPU3
116 fRegs[kIA3IRQ1] = SimpleReg_t("IA3IRQ1", 0x0B61, 12, 0x000 );
117 fRegs[kIA3IRQ2] = SimpleReg_t("IA3IRQ2", 0x0B62, 12, 0x000 );
118 fRegs[kIA3IRQ3] = SimpleReg_t("IA3IRQ3", 0x0B63, 12, 0x000 );
119 fRegs[kIA3IRQ4] = SimpleReg_t("IA3IRQ4", 0x0B64, 12, 0x000 );
120 fRegs[kIA3IRQ5] = SimpleReg_t("IA3IRQ5", 0x0B65, 12, 0x000 );
121 fRegs[kIA3IRQ6] = SimpleReg_t("IA3IRQ6", 0x0B66, 12, 0x000 );
122 fRegs[kIA3IRQ7] = SimpleReg_t("IA3IRQ7", 0x0B67, 12, 0x000 );
123 fRegs[kIA3IRQ8] = SimpleReg_t("IA3IRQ8", 0x0B68, 12, 0x000 );
124 fRegs[kIA3IRQ9] = SimpleReg_t("IA3IRQ9", 0x0B69, 12, 0x000 );
125 fRegs[kIA3IRQA] = SimpleReg_t("IA3IRQA", 0x0B6A, 12, 0x000 );
126 fRegs[kIA3IRQB] = SimpleReg_t("IA3IRQB", 0x0B6B, 12, 0x000 );
127 fRegs[kIA3IRQC] = SimpleReg_t("IA3IRQC", 0x0B6C, 12, 0x000 );
128 fRegs[kIRQSW3] = SimpleReg_t("IRQSW3", 0x0B6D, 13, 0x1FFF );
129 fRegs[kIRQHW3] = SimpleReg_t("IRQHW3", 0x0B6E, 13, 0x0000 );
130 fRegs[kIRQHL3] = SimpleReg_t("IRQHL3", 0x0B6F, 13, 0x0000 );
131 fRegs[kCTGDINI] = SimpleReg_t("CTGDINI", 0x0B80, 32, 0x00000000 ); // Global Counter/Timer
132 fRegs[kCTGCTRL] = SimpleReg_t("CTGCTRL", 0x0B81, 12, 0xE3F );
133 fRegs[kC08CPU0] = SimpleReg_t("C08CPU0", 0x0C00, 32, 0x00000000 ); // CPU constants
134 fRegs[kC09CPU0] = SimpleReg_t("C09CPU0", 0x0C01, 32, 0x00000000 );
135 fRegs[kC10CPU0] = SimpleReg_t("C10CPU0", 0x0C02, 32, 0x00000000 );
136 fRegs[kC11CPU0] = SimpleReg_t("C11CPU0", 0x0C03, 32, 0x00000000 );
137 fRegs[kC12CPUA] = SimpleReg_t("C12CPUA", 0x0C04, 32, 0x00000000 );
138 fRegs[kC13CPUA] = SimpleReg_t("C13CPUA", 0x0C05, 32, 0x00000000 );
139 fRegs[kC14CPUA] = SimpleReg_t("C14CPUA", 0x0C06, 32, 0x00000000 );
140 fRegs[kC15CPUA] = SimpleReg_t("C15CPUA", 0x0C07, 32, 0x00000000 );
141 fRegs[kC08CPU1] = SimpleReg_t("C08CPU1", 0x0C08, 32, 0x00000000 );
142 fRegs[kC09CPU1] = SimpleReg_t("C09CPU1", 0x0C09, 32, 0x00000000 );
143 fRegs[kC10CPU1] = SimpleReg_t("C10CPU1", 0x0C0A, 32, 0x00000000 );
144 fRegs[kC11CPU1] = SimpleReg_t("C11CPU1", 0x0C0B, 32, 0x00000000 );
145 fRegs[kC08CPU2] = SimpleReg_t("C08CPU2", 0x0C10, 32, 0x00000000 );
146 fRegs[kC09CPU2] = SimpleReg_t("C09CPU2", 0x0C11, 32, 0x00000000 );
147 fRegs[kC10CPU2] = SimpleReg_t("C10CPU2", 0x0C12, 32, 0x00000000 );
148 fRegs[kC11CPU2] = SimpleReg_t("C11CPU2", 0x0C13, 32, 0x00000000 );
149 fRegs[kC08CPU3] = SimpleReg_t("C08CPU3", 0x0C18, 32, 0x00000000 );
150 fRegs[kC09CPU3] = SimpleReg_t("C09CPU3", 0x0C19, 32, 0x00000000 );
151 fRegs[kC10CPU3] = SimpleReg_t("C10CPU3", 0x0C1A, 32, 0x00000000 );
152 fRegs[kC11CPU3] = SimpleReg_t("C11CPU3", 0x0C1B, 32, 0x00000000 );
153 fRegs[kNMOD] = SimpleReg_t("NMOD", 0x0D40, 6, 0x08 ); // NI interface
154 fRegs[kNDLY] = SimpleReg_t("NDLY", 0x0D41, 30, 0x24924924 );
155 fRegs[kNED] = SimpleReg_t("NED", 0x0D42, 16, 0xA240 );
156 fRegs[kNTRO] = SimpleReg_t("NTRO", 0x0D43, 18, 0x3FFFC );
157 fRegs[kNRRO] = SimpleReg_t("NRRO", 0x0D44, 18, 0x3FFFC );
158 fRegs[kNES] = SimpleReg_t("NES", 0x0D45, 32, 0x00000000 );
159 fRegs[kNTP] = SimpleReg_t("NTP", 0x0D46, 32, 0x0000FFFF );
160 fRegs[kNBND] = SimpleReg_t("NBND", 0x0D47, 16, 0x6020 );
161 fRegs[kNP0] = SimpleReg_t("NP0", 0x0D48, 11, 0x44C );
162 fRegs[kNP1] = SimpleReg_t("NP1", 0x0D49, 11, 0x44C );
163 fRegs[kNP2] = SimpleReg_t("NP2", 0x0D4A, 11, 0x44C );
164 fRegs[kNP3] = SimpleReg_t("NP3", 0x0D4B, 11, 0x44C );
165 fRegs[kNCUT] = SimpleReg_t("NCUT", 0x0D4C, 32, 0xFFFFFFFF );
166 fRegs[kTPPT0] = SimpleReg_t("TPPT0", 0x3000, 7, 0x01 ); // Filter and Preprocessor
167 fRegs[kTPFS] = SimpleReg_t("TPFS", 0x3001, 7, 0x05 );
168 fRegs[kTPFE] = SimpleReg_t("TPFE", 0x3002, 7, 0x14 );
169 fRegs[kTPPGR] = SimpleReg_t("TPPGR", 0x3003, 7, 0x15 );
170 fRegs[kTPPAE] = SimpleReg_t("TPPAE", 0x3004, 7, 0x1E );
171 fRegs[kTPQS0] = SimpleReg_t("TPQS0", 0x3005, 7, 0x00 );
172 fRegs[kTPQE0] = SimpleReg_t("TPQE0", 0x3006, 7, 0x0A );
173 fRegs[kTPQS1] = SimpleReg_t("TPQS1", 0x3007, 7, 0x0B );
174 fRegs[kTPQE1] = SimpleReg_t("TPQE1", 0x3008, 7, 0x14 );
175 fRegs[kEBD] = SimpleReg_t("EBD", 0x3009, 3, 0x0 );
176 fRegs[kEBAQA] = SimpleReg_t("EBAQA", 0x300A, 7, 0x00 );
177 fRegs[kEBSIA] = SimpleReg_t("EBSIA", 0x300B, 7, 0x20 );
178 fRegs[kEBSF] = SimpleReg_t("EBSF", 0x300C, 1, 0x1 );
179 fRegs[kEBSIM] = SimpleReg_t("EBSIM", 0x300D, 1, 0x1 );
180 fRegs[kEBPP] = SimpleReg_t("EBPP", 0x300E, 1, 0x1 );
181 fRegs[kEBPC] = SimpleReg_t("EBPC", 0x300F, 1, 0x1 );
182 fRegs[kEBIS] = SimpleReg_t("EBIS", 0x3014, 10, 0x005 );
183 fRegs[kEBIT] = SimpleReg_t("EBIT", 0x3015, 12, 0x028 );
184 fRegs[kEBIL] = SimpleReg_t("EBIL", 0x3016, 8, 0xF0 );
185 fRegs[kEBIN] = SimpleReg_t("EBIN", 0x3017, 1, 0x1 );
186 fRegs[kFLBY] = SimpleReg_t("FLBY", 0x3018, 1, 0x0 );
187 fRegs[kFPBY] = SimpleReg_t("FPBY", 0x3019, 1, 0x0 );
188 fRegs[kFGBY] = SimpleReg_t("FGBY", 0x301A, 1, 0x0 );
189 fRegs[kFTBY] = SimpleReg_t("FTBY", 0x301B, 1, 0x0 );
190 fRegs[kFCBY] = SimpleReg_t("FCBY", 0x301C, 1, 0x0 );
191 fRegs[kFPTC] = SimpleReg_t("FPTC", 0x3020, 2, 0x3 );
192 fRegs[kFPNP] = SimpleReg_t("FPNP", 0x3021, 9, 0x078 );
193 fRegs[kFPCL] = SimpleReg_t("FPCL", 0x3022, 1, 0x1 );
194 fRegs[kFGTA] = SimpleReg_t("FGTA", 0x3028, 12, 0x014 );
195 fRegs[kFGTB] = SimpleReg_t("FGTB", 0x3029, 12, 0x80C );
196 fRegs[kFGCL] = SimpleReg_t("FGCL", 0x302A, 1, 0x1 );
197 fRegs[kFTAL] = SimpleReg_t("FTAL", 0x3030, 10, 0x0F6 );
198 fRegs[kFTLL] = SimpleReg_t("FTLL", 0x3031, 9, 0x11D );
199 fRegs[kFTLS] = SimpleReg_t("FTLS", 0x3032, 9, 0x0D3 );
200 fRegs[kFCW1] = SimpleReg_t("FCW1", 0x3038, 8, 0x1E );
201 fRegs[kFCW2] = SimpleReg_t("FCW2", 0x3039, 8, 0xD4 );
202 fRegs[kFCW3] = SimpleReg_t("FCW3", 0x303A, 8, 0xE6 );
203 fRegs[kFCW4] = SimpleReg_t("FCW4", 0x303B, 8, 0x4A );
204 fRegs[kFCW5] = SimpleReg_t("FCW5", 0x303C, 8, 0xEF );
205 fRegs[kTPFP] = SimpleReg_t("TPFP", 0x3040, 9, 0x037 );
206 fRegs[kTPHT] = SimpleReg_t("TPHT", 0x3041, 14, 0x00A0 );
207 fRegs[kTPVT] = SimpleReg_t("TPVT", 0x3042, 6, 0x00 );
208 fRegs[kTPVBY] = SimpleReg_t("TPVBY", 0x3043, 1, 0x0 );
209 fRegs[kTPCT] = SimpleReg_t("TPCT", 0x3044, 5, 0x08 );
210 fRegs[kTPCL] = SimpleReg_t("TPCL", 0x3045, 5, 0x01 );
211 fRegs[kTPCBY] = SimpleReg_t("TPCBY", 0x3046, 1, 0x1 );
212 fRegs[kTPD] = SimpleReg_t("TPD", 0x3047, 4, 0xF );
213 fRegs[kTPCI0] = SimpleReg_t("TPCI0", 0x3048, 5, 0x00 );
214 fRegs[kTPCI1] = SimpleReg_t("TPCI1", 0x3049, 5, 0x00 );
215 fRegs[kTPCI2] = SimpleReg_t("TPCI2", 0x304A, 5, 0x00 );
216 fRegs[kTPCI3] = SimpleReg_t("TPCI3", 0x304B, 5, 0x00 );
217 fRegs[kADCMSK] = SimpleReg_t("ADCMSK", 0x3050, 21, 0x1FFFFF );
218 fRegs[kADCINB] = SimpleReg_t("ADCINB", 0x3051, 2, 0x2 );
219 fRegs[kADCDAC] = SimpleReg_t("ADCDAC", 0x3052, 5, 0x10 );
220 fRegs[kADCPAR] = SimpleReg_t("ADCPAR", 0x3053, 18, 0x195EF );
221 fRegs[kADCTST] = SimpleReg_t("ADCTST", 0x3054, 2, 0x0 );
222 fRegs[kSADCAZ] = SimpleReg_t("SADCAZ", 0x3055, 1, 0x1 );
223 fRegs[kFGF0] = SimpleReg_t("FGF0", 0x3080, 9, 0x000 );
224 fRegs[kFGF1] = SimpleReg_t("FGF1", 0x3081, 9, 0x000 );
225 fRegs[kFGF2] = SimpleReg_t("FGF2", 0x3082, 9, 0x000 );
226 fRegs[kFGF3] = SimpleReg_t("FGF3", 0x3083, 9, 0x000 );
227 fRegs[kFGF4] = SimpleReg_t("FGF4", 0x3084, 9, 0x000 );
228 fRegs[kFGF5] = SimpleReg_t("FGF5", 0x3085, 9, 0x000 );
229 fRegs[kFGF6] = SimpleReg_t("FGF6", 0x3086, 9, 0x000 );
230 fRegs[kFGF7] = SimpleReg_t("FGF7", 0x3087, 9, 0x000 );
231 fRegs[kFGF8] = SimpleReg_t("FGF8", 0x3088, 9, 0x000 );
232 fRegs[kFGF9] = SimpleReg_t("FGF9", 0x3089, 9, 0x000 );
233 fRegs[kFGF10] = SimpleReg_t("FGF10", 0x308A, 9, 0x000 );
234 fRegs[kFGF11] = SimpleReg_t("FGF11", 0x308B, 9, 0x000 );
235 fRegs[kFGF12] = SimpleReg_t("FGF12", 0x308C, 9, 0x000 );
236 fRegs[kFGF13] = SimpleReg_t("FGF13", 0x308D, 9, 0x000 );
237 fRegs[kFGF14] = SimpleReg_t("FGF14", 0x308E, 9, 0x000 );
238 fRegs[kFGF15] = SimpleReg_t("FGF15", 0x308F, 9, 0x000 );
239 fRegs[kFGF16] = SimpleReg_t("FGF16", 0x3090, 9, 0x000 );
240 fRegs[kFGF17] = SimpleReg_t("FGF17", 0x3091, 9, 0x000 );
241 fRegs[kFGF18] = SimpleReg_t("FGF18", 0x3092, 9, 0x000 );
242 fRegs[kFGF19] = SimpleReg_t("FGF19", 0x3093, 9, 0x000 );
243 fRegs[kFGF20] = SimpleReg_t("FGF20", 0x3094, 9, 0x000 );
244 fRegs[kFGA0] = SimpleReg_t("FGA0", 0x30A0, 6, 0x00 );
245 fRegs[kFGA1] = SimpleReg_t("FGA1", 0x30A1, 6, 0x00 );
246 fRegs[kFGA2] = SimpleReg_t("FGA2", 0x30A2, 6, 0x00 );
247 fRegs[kFGA3] = SimpleReg_t("FGA3", 0x30A3, 6, 0x00 );
248 fRegs[kFGA4] = SimpleReg_t("FGA4", 0x30A4, 6, 0x00 );
249 fRegs[kFGA5] = SimpleReg_t("FGA5", 0x30A5, 6, 0x00 );
250 fRegs[kFGA6] = SimpleReg_t("FGA6", 0x30A6, 6, 0x00 );
251 fRegs[kFGA7] = SimpleReg_t("FGA7", 0x30A7, 6, 0x00 );
252 fRegs[kFGA8] = SimpleReg_t("FGA8", 0x30A8, 6, 0x00 );
253 fRegs[kFGA9] = SimpleReg_t("FGA9", 0x30A9, 6, 0x00 );
254 fRegs[kFGA10] = SimpleReg_t("FGA10", 0x30AA, 6, 0x00 );
255 fRegs[kFGA11] = SimpleReg_t("FGA11", 0x30AB, 6, 0x00 );
256 fRegs[kFGA12] = SimpleReg_t("FGA12", 0x30AC, 6, 0x00 );
257 fRegs[kFGA13] = SimpleReg_t("FGA13", 0x30AD, 6, 0x00 );
258 fRegs[kFGA14] = SimpleReg_t("FGA14", 0x30AE, 6, 0x00 );
259 fRegs[kFGA15] = SimpleReg_t("FGA15", 0x30AF, 6, 0x00 );
260 fRegs[kFGA16] = SimpleReg_t("FGA16", 0x30B0, 6, 0x00 );
261 fRegs[kFGA17] = SimpleReg_t("FGA17", 0x30B1, 6, 0x00 );
262 fRegs[kFGA18] = SimpleReg_t("FGA18", 0x30B2, 6, 0x00 );
263 fRegs[kFGA19] = SimpleReg_t("FGA19", 0x30B3, 6, 0x00 );
264 fRegs[kFGA20] = SimpleReg_t("FGA20", 0x30B4, 6, 0x00 );
265 fRegs[kFLL00] = SimpleReg_t("FLL00", 0x3100, 6, 0x00 ); // non-linearity table, 64 x 6 bits
266 fRegs[kFLL01] = SimpleReg_t("FLL01", 0x3101, 6, 0x00 );
267 fRegs[kFLL02] = SimpleReg_t("FLL02", 0x3102, 6, 0x00 );
268 fRegs[kFLL03] = SimpleReg_t("FLL03", 0x3103, 6, 0x00 );
269 fRegs[kFLL04] = SimpleReg_t("FLL04", 0x3104, 6, 0x00 );
270 fRegs[kFLL05] = SimpleReg_t("FLL05", 0x3105, 6, 0x00 );
271 fRegs[kFLL06] = SimpleReg_t("FLL06", 0x3106, 6, 0x00 );
272 fRegs[kFLL07] = SimpleReg_t("FLL07", 0x3107, 6, 0x00 );
273 fRegs[kFLL08] = SimpleReg_t("FLL08", 0x3108, 6, 0x00 );
274 fRegs[kFLL09] = SimpleReg_t("FLL09", 0x3109, 6, 0x00 );
275 fRegs[kFLL0A] = SimpleReg_t("FLL0A", 0x310A, 6, 0x00 );
276 fRegs[kFLL0B] = SimpleReg_t("FLL0B", 0x310B, 6, 0x00 );
277 fRegs[kFLL0C] = SimpleReg_t("FLL0C", 0x310C, 6, 0x00 );
278 fRegs[kFLL0D] = SimpleReg_t("FLL0D", 0x310D, 6, 0x00 );
279 fRegs[kFLL0E] = SimpleReg_t("FLL0E", 0x310E, 6, 0x00 );
280 fRegs[kFLL0F] = SimpleReg_t("FLL0F", 0x310F, 6, 0x00 );
281 fRegs[kFLL10] = SimpleReg_t("FLL10", 0x3110, 6, 0x00 );
282 fRegs[kFLL11] = SimpleReg_t("FLL11", 0x3111, 6, 0x00 );
283 fRegs[kFLL12] = SimpleReg_t("FLL12", 0x3112, 6, 0x00 );
284 fRegs[kFLL13] = SimpleReg_t("FLL13", 0x3113, 6, 0x00 );
285 fRegs[kFLL14] = SimpleReg_t("FLL14", 0x3114, 6, 0x00 );
286 fRegs[kFLL15] = SimpleReg_t("FLL15", 0x3115, 6, 0x00 );
287 fRegs[kFLL16] = SimpleReg_t("FLL16", 0x3116, 6, 0x00 );
288 fRegs[kFLL17] = SimpleReg_t("FLL17", 0x3117, 6, 0x00 );
289 fRegs[kFLL18] = SimpleReg_t("FLL18", 0x3118, 6, 0x00 );
290 fRegs[kFLL19] = SimpleReg_t("FLL19", 0x3119, 6, 0x00 );
291 fRegs[kFLL1A] = SimpleReg_t("FLL1A", 0x311A, 6, 0x00 );
292 fRegs[kFLL1B] = SimpleReg_t("FLL1B", 0x311B, 6, 0x00 );
293 fRegs[kFLL1C] = SimpleReg_t("FLL1C", 0x311C, 6, 0x00 );
294 fRegs[kFLL1D] = SimpleReg_t("FLL1D", 0x311D, 6, 0x00 );
295 fRegs[kFLL1E] = SimpleReg_t("FLL1E", 0x311E, 6, 0x00 );
296 fRegs[kFLL1F] = SimpleReg_t("FLL1F", 0x311F, 6, 0x00 );
297 fRegs[kFLL20] = SimpleReg_t("FLL20", 0x3120, 6, 0x00 );
298 fRegs[kFLL21] = SimpleReg_t("FLL21", 0x3121, 6, 0x00 );
299 fRegs[kFLL22] = SimpleReg_t("FLL22", 0x3122, 6, 0x00 );
300 fRegs[kFLL23] = SimpleReg_t("FLL23", 0x3123, 6, 0x00 );
301 fRegs[kFLL24] = SimpleReg_t("FLL24", 0x3124, 6, 0x00 );
302 fRegs[kFLL25] = SimpleReg_t("FLL25", 0x3125, 6, 0x00 );
303 fRegs[kFLL26] = SimpleReg_t("FLL26", 0x3126, 6, 0x00 );
304 fRegs[kFLL27] = SimpleReg_t("FLL27", 0x3127, 6, 0x00 );
305 fRegs[kFLL28] = SimpleReg_t("FLL28", 0x3128, 6, 0x00 );
306 fRegs[kFLL29] = SimpleReg_t("FLL29", 0x3129, 6, 0x00 );
307 fRegs[kFLL2A] = SimpleReg_t("FLL2A", 0x312A, 6, 0x00 );
308 fRegs[kFLL2B] = SimpleReg_t("FLL2B", 0x312B, 6, 0x00 );
309 fRegs[kFLL2C] = SimpleReg_t("FLL2C", 0x312C, 6, 0x00 );
310 fRegs[kFLL2D] = SimpleReg_t("FLL2D", 0x312D, 6, 0x00 );
311 fRegs[kFLL2E] = SimpleReg_t("FLL2E", 0x312E, 6, 0x00 );
312 fRegs[kFLL2F] = SimpleReg_t("FLL2F", 0x312F, 6, 0x00 );
313 fRegs[kFLL30] = SimpleReg_t("FLL30", 0x3130, 6, 0x00 );
314 fRegs[kFLL31] = SimpleReg_t("FLL31", 0x3131, 6, 0x00 );
315 fRegs[kFLL32] = SimpleReg_t("FLL32", 0x3132, 6, 0x00 );
316 fRegs[kFLL33] = SimpleReg_t("FLL33", 0x3133, 6, 0x00 );
317 fRegs[kFLL34] = SimpleReg_t("FLL34", 0x3134, 6, 0x00 );
318 fRegs[kFLL35] = SimpleReg_t("FLL35", 0x3135, 6, 0x00 );
319 fRegs[kFLL36] = SimpleReg_t("FLL36", 0x3136, 6, 0x00 );
320 fRegs[kFLL37] = SimpleReg_t("FLL37", 0x3137, 6, 0x00 );
321 fRegs[kFLL38] = SimpleReg_t("FLL38", 0x3138, 6, 0x00 );
322 fRegs[kFLL39] = SimpleReg_t("FLL39", 0x3139, 6, 0x00 );
323 fRegs[kFLL3A] = SimpleReg_t("FLL3A", 0x313A, 6, 0x00 );
324 fRegs[kFLL3B] = SimpleReg_t("FLL3B", 0x313B, 6, 0x00 );
325 fRegs[kFLL3C] = SimpleReg_t("FLL3C", 0x313C, 6, 0x00 );
326 fRegs[kFLL3D] = SimpleReg_t("FLL3D", 0x313D, 6, 0x00 );
327 fRegs[kFLL3E] = SimpleReg_t("FLL3E", 0x313E, 6, 0x00 );
328 fRegs[kFLL3F] = SimpleReg_t("FLL3F", 0x313F, 6, 0x00 );
329 fRegs[kPASADEL] = SimpleReg_t("PASADEL", 0x3158, 8, 0xFF ); // end of non-lin table
330 fRegs[kPASAPHA] = SimpleReg_t("PASAPHA", 0x3159, 6, 0x3F );
331 fRegs[kPASAPRA] = SimpleReg_t("PASAPRA", 0x315A, 6, 0x0F );
332 fRegs[kPASADAC] = SimpleReg_t("PASADAC", 0x315B, 8, 0x80 );
333 fRegs[kPASACHM] = SimpleReg_t("PASACHM", 0x315C, 19, 0x7FFFF );
334 fRegs[kPASASTL] = SimpleReg_t("PASASTL", 0x315D, 8, 0xFF );
335 fRegs[kPASAPR1] = SimpleReg_t("PASAPR1", 0x315E, 1, 0x0 );
336 fRegs[kPASAPR0] = SimpleReg_t("PASAPR0", 0x315F, 1, 0x0 );
337 fRegs[kSADCTRG] = SimpleReg_t("SADCTRG", 0x3161, 1, 0x0 );
338 fRegs[kSADCRUN] = SimpleReg_t("SADCRUN", 0x3162, 1, 0x0 );
339 fRegs[kSADCPWR] = SimpleReg_t("SADCPWR", 0x3163, 3, 0x7 );
340 fRegs[kL0TSIM] = SimpleReg_t("L0TSIM", 0x3165, 14, 0x0050 );
341 fRegs[kSADCEC] = SimpleReg_t("SADCEC", 0x3166, 7, 0x00 );
342 fRegs[kSADCMC] = SimpleReg_t("SADCMC", 0x3170, 8, 0xC0 );
343 fRegs[kSADCOC] = SimpleReg_t("SADCOC", 0x3171, 8, 0x19 );
344 fRegs[kSADCGTB] = SimpleReg_t("SADCGTB", 0x3172, 32, 0x37737700 );
345 fRegs[kSEBDEN] = SimpleReg_t("SEBDEN", 0x3178, 3, 0x0 );
346 fRegs[kSEBDOU] = SimpleReg_t("SEBDOU", 0x3179, 3, 0x0 );
347 fRegs[kTPL00] = SimpleReg_t("TPL00", 0x3180, 5, 0x00 ); // pos table, 128 x 5 bits
348 fRegs[kTPL01] = SimpleReg_t("TPL01", 0x3181, 5, 0x00 );
349 fRegs[kTPL02] = SimpleReg_t("TPL02", 0x3182, 5, 0x00 );
350 fRegs[kTPL03] = SimpleReg_t("TPL03", 0x3183, 5, 0x00 );
351 fRegs[kTPL04] = SimpleReg_t("TPL04", 0x3184, 5, 0x00 );
352 fRegs[kTPL05] = SimpleReg_t("TPL05", 0x3185, 5, 0x00 );
353 fRegs[kTPL06] = SimpleReg_t("TPL06", 0x3186, 5, 0x00 );
354 fRegs[kTPL07] = SimpleReg_t("TPL07", 0x3187, 5, 0x00 );
355 fRegs[kTPL08] = SimpleReg_t("TPL08", 0x3188, 5, 0x00 );
356 fRegs[kTPL09] = SimpleReg_t("TPL09", 0x3189, 5, 0x00 );
357 fRegs[kTPL0A] = SimpleReg_t("TPL0A", 0x318A, 5, 0x00 );
358 fRegs[kTPL0B] = SimpleReg_t("TPL0B", 0x318B, 5, 0x00 );
359 fRegs[kTPL0C] = SimpleReg_t("TPL0C", 0x318C, 5, 0x00 );
360 fRegs[kTPL0D] = SimpleReg_t("TPL0D", 0x318D, 5, 0x00 );
361 fRegs[kTPL0E] = SimpleReg_t("TPL0E", 0x318E, 5, 0x00 );
362 fRegs[kTPL0F] = SimpleReg_t("TPL0F", 0x318F, 5, 0x00 );
363 fRegs[kTPL10] = SimpleReg_t("TPL10", 0x3190, 5, 0x00 );
364 fRegs[kTPL11] = SimpleReg_t("TPL11", 0x3191, 5, 0x00 );
365 fRegs[kTPL12] = SimpleReg_t("TPL12", 0x3192, 5, 0x00 );
366 fRegs[kTPL13] = SimpleReg_t("TPL13", 0x3193, 5, 0x00 );
367 fRegs[kTPL14] = SimpleReg_t("TPL14", 0x3194, 5, 0x00 );
368 fRegs[kTPL15] = SimpleReg_t("TPL15", 0x3195, 5, 0x00 );
369 fRegs[kTPL16] = SimpleReg_t("TPL16", 0x3196, 5, 0x00 );
370 fRegs[kTPL17] = SimpleReg_t("TPL17", 0x3197, 5, 0x00 );
371 fRegs[kTPL18] = SimpleReg_t("TPL18", 0x3198, 5, 0x00 );
372 fRegs[kTPL19] = SimpleReg_t("TPL19", 0x3199, 5, 0x00 );
373 fRegs[kTPL1A] = SimpleReg_t("TPL1A", 0x319A, 5, 0x00 );
374 fRegs[kTPL1B] = SimpleReg_t("TPL1B", 0x319B, 5, 0x00 );
375 fRegs[kTPL1C] = SimpleReg_t("TPL1C", 0x319C, 5, 0x00 );
376 fRegs[kTPL1D] = SimpleReg_t("TPL1D", 0x319D, 5, 0x00 );
377 fRegs[kTPL1E] = SimpleReg_t("TPL1E", 0x319E, 5, 0x00 );
378 fRegs[kTPL1F] = SimpleReg_t("TPL1F", 0x319F, 5, 0x00 );
379 fRegs[kTPL20] = SimpleReg_t("TPL20", 0x31A0, 5, 0x00 );
380 fRegs[kTPL21] = SimpleReg_t("TPL21", 0x31A1, 5, 0x00 );
381 fRegs[kTPL22] = SimpleReg_t("TPL22", 0x31A2, 5, 0x00 );
382 fRegs[kTPL23] = SimpleReg_t("TPL23", 0x31A3, 5, 0x00 );
383 fRegs[kTPL24] = SimpleReg_t("TPL24", 0x31A4, 5, 0x00 );
384 fRegs[kTPL25] = SimpleReg_t("TPL25", 0x31A5, 5, 0x00 );
385 fRegs[kTPL26] = SimpleReg_t("TPL26", 0x31A6, 5, 0x00 );
386 fRegs[kTPL27] = SimpleReg_t("TPL27", 0x31A7, 5, 0x00 );
387 fRegs[kTPL28] = SimpleReg_t("TPL28", 0x31A8, 5, 0x00 );
388 fRegs[kTPL29] = SimpleReg_t("TPL29", 0x31A9, 5, 0x00 );
389 fRegs[kTPL2A] = SimpleReg_t("TPL2A", 0x31AA, 5, 0x00 );
390 fRegs[kTPL2B] = SimpleReg_t("TPL2B", 0x31AB, 5, 0x00 );
391 fRegs[kTPL2C] = SimpleReg_t("TPL2C", 0x31AC, 5, 0x00 );
392 fRegs[kTPL2D] = SimpleReg_t("TPL2D", 0x31AD, 5, 0x00 );
393 fRegs[kTPL2E] = SimpleReg_t("TPL2E", 0x31AE, 5, 0x00 );
394 fRegs[kTPL2F] = SimpleReg_t("TPL2F", 0x31AF, 5, 0x00 );
395 fRegs[kTPL30] = SimpleReg_t("TPL30", 0x31B0, 5, 0x00 );
396 fRegs[kTPL31] = SimpleReg_t("TPL31", 0x31B1, 5, 0x00 );
397 fRegs[kTPL32] = SimpleReg_t("TPL32", 0x31B2, 5, 0x00 );
398 fRegs[kTPL33] = SimpleReg_t("TPL33", 0x31B3, 5, 0x00 );
399 fRegs[kTPL34] = SimpleReg_t("TPL34", 0x31B4, 5, 0x00 );
400 fRegs[kTPL35] = SimpleReg_t("TPL35", 0x31B5, 5, 0x00 );
401 fRegs[kTPL36] = SimpleReg_t("TPL36", 0x31B6, 5, 0x00 );
402 fRegs[kTPL37] = SimpleReg_t("TPL37", 0x31B7, 5, 0x00 );
403 fRegs[kTPL38] = SimpleReg_t("TPL38", 0x31B8, 5, 0x00 );
404 fRegs[kTPL39] = SimpleReg_t("TPL39", 0x31B9, 5, 0x00 );
405 fRegs[kTPL3A] = SimpleReg_t("TPL3A", 0x31BA, 5, 0x00 );
406 fRegs[kTPL3B] = SimpleReg_t("TPL3B", 0x31BB, 5, 0x00 );
407 fRegs[kTPL3C] = SimpleReg_t("TPL3C", 0x31BC, 5, 0x00 );
408 fRegs[kTPL3D] = SimpleReg_t("TPL3D", 0x31BD, 5, 0x00 );
409 fRegs[kTPL3E] = SimpleReg_t("TPL3E", 0x31BE, 5, 0x00 );
410 fRegs[kTPL3F] = SimpleReg_t("TPL3F", 0x31BF, 5, 0x00 );
411 fRegs[kTPL40] = SimpleReg_t("TPL40", 0x31C0, 5, 0x00 );
412 fRegs[kTPL41] = SimpleReg_t("TPL41", 0x31C1, 5, 0x00 );
413 fRegs[kTPL42] = SimpleReg_t("TPL42", 0x31C2, 5, 0x00 );
414 fRegs[kTPL43] = SimpleReg_t("TPL43", 0x31C3, 5, 0x00 );
415 fRegs[kTPL44] = SimpleReg_t("TPL44", 0x31C4, 5, 0x00 );
416 fRegs[kTPL45] = SimpleReg_t("TPL45", 0x31C5, 5, 0x00 );
417 fRegs[kTPL46] = SimpleReg_t("TPL46", 0x31C6, 5, 0x00 );
418 fRegs[kTPL47] = SimpleReg_t("TPL47", 0x31C7, 5, 0x00 );
419 fRegs[kTPL48] = SimpleReg_t("TPL48", 0x31C8, 5, 0x00 );
420 fRegs[kTPL49] = SimpleReg_t("TPL49", 0x31C9, 5, 0x00 );
421 fRegs[kTPL4A] = SimpleReg_t("TPL4A", 0x31CA, 5, 0x00 );
422 fRegs[kTPL4B] = SimpleReg_t("TPL4B", 0x31CB, 5, 0x00 );
423 fRegs[kTPL4C] = SimpleReg_t("TPL4C", 0x31CC, 5, 0x00 );
424 fRegs[kTPL4D] = SimpleReg_t("TPL4D", 0x31CD, 5, 0x00 );
425 fRegs[kTPL4E] = SimpleReg_t("TPL4E", 0x31CE, 5, 0x00 );
426 fRegs[kTPL4F] = SimpleReg_t("TPL4F", 0x31CF, 5, 0x00 );
427 fRegs[kTPL50] = SimpleReg_t("TPL50", 0x31D0, 5, 0x00 );
428 fRegs[kTPL51] = SimpleReg_t("TPL51", 0x31D1, 5, 0x00 );
429 fRegs[kTPL52] = SimpleReg_t("TPL52", 0x31D2, 5, 0x00 );
430 fRegs[kTPL53] = SimpleReg_t("TPL53", 0x31D3, 5, 0x00 );
431 fRegs[kTPL54] = SimpleReg_t("TPL54", 0x31D4, 5, 0x00 );
432 fRegs[kTPL55] = SimpleReg_t("TPL55", 0x31D5, 5, 0x00 );
433 fRegs[kTPL56] = SimpleReg_t("TPL56", 0x31D6, 5, 0x00 );
434 fRegs[kTPL57] = SimpleReg_t("TPL57", 0x31D7, 5, 0x00 );
435 fRegs[kTPL58] = SimpleReg_t("TPL58", 0x31D8, 5, 0x00 );
436 fRegs[kTPL59] = SimpleReg_t("TPL59", 0x31D9, 5, 0x00 );
437 fRegs[kTPL5A] = SimpleReg_t("TPL5A", 0x31DA, 5, 0x00 );
438 fRegs[kTPL5B] = SimpleReg_t("TPL5B", 0x31DB, 5, 0x00 );
439 fRegs[kTPL5C] = SimpleReg_t("TPL5C", 0x31DC, 5, 0x00 );
440 fRegs[kTPL5D] = SimpleReg_t("TPL5D", 0x31DD, 5, 0x00 );
441 fRegs[kTPL5E] = SimpleReg_t("TPL5E", 0x31DE, 5, 0x00 );
442 fRegs[kTPL5F] = SimpleReg_t("TPL5F", 0x31DF, 5, 0x00 );
443 fRegs[kTPL60] = SimpleReg_t("TPL60", 0x31E0, 5, 0x00 );
444 fRegs[kTPL61] = SimpleReg_t("TPL61", 0x31E1, 5, 0x00 );
445 fRegs[kTPL62] = SimpleReg_t("TPL62", 0x31E2, 5, 0x00 );
446 fRegs[kTPL63] = SimpleReg_t("TPL63", 0x31E3, 5, 0x00 );
447 fRegs[kTPL64] = SimpleReg_t("TPL64", 0x31E4, 5, 0x00 );
448 fRegs[kTPL65] = SimpleReg_t("TPL65", 0x31E5, 5, 0x00 );
449 fRegs[kTPL66] = SimpleReg_t("TPL66", 0x31E6, 5, 0x00 );
450 fRegs[kTPL67] = SimpleReg_t("TPL67", 0x31E7, 5, 0x00 );
451 fRegs[kTPL68] = SimpleReg_t("TPL68", 0x31E8, 5, 0x00 );
452 fRegs[kTPL69] = SimpleReg_t("TPL69", 0x31E9, 5, 0x00 );
453 fRegs[kTPL6A] = SimpleReg_t("TPL6A", 0x31EA, 5, 0x00 );
454 fRegs[kTPL6B] = SimpleReg_t("TPL6B", 0x31EB, 5, 0x00 );
455 fRegs[kTPL6C] = SimpleReg_t("TPL6C", 0x31EC, 5, 0x00 );
456 fRegs[kTPL6D] = SimpleReg_t("TPL6D", 0x31ED, 5, 0x00 );
457 fRegs[kTPL6E] = SimpleReg_t("TPL6E", 0x31EE, 5, 0x00 );
458 fRegs[kTPL6F] = SimpleReg_t("TPL6F", 0x31EF, 5, 0x00 );
459 fRegs[kTPL70] = SimpleReg_t("TPL70", 0x31F0, 5, 0x00 );
460 fRegs[kTPL71] = SimpleReg_t("TPL71", 0x31F1, 5, 0x00 );
461 fRegs[kTPL72] = SimpleReg_t("TPL72", 0x31F2, 5, 0x00 );
462 fRegs[kTPL73] = SimpleReg_t("TPL73", 0x31F3, 5, 0x00 );
463 fRegs[kTPL74] = SimpleReg_t("TPL74", 0x31F4, 5, 0x00 );
464 fRegs[kTPL75] = SimpleReg_t("TPL75", 0x31F5, 5, 0x00 );
465 fRegs[kTPL76] = SimpleReg_t("TPL76", 0x31F6, 5, 0x00 );
466 fRegs[kTPL77] = SimpleReg_t("TPL77", 0x31F7, 5, 0x00 );
467 fRegs[kTPL78] = SimpleReg_t("TPL78", 0x31F8, 5, 0x00 );
468 fRegs[kTPL79] = SimpleReg_t("TPL79", 0x31F9, 5, 0x00 );
469 fRegs[kTPL7A] = SimpleReg_t("TPL7A", 0x31FA, 5, 0x00 );
470 fRegs[kTPL7B] = SimpleReg_t("TPL7B", 0x31FB, 5, 0x00 );
471 fRegs[kTPL7C] = SimpleReg_t("TPL7C", 0x31FC, 5, 0x00 );
472 fRegs[kTPL7D] = SimpleReg_t("TPL7D", 0x31FD, 5, 0x00 );
473 fRegs[kTPL7E] = SimpleReg_t("TPL7E", 0x31FE, 5, 0x00 );
474 fRegs[kTPL7F] = SimpleReg_t("TPL7F", 0x31FF, 5, 0x00 );
475 fRegs[kMEMRW] = SimpleReg_t("MEMRW", 0xD000, 7, 0x79 ); // end of pos table
476 fRegs[kMEMCOR] = SimpleReg_t("MEMCOR", 0xD001, 9, 0x000 );
477 fRegs[kDMDELA] = SimpleReg_t("DMDELA", 0xD002, 4, 0x8 );
478 fRegs[kDMDELS] = SimpleReg_t("DMDELS", 0xD003, 4, 0x8 );
479
480 InitRegs();
481}
482
483
484AliTRDtrapConfig* AliTRDtrapConfig::Instance()
485{
486 // return a pointer to an instance of this class
487
488 if (!fgInstance) {
489 fgInstance = new AliTRDtrapConfig();
490 fgInstance->LoadConfig();
491 }
492
493 return fgInstance;
494}
495
496
497void AliTRDtrapConfig::InitRegs(void)
498{
499 // Reset the content of all TRAP registers to the reset values (see TRAP User Manual)
500
501 for (Int_t iReg = 0; iReg < kLastReg; iReg++) {
502
503 fRegisterValue[iReg].individualValue = 0x0;
504
505 fRegisterValue[iReg].globalValue = GetRegResetValue((TrapReg_t) iReg);
506 fRegisterValue[iReg].state = RegValue_t::kGlobal;
507 }
508}
509
510
511void AliTRDtrapConfig::ResetRegs(void)
512{
513 // Reset the content of all TRAP registers to the reset values (see TRAP User Manual)
514
515 for (Int_t iReg = 0; iReg < kLastReg; iReg++) {
516 if(fRegisterValue[iReg].state == RegValue_t::kIndividual) {
517 if (fRegisterValue[iReg].individualValue) {
518 delete [] fRegisterValue[iReg].individualValue;
519 fRegisterValue[iReg].individualValue = 0x0;
520 }
521 }
522
523 fRegisterValue[iReg].globalValue = GetRegResetValue((TrapReg_t) iReg);
524 fRegisterValue[iReg].state = RegValue_t::kGlobal;
525 // printf("%-8s: 0x%08x\n", GetRegName((TrapReg_t) iReg), fRegisterValue[iReg].globalValue);
526 }
527}
528
529
530Int_t AliTRDtrapConfig::GetTrapReg(TrapReg_t reg, Int_t det, Int_t rob, Int_t mcm)
531{
532 // get the value of an individual TRAP register
533 // if it is individual for TRAPs a valid TRAP has to be specified
534
535 if ((reg < 0) || (reg >= kLastReg)) {
536 AliError("Non-existing register requested");
537 return -1;
538 }
539 else {
540 if (fRegisterValue[reg].state == RegValue_t::kGlobal) {
541 return fRegisterValue[reg].globalValue;
542 }
543 else if (fRegisterValue[reg].state == RegValue_t::kIndividual) {
544 if((det >= 0 && det < AliTRDgeometry::Ndet()) &&
545 (rob >= 0 && rob < AliTRDfeeParam::GetNrobC1()) &&
546 (mcm >= 0 && mcm < fgkMaxMcm)) {
547 return fRegisterValue[reg].individualValue[det*AliTRDfeeParam::GetNrobC1()*fgkMaxMcm + rob*fgkMaxMcm + mcm];
548 }
549 else {
550 AliError("Invalid MCM specified or register is individual");
551 return -1;
552 }
553 }
554 else { // should never be reached
555 AliError("MCM register status neither kGlobal nor kIndividual");
556 return -1;
557 }
558 }
559 return -1;
560}
561
562
563Bool_t AliTRDtrapConfig::SetTrapReg(TrapReg_t reg, Int_t value)
564{
565 // set a global value for the given TRAP register,
566 // i.e. the same value for all TRAPs
567
568 if (fRegisterValue[reg].state == RegValue_t::kGlobal) {
569 fRegisterValue[reg].globalValue = value;
570 return kTRUE;
571 }
572 else {
573 AliError("Register has individual values");
574 }
575 return kFALSE;
576}
577
578
579Bool_t AliTRDtrapConfig::SetTrapReg(TrapReg_t reg, Int_t value, Int_t det)
580{
581 // set a global value for the given TRAP register,
582 // i.e. the same value for all TRAPs
583
584 if (fRegisterValue[reg].state == RegValue_t::kGlobal) {
585 fRegisterValue[reg].globalValue = value;
586 return kTRUE;
587 }
588 else if (fRegisterValue[reg].state == RegValue_t::kIndividual) {
589 // if the register is in idividual mode but a broadcast is requested, the selected register is
590 // set to value for all MCMs on the chamber
591
592 if( (det>=0 && det<AliTRDgeometry::Ndet())) {
593 for(Int_t rob=0; rob<AliTRDfeeParam::GetNrobC1(); rob++) {
594 for(Int_t mcm=0; mcm<fgkMaxMcm; mcm++)
595 fRegisterValue[reg].individualValue[det*AliTRDfeeParam::GetNrobC1()*fgkMaxMcm + rob*fgkMaxMcm + mcm] = value;
596 }
597 }
598 else {
599 AliError("Invalid value for det, ROB or MCM selected");
600 return kFALSE;
601 }
602 }
603 else { // should never be reached
604 AliError("MCM register status neither kGlobal nor kIndividual");
605 return kFALSE;
606 }
607
608 return kFALSE;
609}
610
611
612Bool_t AliTRDtrapConfig::SetTrapReg(TrapReg_t reg, Int_t value, Int_t det, Int_t rob, Int_t mcm)
613{
614 // set the value for the given TRAP register of an individual MCM
615
616 //std::cout << "-- reg: 0x" << std::hex << fRegs[reg].addr << std::dec << ", data " << value << ", det " << det << ", rob " << rob << ", mcm " << mcm << std::endl;
617
618 if( (det >= 0 && det < AliTRDgeometry::Ndet()) &&
619 (rob >= 0 && rob < AliTRDfeeParam::GetNrobC1()) &&
620 (mcm >= 0 && mcm < fgkMaxMcm) ) {
621 if (fRegisterValue[reg].state == RegValue_t::kGlobal) {
622 Int_t defaultValue = fRegisterValue[reg].globalValue;
623
624 fRegisterValue[reg].state = RegValue_t::kIndividual;
625 fRegisterValue[reg].individualValue = new Int_t[AliTRDgeometry::Ndet()*AliTRDfeeParam::GetNrobC1()*fgkMaxMcm];
626
627 for(Int_t i = 0; i < AliTRDgeometry::Ndet()*AliTRDfeeParam::GetNrobC1()*fgkMaxMcm; i++)
628 fRegisterValue[reg].individualValue[i] = defaultValue; // set the requested register of all MCMs to the value previously stored
629
630 fRegisterValue[reg].individualValue[det*AliTRDfeeParam::GetNrobC1()*fgkMaxMcm + rob*fgkMaxMcm + mcm] = value;
631 }
632 else if (fRegisterValue[reg].state == RegValue_t::kIndividual) {
633 fRegisterValue[reg].individualValue[det*AliTRDfeeParam::GetNrobC1()*fgkMaxMcm + rob*fgkMaxMcm + mcm] = value;
634 }
635 else { // should never be reached
636 AliError("MCM register status neither kGlobal nor kIndividual");
637 return kFALSE;
638 }
639 }
640 else {
641 AliError("Invalid value for det, ROB or MCM selected");
642 return kFALSE;
643 }
644
645 return kTRUE;
646}
647
648
649Int_t AliTRDtrapConfig::Peek(Int_t addr, Int_t /* det */, Int_t /* rob */, Int_t /* mcm */)
650{
651 // reading from given address
652 // not to be used yet
653
654 if ( (addr >= fgkDmemStartAddress) &&
655 (addr < (fgkDmemStartAddress + fgkDmemWords)) ) {
656 printf("DMEM\n");
657 return 0;
658 }
659 else {
660 TrapReg_t mcmReg = GetRegByAddress(addr);
661 if ( mcmReg >= 0 && mcmReg < kLastReg) {
662 printf("Register: %s\n", GetRegName(mcmReg));
663 return 0;
664 }
665 }
666
667 return -1;
668}
669
670
671Bool_t AliTRDtrapConfig::Poke(Int_t addr, Int_t value, Int_t /* det */, Int_t /* rob */, Int_t /* mcm */)
672{
673 // writing to given address
674 // not to be used yet
675
676 if ( (addr >= fgkDmemStartAddress) &&
677 (addr < (fgkDmemStartAddress + fgkDmemWords)) ) {
678 printf("DMEM 0x%08x : %i\n", addr, value);
679 return kTRUE;
680 }
681 else {
682 TrapReg_t mcmReg = GetRegByAddress(addr);
683 if ( mcmReg >= 0 && mcmReg < kLastReg) {
684 printf("Register: %s : %i\n", GetRegName(mcmReg), value);
685 return kTRUE;
686 }
687 }
688
689 return kFALSE;
690}
691
692
693Bool_t AliTRDtrapConfig::SetDmem(Int_t addr, Int_t value)
694{
59f78ad5 695 // Set the content of the given DMEM address
696
ce4786b9 697 if ( (addr >> 14) != 0x3) {
698 AliError(Form("No DMEM address: 0x%08x", addr));
699 return kFALSE;
700 }
701
702 for (Int_t iDet = 0; iDet < 540; iDet++) {
703 for (Int_t iROB = 0; iROB < AliTRDfeeParam::GetNrobC1(); iROB++) {
704 for (Int_t iMCM = 0; iMCM < fgkMaxMcm; iMCM++) {
705 fDmem[iDet*AliTRDfeeParam::GetNrobC1()*fgkMaxMcm + iROB*fgkMaxMcm + iMCM]
706 [addr - fgkDmemStartAddress] = value;
707 }
708 }
709 }
710 return kTRUE;
711}
712
713
714Bool_t AliTRDtrapConfig::SetDmem(Int_t addr, Int_t value, Int_t det)
715{
59f78ad5 716 // Set the content of the given DMEM address
717
ce4786b9 718 for (Int_t iROB = 0; iROB < AliTRDfeeParam::GetNrobC1(); iROB++) {
719 for (Int_t iMCM = 0; iMCM < fgkMaxMcm; iMCM++) {
720 fDmem[det*AliTRDfeeParam::GetNrobC1()*fgkMaxMcm + iROB*fgkMaxMcm + iMCM]
721 [addr - fgkDmemStartAddress] = value;
722 }
723 }
724 return kTRUE;
725}
726
727
728Bool_t AliTRDtrapConfig::SetDmem(Int_t addr, Int_t value, Int_t det, Int_t rob, Int_t mcm)
729{
59f78ad5 730 // Set the content of the given DMEM address
731
ce4786b9 732 fDmem[det*AliTRDfeeParam::GetNrobC1()*fgkMaxMcm + rob*fgkMaxMcm + mcm]
733 [addr - fgkDmemStartAddress] = value;
734 return kTRUE;
735}
736
737
738Int_t AliTRDtrapConfig::GetDmem(Int_t addr, Int_t det, Int_t rob, Int_t mcm)
739{
59f78ad5 740 // Set the content of the given DMEM address
741
ce4786b9 742 return fDmem[det*AliTRDfeeParam::GetNrobC1()*fgkMaxMcm + rob*fgkMaxMcm + mcm]
743 [addr - fgkDmemStartAddress];
744}
745
746
747Bool_t AliTRDtrapConfig::LoadConfig()
748{
749 // load a set of TRAP register values (configuration)
750 // here a default set is implemented for testing
751 // for a detailed description of the registers see the TRAP manual
752
753 // no. of timebins
754 SetTrapReg(kC13CPUA, 24);
755
756 // pedestal filter
757 SetTrapReg(kFPNP, 4*10);
758 SetTrapReg(kFPTC, 0);
759 SetTrapReg(kFPBY, 0); // bypassed!
760
761 // gain filter
762 for (Int_t adc = 0; adc < 20; adc++) {
763 SetTrapReg(TrapReg_t(kFGA0+adc), 40);
764 SetTrapReg(TrapReg_t(kFGF0+adc), 15);
765 }
766 SetTrapReg(kFGTA, 20);
767 SetTrapReg(kFGTB, 2060);
768 SetTrapReg(kFGBY, 0); // bypassed!
769
770 // tail cancellation
771 SetTrapReg(kFTAL, 267);
772 SetTrapReg(kFTLL, 356);
773 SetTrapReg(kFTLS, 387);
774 SetTrapReg(kFTBY, 0);
775
776 // tracklet calculation
777 SetTrapReg(kTPQS0, 5);
778 SetTrapReg(kTPQE0, 10);
779 SetTrapReg(kTPQS1, 11);
780 SetTrapReg(kTPQE1, 20);
781 SetTrapReg(kTPFS, 5);
782 SetTrapReg(kTPFE, 20);
783 SetTrapReg(kTPVBY, 0);
784 SetTrapReg(kTPVT, 10);
785 SetTrapReg(kTPHT, 150);
786 SetTrapReg(kTPFP, 40);
787 SetTrapReg(kTPCL, 1);
788 SetTrapReg(kTPCT, 10);
789
790 // ndrift (+ 5 binary digits)
791 SetDmem(0xc025, 20 << 5);
792 // deflection + tilt correction
793 SetDmem(0xc022, 0);
794 // deflection range table
795 for (Int_t iTrklCh = 0; iTrklCh < 18; iTrklCh++) {
796 SetDmem(0xc030 + 2 * iTrklCh, -64); // min. deflection
797 SetDmem(0xc031 + 2 * iTrklCh, 63); // max. deflection
798 }
799
800 // hit position LUT
801 const UShort_t lutPos[128] = {
802 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15,
803 16, 16, 16, 17, 17, 18, 18, 19, 19, 19, 20, 20, 20, 21, 21, 22, 22, 22, 23, 23, 23, 24, 24, 24, 24, 25, 25, 25, 26, 26, 26, 26,
804 27, 27, 27, 27, 27, 27, 27, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 27, 27, 27, 27, 26,
805 26, 26, 26, 25, 25, 25, 24, 24, 23, 23, 22, 22, 21, 21, 20, 20, 19, 18, 18, 17, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 7};
806 for (Int_t iCOG = 0; iCOG < 128; iCOG++)
807 SetTrapReg((TrapReg_t) (kTPL00 + iCOG), lutPos[iCOG]);
808
809 // event buffer
810 SetTrapReg(kEBSF, 1); // 0: store filtered; 1: store unfiltered
811 // zs applied to data stored in event buffer (sel. by EBSF)
812 SetTrapReg(kEBIS, 15 << 2); // single indicator threshold (plus two digits)
813 SetTrapReg(kEBIT, 30 << 2); // sum indicator threshold (plus two digits)
814 SetTrapReg(kEBIL, 0xf0); // lookup table
815 SetTrapReg(kEBIN, 0); // neighbour sensitivity
816
817 // raw data
818 SetTrapReg(kNES, (0x0000 << 16) | 0x1000);
819
820 return kTRUE;
821}
822
823
824Bool_t AliTRDtrapConfig::LoadConfig(Int_t det, TString filename)
825{
826 // load a TRAP configuration from a file
827 // The file format is the format created by the standalone
828 // command coder: scc / show_cfdat
829 // which are two tools to inspect/export configurations from wingDB
830
831 ResetRegs(); // does not really make sense here???
832
833 std::ifstream infile;
834 infile.open(filename.Data(), std::ifstream::in);
835 if (!infile.is_open()) {
836 AliError("Can not open MCM configuration file");
837 return kFALSE;
838 }
839
840 Int_t cmd, extali, addr, data;
841 Int_t no;
842 char tmp;
843
844 while(infile.good()) {
845 cmd=-1;
846 extali=-1;
847 addr=-1;
848 data=-1;
849 infile >> std::skipws >> no >> tmp >> cmd >> extali >> addr >> data;
850 // std::cout << "no: " << no << ", cmd " << cmd << ", extali " << extali << ", addr " << addr << ", data " << data << endl;
851
852 if(cmd!=-1 && extali!=-1 && addr != -1 && data!= -1) {
853 AddValues(det, cmd, extali, addr, data);
854 }
855 else if(!infile.eof() && !infile.good()) {
856 infile.clear();
857 infile.ignore(256, '\n');
858 }
859
860 if(!infile.eof())
861 infile.clear();
862 }
863
864 infile.close();
865
866 return kTRUE;
867}
868
869
870Bool_t AliTRDtrapConfig::ReadPackedConfig(UInt_t *data, Int_t size)
871{
59f78ad5 872 // Read the packed configuration from the passed memory block
873 //
874 // To be used to retrieve the TRAP configuration from the
875 // configuration as sent in the raw data.
876
ce4786b9 877 Int_t idx = 0;
878 Int_t err = 0;
59f78ad5 879 Int_t step, bwidth, nwords, exitFlag, bitcnt;
ce4786b9 880
881 UShort_t caddr;
59f78ad5 882 UInt_t dat, msk, header, dataHi;
ce4786b9 883
884 while (idx < size) {
885
886 header = *data;
887 data++;
888 idx++;
889
890 AliDebug(5, Form("read: 0x%08x", header));
891
892 if (header & 0x01) // single data
893 {
894 dat = (header >> 2) & 0xFFFF; // 16 bit data
895 caddr = (header >> 18) & 0x3FFF; // 14 bit address
896
897 if (caddr != 0x1FFF) // temp!!! because the end marker was wrong
898 {
899 if (header & 0x02) // check if > 16 bits
900 {
59f78ad5 901 dataHi = *data;
902 AliDebug(5, Form("read: 0x%08x", dataHi));
ce4786b9 903 data++;
904 idx++;
59f78ad5 905 err += ((dataHi ^ (dat | 1)) & 0xFFFF) != 0;
906 dat = (dataHi & 0xFFFF0000) | dat;
ce4786b9 907 }
908 AliDebug(5, Form("addr=0x%04x (%s) data=0x%08x\n", caddr, GetRegName(GetRegByAddress(caddr)), dat));
909 if ( ! Poke(caddr, dat, 0, 0, 0) )
910 AliDebug(5, Form("(single-write): non-existing address 0x%04x containing 0x%08x\n", caddr, header));
911 if (idx > size)
912 {
913 AliDebug(5, Form("(single-write): no more data, missing end marker\n"));
914 return -err;
915 }
916 }
917 else
918 {
919 AliDebug(5, Form("(single-write): address 0x%04x => old endmarker?\n", caddr));
920 return err;
921 }
922 }
923
924 else // block of data
925 {
926 step = (header >> 1) & 0x0003;
927 bwidth = ((header >> 3) & 0x001F) + 1;
928 nwords = (header >> 8) & 0x00FF;
929 caddr = (header >> 16) & 0xFFFF;
59f78ad5 930 exitFlag = (step == 0) || (step == 3) || (nwords == 0);
ce4786b9 931
59f78ad5 932 if (exitFlag)
ce4786b9 933 return err;
934
935 switch (bwidth)
936 {
937 case 15:
938 case 10:
939 case 7:
940 case 6:
941 case 5:
942 {
943 msk = (1 << bwidth) - 1;
944 bitcnt = 0;
945 while (nwords > 0)
946 {
947 nwords--;
948 bitcnt -= bwidth;
949 if (bitcnt < 0)
950 {
951 header = *data;
952 AliDebug(5, Form("read 0x%08x", header));
953 data++;
954 idx++;
955 err += (header & 1);
956 header = header >> 1;
957 bitcnt = 31 - bwidth;
958 }
959 AliDebug(5, Form("addr=0x%04x (%s) data=0x%08x\n", caddr, GetRegName(GetRegByAddress(caddr)), header & msk));
960 if ( ! Poke(caddr, header & msk, 0, 0, 0) )
961 AliDebug(5, Form("(single-write): non-existing address 0x%04x containing 0x%08x\n", caddr, header));
962
963 caddr += step;
964 header = header >> bwidth;
965 if (idx >= size)
966 {
967 AliDebug(5, Form("(block-write): no end marker! %d words read\n", idx));
968 return -err;
969 }
970 }
971 break;
972 } // end case 5-15
973 case 31:
974 {
975 while (nwords > 0)
976 {
977 header = *data;
978 AliDebug(5, Form("read 0x%08x", header));
979 data++;
980 idx++;
981 nwords--;
982 err += (header & 1);
983
984 AliDebug(5, Form("addr=0x%04x (%s) data=0x%08x", caddr, GetRegName(GetRegByAddress(caddr)), header >> 1));
985 if ( ! Poke(caddr, header >> 1, 0, 0, 0) )
986 AliDebug(5, Form("(single-write): non-existing address 0x%04x containing 0x%08x\n", caddr, header));
987
988 caddr += step;
989 if (idx >= size)
990 {
991 AliDebug(5, Form("no end marker! %d words read", idx));
992 return -err;
993 }
994 }
995 break;
996 }
997 default: return err;
998 } // end switch
999 } // end block case
1000 } // end while
1001 AliDebug(5, Form("no end marker! %d words read", idx));
1002 return -err; // only if the max length of the block reached!
1003}
1004
1005
1006Bool_t AliTRDtrapConfig::PrintTrapReg(TrapReg_t reg, Int_t det, Int_t rob, Int_t mcm)
1007{
1008 // print the value stored in the given register
1009 // if it is individual a valid MCM has to be specified
1010
1011 if (fRegisterValue[reg].state == RegValue_t::kGlobal) {
1012 printf("%s (%i bits) at 0x%08x is 0x%08x and resets to: 0x%08x (currently global mode)\n",
1013 GetRegName((TrapReg_t) reg),
1014 GetRegNBits((TrapReg_t) reg),
1015 GetRegAddress((TrapReg_t) reg),
1016 fRegisterValue[reg].globalValue,
1017 GetRegResetValue((TrapReg_t) reg));
1018 }
1019 else if (fRegisterValue[reg].state == RegValue_t::kIndividual) {
1020 if((det >= 0 && det < AliTRDgeometry::Ndet()) &&
1021 (rob >= 0 && rob < AliTRDfeeParam::GetNrobC1()) &&
1022 (mcm >= 0 && mcm < fgkMaxMcm)) {
1023 printf("%s (%i bits) at 0x%08x is 0x%08x and resets to: 0x%08x (currently individual mode)\n",
1024 GetRegName((TrapReg_t) reg),
1025 GetRegNBits((TrapReg_t) reg),
1026 GetRegAddress((TrapReg_t) reg),
1027 fRegisterValue[reg].individualValue[det*AliTRDfeeParam::GetNrobC1()*fgkMaxMcm + rob*fgkMaxMcm + mcm],
1028 GetRegResetValue((TrapReg_t) reg));
1029 }
1030 else {
1031 AliError("Register value is MCM-specific: Invalid detector, ROB or MCM requested");
1032 return kFALSE;
1033 }
1034 }
1035 else { // should never be reached
1036 AliError("MCM register status neither kGlobal nor kIndividual");
1037 return kFALSE;
1038 }
1039 return kTRUE;
1040}
1041
1042
1043Bool_t AliTRDtrapConfig::PrintTrapAddr(Int_t addr, Int_t det, Int_t rob, Int_t mcm)
1044{
1045 // print the value stored at the given address in the MCM chip
1046 TrapReg_t reg = GetRegByAddress(addr);
1047 if (reg >= 0 && reg < kLastReg) {
1048 return PrintTrapReg(reg, det, rob, mcm);
1049 }
1050 else {
1051 AliError(Form("There is no register at address 0x%08x in the simulator", addr));
1052 return kFALSE;
1053 }
1054}
1055
1056
1057Bool_t AliTRDtrapConfig::AddValues(UInt_t det, UInt_t cmd, UInt_t extali, Int_t addr, UInt_t data)
1058{
1059 // transfer the informations provided by LoadConfig to the internal class variables
1060
1061 if(cmd != fgkScsnCmdWrite) {
1062 AliError(Form("Invalid command received: %i", cmd));
1063 return kFALSE;
1064 }
1065
1066 TrapReg_t mcmReg = GetRegByAddress(addr);
1067 Int_t rocType = AliTRDgeometry::GetStack(det) == 2 ? 0 : 1;
1068
1069 // configuration registers
1070 if(mcmReg >= 0 && mcmReg < kLastReg) {
1071
1072 for(Int_t linkPair=0; linkPair<fgkMaxLinkPairs; linkPair++) {
1073 if(ExtAliToAli(extali, linkPair, rocType)!=0) {
1074 Int_t i=0;
1075 while(fMcmlist[i] != -1 && i<fgkMcmlistSize) {
1076 if(fMcmlist[i]==127)
1077 SetTrapReg( (TrapReg_t) mcmReg, data, det);
1078 else
1079 SetTrapReg( (TrapReg_t) mcmReg, data, det, (fMcmlist[i]>>7), (fMcmlist[i]&0x7F));
1080 i++;
1081 }
1082 }
1083 }
1084 return kTRUE;
1085 }
1086 // DMEM
1087 else if ( (addr >= fgkDmemStartAddress) &&
1088 (addr < (fgkDmemStartAddress + fgkDmemWords))) {
1089 for(Int_t linkPair=0; linkPair<fgkMaxLinkPairs; linkPair++) {
1090 if(ExtAliToAli(extali, linkPair, rocType)!=0) {
1091 Int_t i=0;
1092 while(fMcmlist[i] != -1 && i < fgkMcmlistSize) {
1093 if(fMcmlist[i] == 127)
1094 // fDmem[0][addr - fgkDmemStartAddress] = data;
1095 SetDmem(addr, data, det);
1096 else
1097 // fDmem[det*AliTRDfeeParam::GetNrobC1()*fgkMaxMcm + (fMcmlist[i] >> 7)*fgkMaxMcm + (fMcmlist[i]&0x7f)]
1098 // [addr - fgkDmemStartAddress] = data;
1099 SetDmem(addr, data, det, fMcmlist[i] >> 7, fMcmlist[i] & 0x7f);
1100 i++;
1101 }
1102 }
1103 }
1104 return kTRUE;
1105 }
1106 else
1107 return kFALSE;
1108}
1109
1110
1111Int_t AliTRDtrapConfig::ExtAliToAli( UInt_t dest, UShort_t linkpair, UShort_t rocType)
1112{
1113 // Converts an extended ALICE ID which identifies a single MCM or a group of MCMs to
1114 // the corresponding list of MCMs. Only broadcasts (127) are encoded as 127
1115 // The return value is the number of MCMs in the list
1116
1117 fMcmlist[0]=-1;
1118
1119 Short_t nmcm = 0;
1120 UInt_t mcm, rob, robAB;
1121 UInt_t cmA = 0, cmB = 0; // Chipmask for each A and B side
1122
1123 // Default chipmask for 4 linkpairs (each bit correponds each alice-mcm)
1124 static const UInt_t gkChipmaskDefLp[4] = { 0x1FFFF, 0x1FFFF, 0x3FFFF, 0x1FFFF };
1125
1126 rob = dest >> 7; // Extract ROB pattern from dest.
1127 mcm = dest & 0x07F; // Extract MCM pattern from dest.
1128 robAB = GetRobAB( rob, linkpair ); // Get which ROB sides are selected.
1129
1130 // Abort if no ROB is selected
1131 if( robAB == 0 ) {
1132 return 0;
1133 }
1134
1135 // Special case
1136 if( mcm == 127 ) {
1137 if( robAB == 3 ) { // This is very special 127 can stay only if two ROBs are selected
1138 fMcmlist[0]=127; // broadcase to ALL
1139 fMcmlist[1]=-1;
1140 return 1;
1141 }
1142 cmA = cmB = 0x3FFFF;
1143 } else if( (mcm & 0x40) != 0 ) { // If top bit is 1 but not 127, this is chip group.
1144 if( (mcm & 0x01) != 0 ) { cmA |= 0x04444; cmB |= 0x04444; } // chip_cmrg
1145 if( (mcm & 0x02) != 0 ) { cmA |= 0x10000; cmB |= 0x10000; } // chip_bmrg
1146 if( (mcm & 0x04) != 0 && rocType == 0 ) { cmA |= 0x20000; cmB |= 0x20000; } // chip_hm3
1147 if( (mcm & 0x08) != 0 && rocType == 1 ) { cmA |= 0x20000; cmB |= 0x20000; } // chip_hm4
1148 if( (mcm & 0x10) != 0 ) { cmA |= 0x01111; cmB |= 0x08888; } // chip_edge
1149 if( (mcm & 0x20) != 0 ) { cmA |= 0x0aaaa; cmB |= 0x03333; } // chip_norm
1150 } else { // Otherwise, this is normal chip ID, turn on only one chip.
1151 cmA = 1 << mcm;
1152 cmB = 1 << mcm;
1153 }
1154
1155 // Mask non-existing MCMs
1156 cmA &= gkChipmaskDefLp[linkpair];
1157 cmB &= gkChipmaskDefLp[linkpair];
1158 // Remove if only one side is selected
1159 if( robAB == 1 )
1160 cmB = 0;
1161 if( robAB == 2 )
1162 cmA = 0;
1163 if( robAB == 4 && linkpair != 2 )
1164 cmA = cmB = 0; // Restrict to only T3A and T3B
1165
1166 // Finally convert chipmask to list of slaves
1167 nmcm = ChipmaskToMCMlist( cmA, cmB, linkpair );
1168
1169 return nmcm;
1170}
1171
1172
1173Short_t AliTRDtrapConfig::GetRobAB( UShort_t robsel, UShort_t linkpair ) const
1174{
1175 // Converts the ROB part of the extended ALICE ID to robs
1176
1177 if( (robsel & 0x8) != 0 ) { // 1000 .. direct ROB selection. Only one of the 8 ROBs are used.
1178 robsel = robsel & 7;
1179 if( (robsel % 2) == 0 && (robsel / 2) == linkpair )
1180 return 1; // Even means A side (position 0,2,4,6)
1181 if( (robsel % 2) == 1 && (robsel / 2) == linkpair )
1182 return 2; // Odd means B side (position 1,3,5,7)
1183 return 0;
1184 }
1185
1186 // ROB group
1187 if( robsel == 0 ) { return 3; } // Both ROB
1188 if( robsel == 1 ) { return 1; } // A-side ROB
1189 if( robsel == 2 ) { return 2; } // B-side ROB
1190 if( robsel == 3 ) { return 3; } // Both ROB
1191 if( robsel == 4 ) { return 4; } // Only T3A and T3B
1192 // Other number 5 to 7 are ignored (not defined)
1193
1194 return 0;
1195}
1196
1197
1198Short_t AliTRDtrapConfig::ChipmaskToMCMlist( Int_t cmA, Int_t cmB, UShort_t linkpair )
1199{
1200 // Converts the chipmask to a list of MCMs
1201
1202 Short_t nmcm = 0;
1203 Short_t i;
1204 for( i = 0 ; i < fgkMaxMcm ; i++ ) {
1205 if( (cmA & (1 << i)) != 0 ) {
1206 fMcmlist[nmcm] = ((linkpair*2) << 7) | i;
1207 ++nmcm;
1208 }
1209 if( (cmB & (1 << i)) != 0 ) {
1210 fMcmlist[nmcm] = ((linkpair*2+1) << 7) | i;
1211 ++nmcm;
1212 }
1213 }
1214
1215 fMcmlist[nmcm]=-1;
1216 return nmcm;
1217}
1218
1219
1220AliTRDtrapConfig::TrapReg_t AliTRDtrapConfig::GetRegByAddress(Int_t address) const
1221{
36dc3337 1222 // get register by its address
1223 // used for reading of configuration data as sent to real FEE
1224
ce4786b9 1225 TrapReg_t mcmReg = kLastReg;
1226 Int_t reg = 0;
1227 do {
1228 if(fRegs[reg].fAddr == address)
1229 mcmReg = (TrapReg_t) reg;
1230 reg++;
1231 } while (mcmReg == kLastReg && reg < kLastReg);
1232
1233 return mcmReg;
1234}
1235
1236