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Commit | Line | Data |
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f9720615 | 1 | # |
2 | # Pre-trigger run time parameter example file | |
3 | # which should be generated by PVSS tag editor panels | |
4 | # | |
5 | ||
6 | # Configuration infos | |
7 | TAG 120 | |
8 | REVISION 123 | |
9 | TIMESTAMP/CREATION YYYY-MM-DD hh:mm:ss | |
10 | TIMESTAMP/LASTUPDATE YYYY-MM-DD hh:mm:ss | |
11 | COMMENT example configuration (2010-03-31) changes according to PT meeting | |
12 | ||
13 | # TLMU input masks | |
14 | TLMU/IMASK/SEC00 1111_1111_1111_1111_1111_1111_1111_1111 | |
15 | TLMU/IMASK/SEC01 1111_1111_1111_1111_1111_1111_1111_1111 | |
16 | TLMU/IMASK/SEC02 1111_1111_1111_1111_1111_1111_1111_1111 | |
17 | TLMU/IMASK/SEC03 1111_1111_1111_1111_1111_1111_1111_1111 | |
18 | TLMU/IMASK/SEC04 1111_1111_1111_1111_1111_1111_1111_1111 | |
19 | TLMU/IMASK/SEC05 1111_1111_1111_1111_1111_1111_1111_1111 | |
20 | TLMU/IMASK/SEC06 1111_1111_1111_1111_1111_1111_1111_1111 | |
21 | TLMU/IMASK/SEC07 1111_1111_1111_1111_1111_1111_1111_1111 | |
22 | TLMU/IMASK/SEC08 1111_1111_1111_1111_1111_1111_1111_1111 | |
23 | TLMU/IMASK/SEC09 1111_1111_1111_1111_1111_1111_1111_1111 | |
24 | TLMU/IMASK/SEC10 1111_1111_1111_1111_1111_1111_1111_1111 | |
25 | TLMU/IMASK/SEC11 1111_1111_1111_1111_1111_1111_1111_1111 | |
26 | TLMU/IMASK/SEC12 1111_1111_1111_1111_1111_1111_1111_1111 | |
27 | TLMU/IMASK/SEC13 1111_1111_1111_1111_1111_1111_1111_1111 | |
28 | TLMU/IMASK/SEC14 1111_1111_1111_1111_1111_1111_1111_1111 | |
29 | TLMU/IMASK/SEC15 1111_1111_1111_1111_1111_1111_1111_1111 | |
30 | TLMU/IMASK/SEC17 1111_1111_1111_1111_1111_1111_1111_1111 | |
31 | ||
32 | # How long input if stretched. Value can be 0 to 3 | |
33 | TLMU/STRETCH 1 | |
34 | ||
35 | # Coincidence matrices set (there are three) (if not set, not activated) | |
36 | ||
37 | TLMU/CMATRIX0/SEC00 00_0000_0010_0000_0001 | |
38 | TLMU/CMATRIX0/SEC01 00_0000_0100_0000_0010 | |
39 | TLMU/CMATRIX0/SEC02 00_0000_1000_0000_0100 | |
40 | TLMU/CMATRIX0/SEC03 00_0001_0000_0000_1000 | |
41 | TLMU/CMATRIX0/SEC04 00_0010_0000_0001_0000 | |
42 | TLMU/CMATRIX0/SEC05 00_0100_0000_0010_0000 | |
43 | TLMU/CMATRIX0/SEC06 00_1000_0000_0100_0000 | |
44 | TLMU/CMATRIX0/SEC07 01_0000_0000_1000_0000 | |
45 | TLMU/CMATRIX0/SEC08 10_0000_0001_0000_0000 | |
46 | ||
47 | TLMU/CMATRIX1/SEC00 00_0000_0111_0000_0001 | |
48 | TLMU/CMATRIX1/SEC01 00_0000_1110_0000_0010 | |
49 | TLMU/CMATRIX1/SEC02 00_0001_1100_0000_0100 | |
50 | TLMU/CMATRIX1/SEC03 00_0011_1000_0000_1000 | |
51 | TLMU/CMATRIX1/SEC04 00_0111_0000_0001_0000 | |
52 | TLMU/CMATRIX1/SEC05 00_1110_0000_0010_0000 | |
53 | TLMU/CMATRIX1/SEC06 01_1100_0000_0100_0000 | |
54 | TLMU/CMATRIX1/SEC07 11_1000_0000_1000_0000 | |
55 | TLMU/CMATRIX1/SEC08 11_0000_0001_0000_0001 | |
56 | TLMU/CMATRIX1/SEC09 10_0000_0010_0000_0011 | |
57 | TLMU/CMATRIX1/SEC10 00_0000_0100_0000_0111 | |
58 | TLMU/CMATRIX1/SEC11 00_0000_1000_0000_1110 | |
59 | TLMU/CMATRIX1/SEC12 00_0001_0000_0001_1100 | |
60 | TLMU/CMATRIX1/SEC13 00_0010_0000_0011_1000 | |
61 | TLMU/CMATRIX1/SEC14 00_0100_0000_0111_0000 | |
62 | TLMU/CMATRIX1/SEC15 00_1000_0000_1110_0000 | |
63 | TLMU/CMATRIX1/SEC16 01_0000_0001_1100_0000 | |
64 | TLMU/CMATRIX1/SEC17 10_0000_0011_1000_0000 | |
65 | ||
66 | ||
67 | TLMU/CMATRIX2/SEC00 00_0000_1111_1000_0001 | |
68 | TLMU/CMATRIX2/SEC01 00_0001_1111_0000_0010 | |
69 | TLMU/CMATRIX2/SEC02 00_0011_1110_0000_0100 | |
70 | TLMU/CMATRIX2/SEC03 00_0111_1100_0000_1000 | |
71 | TLMU/CMATRIX2/SEC04 00_1111_1000_0001_0000 | |
72 | TLMU/CMATRIX2/SEC05 01_1111_0000_0010_0000 | |
73 | TLMU/CMATRIX2/SEC06 11_1110_0000_0100_0000 | |
74 | TLMU/CMATRIX2/SEC07 11_1100_0000_1000_0001 | |
75 | TLMU/CMATRIX2/SEC08 11_1000_0001_0000_0011 | |
76 | TLMU/CMATRIX2/SEC09 11_0000_0010_0000_0111 | |
77 | TLMU/CMATRIX2/SEC10 10_0000_0100_0000_1111 | |
78 | TLMU/CMATRIX2/SEC11 00_0000_1000_0001_1111 | |
79 | TLMU/CMATRIX2/SEC12 00_0001_0000_0011_1110 | |
80 | TLMU/CMATRIX2/SEC13 00_0010_0000_0111_1100 | |
81 | TLMU/CMATRIX2/SEC14 00_0100_0000_1111_1000 | |
82 | TLMU/CMATRIX2/SEC15 00_1000_0001_1111_0000 | |
83 | TLMU/CMATRIX2/SEC16 01_0000_0011_1110_0000 | |
84 | TLMU/CMATRIX2/SEC17 10_0000_0111_1100_0000 | |
85 | ||
86 | ||
87 | # Multiplicity counter setup (where to slice) . | |
88 | # there are 9 slices with lower and upper thresholds | |
89 | TLMU/MCNTR0/THR 5 20 | |
90 | TLMU/MCNTR1/THR 20 100 | |
91 | TLMU/MCNTR2/THR 100 200 | |
92 | TLMU/MCNTR3/THR 200 300 | |
93 | TLMU/MCNTR4/THR 300 400 | |
94 | TLMU/MCNTR5/THR 400 500 | |
95 | TLMU/MCNTR6/THR 500 520 | |
e51605d9 | 96 | TLMU/MCNTR7/THR 520 576 |
97 | TLMU/MCNTR8/THR 1 576 | |
f9720615 | 98 | |
99 | ||
100 | # Assign signal to output. CM means CMATRIX and MC means Multiplicity counter | |
101 | # SEQ [0..4] means trigger sequencer. NONE will not assign anything | |
102 | # | |
103 | # channel 0 1 2 3 4 5 6 7 | |
104 | TLMU/OUTMUX CM1 MC2 MC3 MC4 MC5 MC6 MC7 MC8 | |
105 | ||
106 | # FEBs | |
107 | ||
108 | # basically thresholds and delay (T0 has 12 channels, and V0 has 8 channels) | |
109 | # V0 has 4 sections named V0, V1, V2, V3 | |
110 | # Delay is 0 to 31, with 1/4 BC precision (max delay is then 8 BCs) | |
111 | # The value can take here is from 0 to 255 for threshold and 0 to 31 for delay | |
112 | ||
113 | FEB/T0/A/THR 10 10 10 10 10 10 10 10 10 10 10 10 | |
114 | FEB/T0/A/DELAY 1 1 1 1 1 1 1 1 1 1 1 1 | |
115 | FEB/T0/C/THR 10 10 10 10 10 10 10 10 10 10 10 10 | |
116 | FEB/T0/C/DELAY 1 1 1 1 1 1 1 1 1 1 1 1 | |
117 | ||
118 | FEB/V0/A0/THR 10 10 10 10 10 10 10 10 | |
119 | FEB/V0/A1/THR 10 10 10 10 10 10 10 10 | |
120 | FEB/V0/A2/THR 10 10 10 10 10 10 10 10 | |
121 | FEB/V0/A3/THR 10 10 10 10 10 10 10 10 | |
122 | ||
123 | FEB/V0/A0/DELAY 1 1 1 1 1 1 1 1 | |
124 | FEB/V0/A1/DELAY 1 1 1 1 1 1 1 1 | |
125 | FEB/V0/A2/DELAY 1 1 1 1 1 1 1 1 | |
126 | FEB/V0/A3/DELAY 1 1 1 1 1 1 1 1 | |
127 | ||
128 | FEB/V0/C0/THR 10 10 10 10 10 10 10 10 | |
129 | FEB/V0/C1/THR 10 10 10 10 10 10 10 10 | |
130 | FEB/V0/C2/THR 10 10 10 10 10 10 10 10 | |
131 | FEB/V0/C3/THR 10 10 10 10 10 10 10 10 | |
132 | ||
133 | FEB/V0/C0/DELAY 1 1 1 1 1 1 1 1 | |
134 | FEB/V0/C1/DELAY 1 1 1 1 1 1 1 1 | |
135 | FEB/V0/C2/DELAY 1 1 1 1 1 1 1 1 | |
136 | FEB/V0/C3/DELAY 1 1 1 1 1 1 1 1 | |
137 | ||
138 | # Lookup table at FEB | |
139 | ||
140 | FEB/T0/A/LUT/0 M(1111_1111_1111)>0 # maybe also logical equations | |
141 | FEB/T0/A/LUT/1 M(1111_1111_1111)>4 | |
142 | ||
143 | FEB/V0/A0/LUT/0 M(1111_1111)>0 | |
144 | FEB/V0/A0/LUT/1 M(1111_1111)>2 | |
145 | FEB/V0/A1/LUT/0 M(1111_1111)>0 | |
146 | FEB/V0/A1/LUT/1 M(1111_1111)>2 | |
147 | FEB/V0/A2/LUT/0 M(1111_1111)>0 | |
148 | FEB/V0/A2/LUT/1 M(1111_1111)>2 | |
149 | FEB/V0/A3/LUT/0 M(1111_1111)>0 | |
150 | FEB/V0/A3/LUT/1 M(1111_1111)>2 | |
151 | ||
152 | FEB/T0/C/LUT/0 M(1111_1111_1111)>0 | |
153 | FEB/T0/C/LUT/1 M(1111_1111_1111)>4 | |
154 | ||
155 | FEB/V0/C0/LUT/0 M(1111_1111)>0 | |
156 | FEB/V0/C0/LUT/1 M(1111_1111)>2 | |
157 | FEB/V0/C1/LUT/0 M(1111_1111)>0 | |
158 | FEB/V0/C1/LUT/1 M(1111_1111)>2 | |
159 | FEB/V0/C2/LUT/0 M(1111_1111)>0 | |
160 | FEB/V0/C2/LUT/1 M(1111_1111)>2 | |
161 | FEB/V0/C3/LUT/0 M(1111_1111)>0 | |
162 | FEB/V0/C3/LUT/1 M(1111_1111)>2 | |
163 | ||
164 | # Lookup table at CB-AC | |
165 | ||
166 | CBA/LUT/0 T0_0 || ( V0-0_0 || V0-1_0 || V0-2_0 || V0-3_0 ) | |
167 | CBA/LUT/1 !T0_1 && !V0-0_1 && !V0-1_1 && !V0-2_1 && !V0-3_1 | |
168 | ||
169 | CBC/LUT/0 T0_0 || ( V0-0_0 || V0-1_0 || V0-2_0 || V0-3_0 ) | |
170 | CBC/LUT/1 !T0_1 && !V0-0_1 && !V0-1_1 && !V0-2_1 && !V0-3_1 | |
171 | ||
172 | # Lookup table at CB-B | |
173 | ||
7788992c | 174 | CBB/LUT/0 ( CB-A_1 && !CB-C_1 ) && TLMU_7 |
175 | CBB/LUT/1 ( !CB-A_1 && CB-C_1 ) && TLMU_7 | |
176 | CBB/LUT/2 ( CB-A_1 && CB-C_1 ) && TLMU_7 | |
f9720615 | 177 | |
178 | # Timing parameter for trigger processor | |
179 | ||
180 | CBB/TRG/L0A 43 # comment | |
181 | CBB/TRG/L0S 47 | |
182 | CBB/TRG/L1A 308 | |
183 | CBB/TRG/L1S 311 | |
184 | CBB/TRG/DEAD/PT 200 | |
185 | CBB/TRG/DEAD/L0 350 | |
186 | CBB/TRG/DEAD/L1 500 | |
187 | CBB/TRG/DELAY/L0 46 | |
188 | ||
189 | CBB/TRG/CTRL/SM_TO_CTP YES | |
190 | CBB/TRG/CTRL/TRG_EMU YES | |
191 | CBB/TRG/CTRL/A/VALUE 0 | |
192 | CBB/TRG/CTRL/A/OVR NO | |
193 | CBB/TRG/CTRL/B/VALUE 0 | |
194 | CBB/TRG/CTRL/B/OVR NO | |
195 | ||
196 | CBB/TRG/A/DIS YES # do not change! | |
197 | ||
198 | CBB/TRG/TIN/0 0 # normal triggering (should be 0!) | |
199 | CBB/TRG/TIN/1 0 # normal triggering (should be 0!) | |
200 | ||
201 | CBB/PT/CBA/SAMPL 0 | |
202 | CBB/PT/CBC/SAMPL 0 | |
203 | ||
204 | ||
205 | CBB/PT/ALIGN/CB-A_0/STRETCH 0 | |
206 | CBB/PT/ALIGN/CB-A_0/DELAY 0 | |
207 | CBB/PT/ALIGN/CB-A_1/STRETCH 0 | |
208 | CBB/PT/ALIGN/CB-A_1/DELAY 0 | |
209 | CBB/PT/ALIGN/CB-C_0/STRETCH 0 | |
210 | CBB/PT/ALIGN/CB-C_0/DELAY 0 | |
211 | CBB/PT/ALIGN/CB-C_1/STRETCH 0 | |
212 | CBB/PT/ALIGN/CB-C_1/DELAY 0 | |
213 | CBB/PT/ALIGN/RND/STRETCH 0 | |
214 | CBB/PT/ALIGN/RND/DELAY 0 | |
215 | CBB/PT/ALIGN/BC/STRETCH 0 | |
216 | CBB/PT/ALIGN/BC/DELAY 0 | |
217 | CBB/PT/ALIGN/TLMU_0/STRETCH 0 | |
218 | CBB/PT/ALIGN/TLMU_0/DELAY 0 | |
219 | CBB/PT/ALIGN/TLMU_1/STRETCH 0 | |
220 | CBB/PT/ALIGN/TLMU_1/DELAY 0 | |
221 | CBB/PT/ALIGN/TLMU_2/STRETCH 0 | |
222 | CBB/PT/ALIGN/TLMU_2/DELAY 0 | |
223 | CBB/PT/ALIGN/TLMU_3/STRETCH 0 | |
224 | CBB/PT/ALIGN/TLMU_3/DELAY 0 | |
225 | CBB/PT/ALIGN/TLMU_4/STRETCH 0 | |
226 | CBB/PT/ACBB/LIGN/TLMU_4/DELAY 0 | |
227 | CBB/PT/ALIGN/TLMU_5/STRETCH 0 | |
228 | CBB/PT/ALIGN/TLMU_5/DELAY 0 | |
229 | CBB/PT/ALIGN/TLMU_6/STRETCH 0 | |
230 | CBB/PT/ALIGN/TLMU_6/DELAY 0 | |
231 | CBB/PT/ALIGN/TLMU_7/STRETCH 0 | |
232 | CBB/PT/ALIGN/TLMU_7/DELAY 0 | |
233 | CBB/PT/ALIGN/CB-B_0/STRETCH 0 | |
234 | CBB/PT/ALIGN/CB-B_0/DELAY 0 | |
235 | CBB/PT/ALIGN/CB-B_1/STRETCH 0 | |
236 | CBB/PT/ALIGN/CB-B_1/DELAY 0 | |
237 | ||
238 | CBB/BUSY/CTRL 0 | |
239 | ||
240 | CBB/RND/THR 150000 | |
241 | CBB/BC/RESET_VALUE 222 | |
242 | ||
243 | CBB/PT/MASK/CB-A_0 YES | |
7788992c | 244 | CBB/PT/MASK/CB-A_1 NO |
f9720615 | 245 | CBB/PT/MASK/CB-C_0 YES |
7788992c | 246 | CBB/PT/MASK/CB-C_1 NO |
247 | CBB/PT/MASK/RND NO | |
248 | CBB/PT/MASK/BC NO | |
f9720615 | 249 | CBB/PT/MASK/TLMU_0 YES |
250 | CBB/PT/MASK/TLMU_1 YES | |
251 | CBB/PT/MASK/TLMU_2 YES | |
252 | CBB/PT/MASK/TLMU_3 YES | |
253 | CBB/PT/MASK/TLMU_4 YES | |
254 | CBB/PT/MASK/TLMU_5 YES | |
255 | CBB/PT/MASK/TLMU_6 YES | |
7788992c | 256 | CBB/PT/MASK/TLMU_7 NO |
f9720615 | 257 | CBB/PT/MASK/CB-B_0 YES |
258 | CBB/PT/MASK/CB-B_1 YES | |
7788992c | 259 | CBB/PT/MASK/CB-B_2 YES |
f9720615 | 260 | |
261 | # EOF |